sun4i_emac.c revision 1.2.2.2
1 /* $NetBSD: sun4i_emac.c,v 1.2.2.2 2017/12/03 11:35:56 jdolecek Exp $ */ 2 3 /*- 4 * Copyright (c) 2013-2017 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry and Jared McNeill. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 34 __KERNEL_RCSID(1, "$NetBSD: sun4i_emac.c,v 1.2.2.2 2017/12/03 11:35:56 jdolecek Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/bus.h> 38 #include <sys/device.h> 39 #include <sys/intr.h> 40 #include <sys/ioctl.h> 41 #include <sys/mutex.h> 42 #include <sys/rndsource.h> 43 #include <sys/kernel.h> 44 #include <sys/systm.h> 45 46 #include <net/bpf.h> 47 #include <net/if.h> 48 #include <net/if_dl.h> 49 #include <net/if_ether.h> 50 #include <net/if_media.h> 51 52 #include <dev/mii/miivar.h> 53 54 #include <dev/fdt/fdtvar.h> 55 56 #include <arm/sunxi/sunxi_sramc.h> 57 58 #define EMAC_IFNAME "emac%d" 59 60 #define EMAC_CTL_REG 0x00 61 #define EMAC_CTL_RX_EN __BIT(2) 62 #define EMAC_CTL_TX_EN __BIT(1) 63 #define EMAC_CTL_RST __BIT(0) 64 #define EMAC_TX_MODE_REG 0x04 65 #define EMAC_TX_MODE_DMA __BIT(1) 66 #define EMAC_TX_MODE_ABF_ENA __BIT(0) 67 #define EMAC_TX_FLOW_REG 0x08 68 #define EMAC_TX_CTL0_REG 0x0c 69 #define EMAC_TX_CTL1_REG 0x10 70 #define EMAC_TX_CTL_REG(n) (EMAC_TX_CTL0_REG+4*(n)) 71 #define EMAC_TX_CTL_START __BIT(0) 72 #define EMAC_TX_INS_REG 0x14 73 #define EMAC_TX_PL0_REG 0x18 74 #define EMAC_TX_PL1_REG 0x1c 75 #define EMAC_TX_PL_REG(n) (EMAC_TX_PL0_REG+4*(n)) 76 #define EMAC_TX_STA_REG 0x20 77 #define EMAC_TX_IO_DATA0_REG 0x24 78 #define EMAC_TX_IO_DATA1_REG 0x28 79 #define EMAC_TX_IO_DATA_REG(n) (EMAC_TX_IO_DATA0_REG+4*(n)) 80 #define EMAC_TX_TSVL0_REG 0x2c 81 #define EMAC_TX_TSVH0_REG 0x30 82 #define EMAC_TX_TSVL1_REG 0x34 83 #define EMAC_TX_TSVH1_REG 0x38 84 #define EMAC_RX_CTL_REG 0x3c 85 #define EMAC_RX_CTL_SA_IF __BIT(25) 86 #define EMAC_RX_CTL_SA __BIT(24) 87 #define EMAC_RX_CTL_BC0 __BIT(22) 88 #define EMAC_RX_CTL_MHF __BIT(21) 89 #define EMAC_RX_CTL_MC0 __BIT(20) 90 #define EMAC_RX_CTL_DAF __BIT(17) 91 #define EMAC_RX_CTL_UCAD __BIT(16) 92 #define EMAC_RX_CTL_POR __BIT(8) 93 #define EMAC_RX_CTL_PLE __BIT(7) 94 #define EMAC_RX_CTL_PCRCE __BIT(6) 95 #define EMAC_RX_CTL_PCF __BIT(5) 96 #define EMAC_RX_CTL_PROMISC __BIT(4) 97 #define EMAC_RX_CTL_FIFO_RESET __BIT(3) 98 #define EMAC_RX_CTL_DMA __BIT(2) 99 #define EMAC_RX_CTL_DRQ_MODE __BIT(1) 100 #define EMAC_RX_CTL_START __BIT(0) 101 #define EMAC_RX_HASH0_REG 0x40 102 #define EMAC_RX_HASH1_REG 0x44 103 #define EMAC_RX_STA_REG 0x48 104 #define EMAC_RX_STA_PKTOK __BIT(7) 105 #define EMAC_RX_STA_ALNERR __BIT(6) 106 #define EMAC_RX_STA_LENERR __BIT(5) 107 #define EMAC_RX_STA_CRCERR __BIT(4) 108 #define EMAC_RX_IO_DATA_REG 0x4c 109 #define EMAC_RX_FBC_REG 0x50 110 #define EMAC_INT_CTL_REG 0x54 111 #define EMAC_INT_STA_REG 0x58 112 #define EMAC_INT_RX __BIT(8) 113 #define EMAC_INT_TX1 __BIT(1) 114 #define EMAC_INT_TX0 __BIT(0) 115 #define EMAC_INT_ENABLE \ 116 (EMAC_INT_RX|EMAC_INT_TX1|EMAC_INT_TX0) 117 #define EMAC_MAC_CTL0_REG 0x5c 118 #define EMAC_MAC_CTL0_SOFT_RESET __BIT(15) 119 #define EMAC_MAC_CTL0_TFC __BIT(3) 120 #define EMAC_MAC_CTL0_RFC __BIT(2) 121 #define EMAC_MAC_CTL1_REG 0x60 122 #define EMAC_MAC_CTL1_ED __BIT(15) 123 #define EMAC_MAC_CTL1_NB __BIT(13) 124 #define EMAC_MAC_CTL1_BNB __BIT(12) 125 #define EMAC_MAC_CTL1_LPE __BIT(9) 126 #define EMAC_MAC_CTL1_PRE __BIT(8) 127 #define EMAC_MAC_CTL1_ADP __BIT(7) 128 #define EMAC_MAC_CTL1_VC __BIT(6) 129 #define EMAC_MAC_CTL1_PC __BIT(5) 130 #define EMAC_MAC_CTL1_CRC __BIT(4) 131 #define EMAC_MAC_CTL1_DCRC __BIT(3) 132 #define EMAC_MAC_CTL1_HF __BIT(2) 133 #define EMAC_MAC_CTL1_FLC __BIT(1) 134 #define EMAC_MAC_CTL1_FD __BIT(0) 135 #define EMAC_MAC_IPGT_REG 0x64 136 #define EMAC_MAC_IPGT_FD 0x15 137 #define EMAC_MAC_IPGR_REG 0x68 138 #define EMAC_MAC_IPGR_IPG1 __BITS(15,8) 139 #define EMAC_MAC_IPGR_IPG2 __BITS(7,0) 140 #define EMAC_MAC_CLRT_REG 0x6c 141 #define EMAC_MAC_CLRT_CW __BITS(15,8) 142 #define EMAC_MAC_CLRT_RM __BITS(7,0) 143 #define EMAC_MAC_MAXF_REG 0x70 144 #define EMAC_MAC_SUPP_REG 0x74 145 #define EMAC_MAC_SUPP_100M __BIT(8) 146 #define EMAC_MAC_TEST_REG 0x78 147 #define EMAC_MAC_MCFG_REG 0x7c 148 #define EMAC_MAC_MCFG_CLK __BITS(5,2) 149 #define EMAC_MAC_MCMD_REG 0x80 150 #define EMAC_MAC_MADR_REG 0x84 151 #define EMAC_MAC_MWTD_REG 0x88 152 #define EMAC_MAC_MRDD_REG 0x8c 153 #define EMAC_MAC_MIND_REG 0x90 154 #define EMAC_MAC_SSRR_REG 0x94 155 #define EMAC_MAC_A0_REG 0x98 156 #define EMAC_MAC_A1_REG 0x9c 157 #define EMAC_MAC_A2_REG 0xa0 158 159 #define EMAC_RXHDR_STS __BITS(31,16) 160 #define EMAC_RXHDR_LEN __BITS(15,0) 161 162 #define EMAC_RX_MAGIC 0x0143414d /* M A C \001 */ 163 164 #define EMAC_TXBUF_SIZE 4096 165 166 static int sun4i_emac_match(device_t, cfdata_t, void *); 167 static void sun4i_emac_attach(device_t, device_t, void *); 168 169 static int sun4i_emac_intr(void *); 170 static void sun4i_emac_tick(void *); 171 172 static int sun4i_emac_miibus_read_reg(device_t, int, int); 173 static void sun4i_emac_miibus_write_reg(device_t, int, int, int); 174 static void sun4i_emac_miibus_statchg(struct ifnet *); 175 176 static void sun4i_emac_ifstart(struct ifnet *); 177 static int sun4i_emac_ifioctl(struct ifnet *, u_long, void *); 178 static int sun4i_emac_ifinit(struct ifnet *); 179 static void sun4i_emac_ifstop(struct ifnet *, int); 180 static void sun4i_emac_ifwatchdog(struct ifnet *); 181 182 struct sun4i_emac_softc; 183 static void sun4i_emac_rx_hash(struct sun4i_emac_softc *); 184 185 struct sun4i_emac_softc { 186 device_t sc_dev; 187 int sc_phandle; 188 bus_space_tag_t sc_bst; 189 bus_space_handle_t sc_bsh; 190 bus_dma_tag_t sc_dmat; 191 struct ethercom sc_ec; 192 struct mii_data sc_mii; 193 krndsource_t sc_rnd_source; /* random source */ 194 kmutex_t sc_intr_lock; 195 uint8_t sc_tx_active; 196 callout_t sc_stat_ch; 197 void *sc_ih; 198 uint32_t sc_txbuf[EMAC_TXBUF_SIZE/4]; 199 }; 200 201 static const char * compatible[] = { 202 "allwinner,sun4i-a10-emac", 203 NULL 204 }; 205 206 CFATTACH_DECL_NEW(sun4i_emac, sizeof(struct sun4i_emac_softc), 207 sun4i_emac_match, sun4i_emac_attach, NULL, NULL); 208 209 static inline uint32_t 210 sun4i_emac_read(struct sun4i_emac_softc *sc, bus_size_t o) 211 { 212 return bus_space_read_4(sc->sc_bst, sc->sc_bsh, o); 213 } 214 215 static inline void 216 sun4i_emac_write(struct sun4i_emac_softc *sc, bus_size_t o, uint32_t v) 217 { 218 return bus_space_write_4(sc->sc_bst, sc->sc_bsh, o, v); 219 } 220 221 static inline void 222 sun4i_emac_clear_set(struct sun4i_emac_softc *sc, bus_size_t o, uint32_t c, 223 uint32_t s) 224 { 225 uint32_t v = bus_space_read_4(sc->sc_bst, sc->sc_bsh, o); 226 return bus_space_write_4(sc->sc_bst, sc->sc_bsh, o, (v & ~c) | s); 227 } 228 229 static int 230 sun4i_emac_match(device_t parent, cfdata_t cf, void *aux) 231 { 232 struct fdt_attach_args * const faa = aux; 233 234 return of_match_compatible(faa->faa_phandle, compatible); 235 } 236 237 static void 238 sun4i_emac_attach(device_t parent, device_t self, void *aux) 239 { 240 struct sun4i_emac_softc * const sc = device_private(self); 241 struct fdt_attach_args * const faa = aux; 242 struct ifnet * const ifp = &sc->sc_ec.ec_if; 243 struct mii_data * const mii = &sc->sc_mii; 244 const int phandle = faa->faa_phandle; 245 char enaddr[ETHER_ADDR_LEN]; 246 const uint8_t *local_addr; 247 char intrstr[128]; 248 struct clk *clk; 249 bus_addr_t addr; 250 bus_size_t size; 251 int len; 252 253 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 254 aprint_error(": cannot get registers\n"); 255 return; 256 } 257 258 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 259 aprint_error(": cannot decode interrupt\n"); 260 return; 261 } 262 263 clk = fdtbus_clock_get_index(phandle, 0); 264 if (clk == NULL) { 265 aprint_error(": cannot acquire clock\n"); 266 return; 267 } 268 if (clk_enable(clk) != 0) { 269 aprint_error(": cannot enable clock\n"); 270 return; 271 } 272 273 if (sunxi_sramc_claim(phandle) != 0) { 274 aprint_error(": cannot map SRAM to EMAC\n"); 275 return; 276 } 277 278 sc->sc_dev = self; 279 sc->sc_phandle = phandle; 280 sc->sc_ec.ec_mii = mii; 281 sc->sc_bst = faa->faa_bst; 282 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 283 aprint_error(": cannot map registers\n"); 284 return; 285 } 286 sc->sc_dmat = faa->faa_dmat; 287 288 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_NET); 289 callout_init(&sc->sc_stat_ch, 0); 290 callout_setfunc(&sc->sc_stat_ch, sun4i_emac_tick, sc); 291 292 aprint_naive("\n"); 293 aprint_normal(": 10/100 Ethernet Controller\n"); 294 295 /* 296 * Disable and then clear all interrupts 297 */ 298 sun4i_emac_write(sc, EMAC_INT_CTL_REG, 0); 299 sun4i_emac_write(sc, EMAC_INT_STA_REG, 300 sun4i_emac_read(sc, EMAC_INT_STA_REG)); 301 302 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_NET, 0, 303 sun4i_emac_intr, sc); 304 if (sc->sc_ih == NULL) { 305 aprint_error_dev(self, "failed to establish interrupt on %s\n", 306 intrstr); 307 return; 308 } 309 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 310 311 local_addr = fdtbus_get_prop(phandle, "local-mac-address", &len); 312 if (local_addr && len == ETHER_ADDR_LEN) { 313 memcpy(enaddr, local_addr, ETHER_ADDR_LEN); 314 315 uint32_t a1 = ((uint32_t)enaddr[0] << 16) | 316 ((uint32_t)enaddr[1] << 8) | 317 (uint32_t)enaddr[2]; 318 uint32_t a0 = ((uint32_t)enaddr[3] << 16) | 319 ((uint32_t)enaddr[4] << 8) | 320 (uint32_t)enaddr[5]; 321 322 sun4i_emac_write(sc, EMAC_MAC_A1_REG, a1); 323 sun4i_emac_write(sc, EMAC_MAC_A0_REG, a0); 324 } 325 326 uint32_t a1 = sun4i_emac_read(sc, EMAC_MAC_A1_REG); 327 uint32_t a0 = sun4i_emac_read(sc, EMAC_MAC_A0_REG); 328 if (a0 != 0 || a1 != 0) { 329 enaddr[0] = a1 >> 16; 330 enaddr[1] = a1 >> 8; 331 enaddr[2] = a1 >> 0; 332 enaddr[3] = a0 >> 16; 333 enaddr[4] = a0 >> 8; 334 enaddr[5] = a0 >> 0; 335 } 336 aprint_normal_dev(self, "Ethernet address: %s\n", ether_sprintf(enaddr)); 337 338 snprintf(ifp->if_xname, IFNAMSIZ, EMAC_IFNAME, device_unit(self)); 339 ifp->if_softc = sc; 340 ifp->if_capabilities = 0; 341 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 342 ifp->if_start = sun4i_emac_ifstart; 343 ifp->if_ioctl = sun4i_emac_ifioctl; 344 ifp->if_init = sun4i_emac_ifinit; 345 ifp->if_stop = sun4i_emac_ifstop; 346 ifp->if_watchdog = sun4i_emac_ifwatchdog; 347 IFQ_SET_READY(&ifp->if_snd); 348 349 /* 802.1Q VLAN-sized frames are supported */ 350 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 351 352 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 353 354 mii->mii_ifp = ifp; 355 mii->mii_readreg = sun4i_emac_miibus_read_reg; 356 mii->mii_writereg = sun4i_emac_miibus_write_reg; 357 mii->mii_statchg = sun4i_emac_miibus_statchg; 358 359 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 0); 360 361 if (LIST_EMPTY(&mii->mii_phys)) { 362 aprint_error_dev(self, "no PHY found!\n"); 363 ifmedia_add(&mii->mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 364 ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_MANUAL); 365 } else { 366 ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_AUTO); 367 } 368 369 /* 370 * Attach the interface. 371 */ 372 if_attach(ifp); 373 if_deferred_start_init(ifp, NULL); 374 ether_ifattach(ifp, enaddr); 375 rnd_attach_source(&sc->sc_rnd_source, device_xname(self), 376 RND_TYPE_NET, RND_FLAG_DEFAULT); 377 } 378 379 static inline void 380 sun4i_emac_int_enable(struct sun4i_emac_softc *sc) 381 { 382 sun4i_emac_clear_set(sc, EMAC_INT_CTL_REG, 0, 383 EMAC_INT_ENABLE); 384 sun4i_emac_write(sc, EMAC_INT_STA_REG, 385 sun4i_emac_read(sc, EMAC_INT_STA_REG)); 386 } 387 388 int 389 sun4i_emac_miibus_read_reg(device_t self, int phy, int reg) 390 { 391 struct sun4i_emac_softc * const sc = device_private(self); 392 int retry = 100; 393 394 sun4i_emac_write(sc, EMAC_MAC_MADR_REG, (phy << 8) | reg); 395 sun4i_emac_write(sc, EMAC_MAC_MCMD_REG, 1); 396 397 while (--retry > 0 && (sun4i_emac_read(sc, EMAC_MAC_MIND_REG) & 1) != 0) 398 delay(1000); 399 if (retry == 0) 400 device_printf(self, "PHY read timeout\n"); 401 402 sun4i_emac_write(sc, EMAC_MAC_MCMD_REG, 0); 403 const uint32_t rv = sun4i_emac_read(sc, EMAC_MAC_MRDD_REG); 404 405 return rv; 406 } 407 408 void 409 sun4i_emac_miibus_write_reg(device_t self, int phy, int reg, int val) 410 { 411 struct sun4i_emac_softc * const sc = device_private(self); 412 int retry = 100; 413 414 sun4i_emac_write(sc, EMAC_MAC_MADR_REG, (phy << 8) | reg); 415 sun4i_emac_write(sc, EMAC_MAC_MCMD_REG, 1); 416 417 while (--retry > 0 && (sun4i_emac_read(sc, EMAC_MAC_MIND_REG) & 1) != 0) 418 delay(1000); 419 if (retry == 0) 420 device_printf(self, "PHY write timeout\n"); 421 422 sun4i_emac_write(sc, EMAC_MAC_MCMD_REG, 0); 423 sun4i_emac_write(sc, EMAC_MAC_MWTD_REG, val); 424 } 425 426 void 427 sun4i_emac_miibus_statchg(struct ifnet *ifp) 428 { 429 struct sun4i_emac_softc * const sc = ifp->if_softc; 430 struct mii_data * const mii = &sc->sc_mii; 431 const u_int media = mii->mii_media_active; 432 433 /* 434 * Set MII interface based on the speed 435 * negotiated by the PHY. 436 */ 437 switch (IFM_SUBTYPE(media)) { 438 case IFM_10_T: 439 sun4i_emac_clear_set(sc, EMAC_MAC_SUPP_REG, 440 EMAC_MAC_SUPP_100M, 0); 441 break; 442 case IFM_100_TX: 443 sun4i_emac_clear_set(sc, EMAC_MAC_SUPP_REG, 444 0, EMAC_MAC_SUPP_100M); 445 break; 446 } 447 448 const bool link = (IFM_SUBTYPE(media) & (IFM_10_T|IFM_100_TX)) != 0; 449 if (link) { 450 if (media & IFM_FDX) { 451 sun4i_emac_clear_set(sc, EMAC_MAC_CTL1_REG, 452 0, EMAC_MAC_CTL1_FD); 453 } else { 454 sun4i_emac_clear_set(sc, EMAC_MAC_CTL1_REG, 455 EMAC_MAC_CTL1_FD, 0); 456 } 457 } 458 } 459 460 static void 461 sun4i_emac_tick(void *softc) 462 { 463 struct sun4i_emac_softc * const sc = softc; 464 struct mii_data * const mii = &sc->sc_mii; 465 int s; 466 467 s = splnet(); 468 mii_tick(mii); 469 callout_schedule(&sc->sc_stat_ch, hz); 470 splx(s); 471 } 472 473 static inline void 474 sun4i_emac_rxfifo_flush(struct sun4i_emac_softc *sc) 475 { 476 sun4i_emac_clear_set(sc, EMAC_CTL_REG, EMAC_CTL_RX_EN, 0); 477 478 sun4i_emac_clear_set(sc, EMAC_RX_CTL_REG, 0, EMAC_RX_CTL_FIFO_RESET); 479 480 for (;;) { 481 uint32_t v0 = sun4i_emac_read(sc, EMAC_RX_CTL_REG); 482 if ((v0 & EMAC_RX_CTL_FIFO_RESET) == 0) 483 break; 484 } 485 486 sun4i_emac_clear_set(sc, EMAC_CTL_REG, 0, EMAC_CTL_RX_EN); 487 } 488 489 static void 490 sun4i_emac_rxfifo_consume(struct sun4i_emac_softc *sc, size_t len) 491 { 492 for (len = (len + 3) >> 2; len > 0; len--) { 493 (void) sun4i_emac_read(sc, EMAC_RX_IO_DATA_REG); 494 } 495 } 496 497 static void 498 sun4i_emac_rxfifo_transfer(struct sun4i_emac_softc *sc, struct mbuf *m) 499 { 500 uint32_t *dp32 = mtod(m, uint32_t *); 501 const int len = roundup2(m->m_len, 4); 502 503 bus_space_read_multi_4(sc->sc_bst, sc->sc_bsh, 504 EMAC_RX_IO_DATA_REG, dp32, len / 4); 505 } 506 507 static struct mbuf * 508 sun4i_emac_mgethdr(struct sun4i_emac_softc *sc, size_t rxlen) 509 { 510 struct mbuf *m = m_gethdr(M_DONTWAIT, MT_DATA); 511 512 if (rxlen + 2 > MHLEN) { 513 MCLGET(m, M_DONTWAIT); 514 if ((m->m_flags & M_EXT) == 0) { 515 m_free(m); 516 return NULL; 517 } 518 } 519 520 m_adj(m, 2); 521 m->m_len = rxlen; 522 m->m_pkthdr.len = rxlen; 523 m_set_rcvif(m, &sc->sc_ec.ec_if); 524 m->m_flags |= M_HASFCS; 525 526 return m; 527 } 528 529 static void 530 sun4i_emac_if_input(struct sun4i_emac_softc *sc, struct mbuf *m) 531 { 532 struct ifnet * const ifp = &sc->sc_ec.ec_if; 533 534 if_percpuq_enqueue(ifp->if_percpuq, m); 535 } 536 537 static void 538 sun4i_emac_rx_intr(struct sun4i_emac_softc *sc) 539 { 540 for (;;) { 541 uint32_t rx_count = sun4i_emac_read(sc, EMAC_RX_FBC_REG); 542 struct mbuf *m; 543 544 if (rx_count == 0) { 545 rx_count = sun4i_emac_read(sc, EMAC_RX_FBC_REG); 546 if (rx_count == 0) 547 return; 548 } 549 550 uint32_t v = sun4i_emac_read(sc, EMAC_RX_IO_DATA_REG); 551 if (v != EMAC_RX_MAGIC) { 552 sun4i_emac_rxfifo_flush(sc); 553 return; 554 } 555 556 uint32_t rxhdr = sun4i_emac_read(sc, EMAC_RX_IO_DATA_REG); 557 uint32_t rxlen = __SHIFTOUT(rxhdr, EMAC_RXHDR_LEN); 558 uint32_t rxsts = __SHIFTOUT(rxhdr, EMAC_RXHDR_STS); 559 560 if (rxlen < ETHER_MIN_LEN || (rxsts & EMAC_RX_STA_PKTOK) == 0) { 561 sc->sc_ec.ec_if.if_ierrors++; 562 continue; 563 } 564 565 m = sun4i_emac_mgethdr(sc, rxlen); 566 if (m == NULL) { 567 sc->sc_ec.ec_if.if_ierrors++; 568 sun4i_emac_rxfifo_consume(sc, rxlen); 569 return; 570 } 571 572 sun4i_emac_rxfifo_transfer(sc, m); 573 sun4i_emac_if_input(sc, m); 574 } 575 } 576 577 static int 578 sun4i_emac_txfifo_transfer(struct sun4i_emac_softc *sc, struct mbuf *m, u_int slot) 579 { 580 bus_size_t const io_data_reg = EMAC_TX_IO_DATA_REG(0); 581 const int len = m->m_pkthdr.len; 582 uint32_t *pktdata; 583 584 KASSERT(len > 0 && len <= sizeof(sc->sc_txbuf)); 585 586 if (m->m_next != NULL) { 587 m_copydata(m, 0, len, sc->sc_txbuf); 588 pktdata = sc->sc_txbuf; 589 } else { 590 pktdata = mtod(m, uint32_t *); 591 } 592 593 bus_space_write_multi_4(sc->sc_bst, sc->sc_bsh, io_data_reg, 594 pktdata, roundup2(len, 4) / 4); 595 596 return len; 597 } 598 599 static void 600 sun4i_emac_tx_enqueue(struct sun4i_emac_softc *sc, struct mbuf *m, u_int slot) 601 { 602 struct ifnet * const ifp = &sc->sc_ec.ec_if; 603 604 sun4i_emac_write(sc, EMAC_TX_INS_REG, slot); 605 606 const int len = sun4i_emac_txfifo_transfer(sc, m, slot); 607 608 bus_size_t const pl_reg = EMAC_TX_PL_REG(slot); 609 bus_size_t const ctl_reg = EMAC_TX_CTL_REG(slot); 610 611 sun4i_emac_write(sc, pl_reg, len); 612 sun4i_emac_clear_set(sc, ctl_reg, 0, EMAC_TX_CTL_START); 613 614 bpf_mtap(ifp, m); 615 616 m_freem(m); 617 } 618 619 static void 620 sun4i_emac_tx_intr(struct sun4i_emac_softc *sc, u_int slot) 621 { 622 struct ifnet * const ifp = &sc->sc_ec.ec_if; 623 624 sc->sc_tx_active &= ~__BIT(slot); 625 ifp->if_flags &= ~IFF_OACTIVE; 626 } 627 628 int 629 sun4i_emac_intr(void *arg) 630 { 631 struct sun4i_emac_softc * const sc = arg; 632 struct ifnet * const ifp = &sc->sc_ec.ec_if; 633 634 mutex_enter(&sc->sc_intr_lock); 635 636 uint32_t sts = sun4i_emac_read(sc, EMAC_INT_STA_REG); 637 sun4i_emac_write(sc, EMAC_INT_STA_REG, sts); 638 rnd_add_uint32(&sc->sc_rnd_source, sts); 639 640 if (sts & EMAC_INT_RX) { 641 sun4i_emac_rx_intr(sc); 642 } 643 if (sts & EMAC_INT_TX0) { 644 sun4i_emac_tx_intr(sc, 0); 645 } 646 if (sts & EMAC_INT_TX1) { 647 sun4i_emac_tx_intr(sc, 1); 648 } 649 if (sts & (EMAC_INT_TX0|EMAC_INT_TX1)) { 650 if (sc->sc_tx_active == 0) 651 ifp->if_timer = 0; 652 if_schedule_deferred_start(ifp); 653 } 654 655 mutex_exit(&sc->sc_intr_lock); 656 657 return 1; 658 } 659 660 void 661 sun4i_emac_ifstart(struct ifnet *ifp) 662 { 663 struct sun4i_emac_softc * const sc = ifp->if_softc; 664 665 mutex_enter(&sc->sc_intr_lock); 666 667 if ((sc->sc_tx_active & 1) == 0) { 668 struct mbuf *m; 669 IFQ_DEQUEUE(&ifp->if_snd, m); 670 if (m == NULL) { 671 mutex_exit(&sc->sc_intr_lock); 672 return; 673 } 674 sun4i_emac_tx_enqueue(sc, m, 0); 675 sc->sc_tx_active |= 1; 676 } 677 678 if ((sc->sc_tx_active & 2) == 0) { 679 struct mbuf *m; 680 IFQ_DEQUEUE(&ifp->if_snd, m); 681 if (m == NULL) { 682 mutex_exit(&sc->sc_intr_lock); 683 return; 684 } 685 sun4i_emac_tx_enqueue(sc, m, 1); 686 sc->sc_tx_active |= 2; 687 } 688 689 if (sc->sc_tx_active == 3) 690 ifp->if_flags |= IFF_OACTIVE; 691 692 ifp->if_timer = 5; 693 694 mutex_exit(&sc->sc_intr_lock); 695 } 696 697 698 static int 699 sun4i_emac_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 700 { 701 struct sun4i_emac_softc * const sc = ifp->if_softc; 702 struct ifreq *ifr = (struct ifreq *)data; 703 int error; 704 705 switch (cmd) { 706 case SIOCGIFMEDIA: 707 case SIOCSIFMEDIA: 708 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 709 break; 710 default: 711 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 712 break; 713 error = 0; 714 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 715 break; 716 if (ifp->if_flags & IFF_RUNNING) { 717 /* 718 * Multicast list has changed; set the hardware filter 719 * accordingly. 720 */ 721 mutex_enter(&sc->sc_intr_lock); 722 sun4i_emac_ifstop(ifp, 0); 723 error = sun4i_emac_ifinit(ifp); 724 mutex_exit(&sc->sc_intr_lock); 725 } 726 break; 727 } 728 729 return error; 730 } 731 732 static void 733 sun4i_emac_ifstop(struct ifnet *ifp, int discard) 734 { 735 struct sun4i_emac_softc * const sc = ifp->if_softc; 736 struct mii_data * const mii = &sc->sc_mii; 737 738 KASSERT(mutex_owned(&sc->sc_intr_lock)); 739 740 callout_stop(&sc->sc_stat_ch); 741 mii_down(mii); 742 743 sun4i_emac_write(sc, EMAC_INT_CTL_REG, 0); 744 sun4i_emac_write(sc, EMAC_INT_STA_REG, 745 sun4i_emac_read(sc, EMAC_INT_STA_REG)); 746 747 sun4i_emac_clear_set(sc, EMAC_CTL_REG, 748 EMAC_CTL_RST | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN, 0); 749 750 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 751 ifp->if_timer = 0; 752 } 753 754 int 755 sun4i_emac_ifinit(struct ifnet *ifp) 756 { 757 struct sun4i_emac_softc * const sc = ifp->if_softc; 758 struct mii_data * const mii = &sc->sc_mii; 759 760 sun4i_emac_clear_set(sc, EMAC_RX_CTL_REG, 761 0, EMAC_RX_CTL_FIFO_RESET); 762 763 delay(1); 764 765 sun4i_emac_clear_set(sc, EMAC_MAC_CTL0_REG, 766 EMAC_MAC_CTL0_SOFT_RESET, 0); 767 768 sun4i_emac_clear_set(sc, EMAC_MAC_MCFG_REG, 769 EMAC_MAC_MCFG_CLK, __SHIFTIN(0xd, EMAC_MAC_MCFG_CLK)); 770 771 sun4i_emac_write(sc, EMAC_RX_FBC_REG, 0); 772 773 sun4i_emac_write(sc, EMAC_INT_CTL_REG, 0); 774 sun4i_emac_write(sc, EMAC_INT_STA_REG, 775 sun4i_emac_read(sc, EMAC_INT_STA_REG)); 776 777 delay(1); 778 779 sun4i_emac_clear_set(sc, EMAC_TX_MODE_REG, 780 EMAC_TX_MODE_DMA, EMAC_TX_MODE_ABF_ENA); 781 782 sun4i_emac_clear_set(sc, EMAC_MAC_CTL0_REG, 783 0, EMAC_MAC_CTL0_TFC | EMAC_MAC_CTL0_RFC); 784 785 sun4i_emac_clear_set(sc, EMAC_RX_CTL_REG, 786 EMAC_RX_CTL_DMA, 0); 787 788 sun4i_emac_clear_set(sc, EMAC_MAC_CTL1_REG, 789 0, 790 EMAC_MAC_CTL1_FLC | EMAC_MAC_CTL1_CRC | 791 EMAC_MAC_CTL1_PC); 792 793 sun4i_emac_write(sc, EMAC_MAC_IPGT_REG, EMAC_MAC_IPGT_FD); 794 sun4i_emac_write(sc, EMAC_MAC_IPGR_REG, 795 __SHIFTIN(0x0c, EMAC_MAC_IPGR_IPG1) | 796 __SHIFTIN(0x12, EMAC_MAC_IPGR_IPG2)); 797 798 sun4i_emac_write(sc, EMAC_MAC_CLRT_REG, 799 __SHIFTIN(0x0f, EMAC_MAC_CLRT_RM) | 800 __SHIFTIN(0x37, EMAC_MAC_CLRT_CW)); 801 802 sun4i_emac_write(sc, EMAC_MAC_MAXF_REG, 0x600); 803 804 sun4i_emac_rx_hash(sc); 805 806 sun4i_emac_int_enable(sc); 807 808 ifp->if_flags |= IFF_RUNNING; 809 ifp->if_flags &= ~IFF_OACTIVE; 810 811 /* Enable RX/TX */ 812 sun4i_emac_clear_set(sc, EMAC_CTL_REG, 813 0, EMAC_CTL_RST | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN); 814 815 mii_mediachg(mii); 816 callout_schedule(&sc->sc_stat_ch, hz); 817 818 return 0; 819 } 820 821 static void 822 sun4i_emac_ifwatchdog(struct ifnet *ifp) 823 { 824 struct sun4i_emac_softc * const sc = ifp->if_softc; 825 826 device_printf(sc->sc_dev, "device timeout\n"); 827 828 ifp->if_oerrors++; 829 sun4i_emac_ifinit(ifp); 830 sun4i_emac_ifstart(ifp); 831 } 832 833 static void 834 sun4i_emac_rx_hash(struct sun4i_emac_softc *sc) 835 { 836 struct ifnet * const ifp = &sc->sc_ec.ec_if; 837 struct ether_multistep step; 838 struct ether_multi *enm; 839 uint32_t hash[2]; 840 uint32_t rxctl; 841 842 rxctl = sun4i_emac_read(sc, EMAC_RX_CTL_REG); 843 rxctl &= ~EMAC_RX_CTL_MHF; 844 rxctl |= EMAC_RX_CTL_UCAD; 845 rxctl |= EMAC_RX_CTL_DAF; 846 rxctl |= EMAC_RX_CTL_MC0; 847 rxctl |= EMAC_RX_CTL_BC0; 848 rxctl |= EMAC_RX_CTL_POR; 849 850 hash[0] = hash[1] = ~0; 851 if (ifp->if_flags & IFF_PROMISC) { 852 ifp->if_flags |= IFF_ALLMULTI; 853 rxctl |= EMAC_RX_CTL_PROMISC; 854 } else { 855 rxctl &= ~EMAC_RX_CTL_PROMISC; 856 } 857 858 if ((ifp->if_flags & IFF_PROMISC) == 0) { 859 hash[0] = hash[1] = 0; 860 861 ETHER_FIRST_MULTI(step, &sc->sc_ec, enm); 862 while (enm != NULL) { 863 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 864 /* 865 * We must listen to a range of multicast addresses. 866 * For now, just accept all multicasts, rather than 867 * trying to set only those filter bits needed to match 868 * the range. (At this time, the only use of address 869 * ranges is for IP multicast routing, for which the 870 * range is big enough to require all bits set.) 871 */ 872 hash[0] = hash[1] = ~0; 873 ifp->if_flags |= IFF_ALLMULTI; 874 goto done; 875 } 876 877 u_int crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 878 879 /* Just want the 6 most significant bits. */ 880 crc >>= 26; 881 882 /* Set the corresponding bit in the filter. */ 883 hash[crc >> 5] |= __BIT(crc & 31); 884 ETHER_NEXT_MULTI(step, enm); 885 } 886 ifp->if_flags &= ~IFF_ALLMULTI; 887 rxctl |= EMAC_RX_CTL_MHF; 888 } 889 890 done: 891 892 sun4i_emac_write(sc, EMAC_RX_HASH0_REG, hash[0]); 893 sun4i_emac_write(sc, EMAC_RX_HASH1_REG, hash[1]); 894 895 sun4i_emac_write(sc, EMAC_RX_CTL_REG, rxctl); 896 } 897
Indexes created Mon Oct 27 08:10:08 GMT 2025