sun4i_emac.c revision 1.3
1 /* $NetBSD: sun4i_emac.c,v 1.3 2018/02/12 17:04:58 maxv Exp $ */ 2 3 /*- 4 * Copyright (c) 2013-2017 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry and Jared McNeill. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 34 __KERNEL_RCSID(1, "$NetBSD: sun4i_emac.c,v 1.3 2018/02/12 17:04:58 maxv Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/bus.h> 38 #include <sys/device.h> 39 #include <sys/intr.h> 40 #include <sys/ioctl.h> 41 #include <sys/mutex.h> 42 #include <sys/rndsource.h> 43 #include <sys/kernel.h> 44 #include <sys/systm.h> 45 46 #include <net/bpf.h> 47 #include <net/if.h> 48 #include <net/if_dl.h> 49 #include <net/if_ether.h> 50 #include <net/if_media.h> 51 52 #include <dev/mii/miivar.h> 53 54 #include <dev/fdt/fdtvar.h> 55 56 #include <arm/sunxi/sunxi_sramc.h> 57 58 #define EMAC_IFNAME "emac%d" 59 60 #define EMAC_CTL_REG 0x00 61 #define EMAC_CTL_RX_EN __BIT(2) 62 #define EMAC_CTL_TX_EN __BIT(1) 63 #define EMAC_CTL_RST __BIT(0) 64 #define EMAC_TX_MODE_REG 0x04 65 #define EMAC_TX_MODE_DMA __BIT(1) 66 #define EMAC_TX_MODE_ABF_ENA __BIT(0) 67 #define EMAC_TX_FLOW_REG 0x08 68 #define EMAC_TX_CTL0_REG 0x0c 69 #define EMAC_TX_CTL1_REG 0x10 70 #define EMAC_TX_CTL_REG(n) (EMAC_TX_CTL0_REG+4*(n)) 71 #define EMAC_TX_CTL_START __BIT(0) 72 #define EMAC_TX_INS_REG 0x14 73 #define EMAC_TX_PL0_REG 0x18 74 #define EMAC_TX_PL1_REG 0x1c 75 #define EMAC_TX_PL_REG(n) (EMAC_TX_PL0_REG+4*(n)) 76 #define EMAC_TX_STA_REG 0x20 77 #define EMAC_TX_IO_DATA0_REG 0x24 78 #define EMAC_TX_IO_DATA1_REG 0x28 79 #define EMAC_TX_IO_DATA_REG(n) (EMAC_TX_IO_DATA0_REG+4*(n)) 80 #define EMAC_TX_TSVL0_REG 0x2c 81 #define EMAC_TX_TSVH0_REG 0x30 82 #define EMAC_TX_TSVL1_REG 0x34 83 #define EMAC_TX_TSVH1_REG 0x38 84 #define EMAC_RX_CTL_REG 0x3c 85 #define EMAC_RX_CTL_SA_IF __BIT(25) 86 #define EMAC_RX_CTL_SA __BIT(24) 87 #define EMAC_RX_CTL_BC0 __BIT(22) 88 #define EMAC_RX_CTL_MHF __BIT(21) 89 #define EMAC_RX_CTL_MC0 __BIT(20) 90 #define EMAC_RX_CTL_DAF __BIT(17) 91 #define EMAC_RX_CTL_UCAD __BIT(16) 92 #define EMAC_RX_CTL_POR __BIT(8) 93 #define EMAC_RX_CTL_PLE __BIT(7) 94 #define EMAC_RX_CTL_PCRCE __BIT(6) 95 #define EMAC_RX_CTL_PCF __BIT(5) 96 #define EMAC_RX_CTL_PROMISC __BIT(4) 97 #define EMAC_RX_CTL_FIFO_RESET __BIT(3) 98 #define EMAC_RX_CTL_DMA __BIT(2) 99 #define EMAC_RX_CTL_DRQ_MODE __BIT(1) 100 #define EMAC_RX_CTL_START __BIT(0) 101 #define EMAC_RX_HASH0_REG 0x40 102 #define EMAC_RX_HASH1_REG 0x44 103 #define EMAC_RX_STA_REG 0x48 104 #define EMAC_RX_STA_PKTOK __BIT(7) 105 #define EMAC_RX_STA_ALNERR __BIT(6) 106 #define EMAC_RX_STA_LENERR __BIT(5) 107 #define EMAC_RX_STA_CRCERR __BIT(4) 108 #define EMAC_RX_IO_DATA_REG 0x4c 109 #define EMAC_RX_FBC_REG 0x50 110 #define EMAC_INT_CTL_REG 0x54 111 #define EMAC_INT_STA_REG 0x58 112 #define EMAC_INT_RX __BIT(8) 113 #define EMAC_INT_TX1 __BIT(1) 114 #define EMAC_INT_TX0 __BIT(0) 115 #define EMAC_INT_ENABLE \ 116 (EMAC_INT_RX|EMAC_INT_TX1|EMAC_INT_TX0) 117 #define EMAC_MAC_CTL0_REG 0x5c 118 #define EMAC_MAC_CTL0_SOFT_RESET __BIT(15) 119 #define EMAC_MAC_CTL0_TFC __BIT(3) 120 #define EMAC_MAC_CTL0_RFC __BIT(2) 121 #define EMAC_MAC_CTL1_REG 0x60 122 #define EMAC_MAC_CTL1_ED __BIT(15) 123 #define EMAC_MAC_CTL1_NB __BIT(13) 124 #define EMAC_MAC_CTL1_BNB __BIT(12) 125 #define EMAC_MAC_CTL1_LPE __BIT(9) 126 #define EMAC_MAC_CTL1_PRE __BIT(8) 127 #define EMAC_MAC_CTL1_ADP __BIT(7) 128 #define EMAC_MAC_CTL1_VC __BIT(6) 129 #define EMAC_MAC_CTL1_PC __BIT(5) 130 #define EMAC_MAC_CTL1_CRC __BIT(4) 131 #define EMAC_MAC_CTL1_DCRC __BIT(3) 132 #define EMAC_MAC_CTL1_HF __BIT(2) 133 #define EMAC_MAC_CTL1_FLC __BIT(1) 134 #define EMAC_MAC_CTL1_FD __BIT(0) 135 #define EMAC_MAC_IPGT_REG 0x64 136 #define EMAC_MAC_IPGT_FD 0x15 137 #define EMAC_MAC_IPGR_REG 0x68 138 #define EMAC_MAC_IPGR_IPG1 __BITS(15,8) 139 #define EMAC_MAC_IPGR_IPG2 __BITS(7,0) 140 #define EMAC_MAC_CLRT_REG 0x6c 141 #define EMAC_MAC_CLRT_CW __BITS(15,8) 142 #define EMAC_MAC_CLRT_RM __BITS(7,0) 143 #define EMAC_MAC_MAXF_REG 0x70 144 #define EMAC_MAC_SUPP_REG 0x74 145 #define EMAC_MAC_SUPP_100M __BIT(8) 146 #define EMAC_MAC_TEST_REG 0x78 147 #define EMAC_MAC_MCFG_REG 0x7c 148 #define EMAC_MAC_MCFG_CLK __BITS(5,2) 149 #define EMAC_MAC_MCMD_REG 0x80 150 #define EMAC_MAC_MADR_REG 0x84 151 #define EMAC_MAC_MWTD_REG 0x88 152 #define EMAC_MAC_MRDD_REG 0x8c 153 #define EMAC_MAC_MIND_REG 0x90 154 #define EMAC_MAC_SSRR_REG 0x94 155 #define EMAC_MAC_A0_REG 0x98 156 #define EMAC_MAC_A1_REG 0x9c 157 #define EMAC_MAC_A2_REG 0xa0 158 159 #define EMAC_RXHDR_STS __BITS(31,16) 160 #define EMAC_RXHDR_LEN __BITS(15,0) 161 162 #define EMAC_RX_MAGIC 0x0143414d /* M A C \001 */ 163 164 #define EMAC_TXBUF_SIZE 4096 165 166 static int sun4i_emac_match(device_t, cfdata_t, void *); 167 static void sun4i_emac_attach(device_t, device_t, void *); 168 169 static int sun4i_emac_intr(void *); 170 static void sun4i_emac_tick(void *); 171 172 static int sun4i_emac_miibus_read_reg(device_t, int, int); 173 static void sun4i_emac_miibus_write_reg(device_t, int, int, int); 174 static void sun4i_emac_miibus_statchg(struct ifnet *); 175 176 static void sun4i_emac_ifstart(struct ifnet *); 177 static int sun4i_emac_ifioctl(struct ifnet *, u_long, void *); 178 static int sun4i_emac_ifinit(struct ifnet *); 179 static void sun4i_emac_ifstop(struct ifnet *, int); 180 static void sun4i_emac_ifwatchdog(struct ifnet *); 181 182 struct sun4i_emac_softc; 183 static void sun4i_emac_rx_hash(struct sun4i_emac_softc *); 184 185 struct sun4i_emac_softc { 186 device_t sc_dev; 187 int sc_phandle; 188 bus_space_tag_t sc_bst; 189 bus_space_handle_t sc_bsh; 190 bus_dma_tag_t sc_dmat; 191 struct ethercom sc_ec; 192 struct mii_data sc_mii; 193 krndsource_t sc_rnd_source; /* random source */ 194 kmutex_t sc_intr_lock; 195 uint8_t sc_tx_active; 196 callout_t sc_stat_ch; 197 void *sc_ih; 198 uint32_t sc_txbuf[EMAC_TXBUF_SIZE/4]; 199 }; 200 201 static const char * compatible[] = { 202 "allwinner,sun4i-a10-emac", 203 NULL 204 }; 205 206 CFATTACH_DECL_NEW(sun4i_emac, sizeof(struct sun4i_emac_softc), 207 sun4i_emac_match, sun4i_emac_attach, NULL, NULL); 208 209 static inline uint32_t 210 sun4i_emac_read(struct sun4i_emac_softc *sc, bus_size_t o) 211 { 212 return bus_space_read_4(sc->sc_bst, sc->sc_bsh, o); 213 } 214 215 static inline void 216 sun4i_emac_write(struct sun4i_emac_softc *sc, bus_size_t o, uint32_t v) 217 { 218 return bus_space_write_4(sc->sc_bst, sc->sc_bsh, o, v); 219 } 220 221 static inline void 222 sun4i_emac_clear_set(struct sun4i_emac_softc *sc, bus_size_t o, uint32_t c, 223 uint32_t s) 224 { 225 uint32_t v = bus_space_read_4(sc->sc_bst, sc->sc_bsh, o); 226 return bus_space_write_4(sc->sc_bst, sc->sc_bsh, o, (v & ~c) | s); 227 } 228 229 static int 230 sun4i_emac_match(device_t parent, cfdata_t cf, void *aux) 231 { 232 struct fdt_attach_args * const faa = aux; 233 234 return of_match_compatible(faa->faa_phandle, compatible); 235 } 236 237 static void 238 sun4i_emac_attach(device_t parent, device_t self, void *aux) 239 { 240 struct sun4i_emac_softc * const sc = device_private(self); 241 struct fdt_attach_args * const faa = aux; 242 struct ifnet * const ifp = &sc->sc_ec.ec_if; 243 struct mii_data * const mii = &sc->sc_mii; 244 const int phandle = faa->faa_phandle; 245 char enaddr[ETHER_ADDR_LEN]; 246 const uint8_t *local_addr; 247 char intrstr[128]; 248 struct clk *clk; 249 bus_addr_t addr; 250 bus_size_t size; 251 int len; 252 253 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 254 aprint_error(": cannot get registers\n"); 255 return; 256 } 257 258 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 259 aprint_error(": cannot decode interrupt\n"); 260 return; 261 } 262 263 clk = fdtbus_clock_get_index(phandle, 0); 264 if (clk == NULL) { 265 aprint_error(": cannot acquire clock\n"); 266 return; 267 } 268 if (clk_enable(clk) != 0) { 269 aprint_error(": cannot enable clock\n"); 270 return; 271 } 272 273 if (sunxi_sramc_claim(phandle) != 0) { 274 aprint_error(": cannot map SRAM to EMAC\n"); 275 return; 276 } 277 278 sc->sc_dev = self; 279 sc->sc_phandle = phandle; 280 sc->sc_ec.ec_mii = mii; 281 sc->sc_bst = faa->faa_bst; 282 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 283 aprint_error(": cannot map registers\n"); 284 return; 285 } 286 sc->sc_dmat = faa->faa_dmat; 287 288 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_NET); 289 callout_init(&sc->sc_stat_ch, 0); 290 callout_setfunc(&sc->sc_stat_ch, sun4i_emac_tick, sc); 291 292 aprint_naive("\n"); 293 aprint_normal(": 10/100 Ethernet Controller\n"); 294 295 /* 296 * Disable and then clear all interrupts 297 */ 298 sun4i_emac_write(sc, EMAC_INT_CTL_REG, 0); 299 sun4i_emac_write(sc, EMAC_INT_STA_REG, 300 sun4i_emac_read(sc, EMAC_INT_STA_REG)); 301 302 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_NET, 0, 303 sun4i_emac_intr, sc); 304 if (sc->sc_ih == NULL) { 305 aprint_error_dev(self, "failed to establish interrupt on %s\n", 306 intrstr); 307 return; 308 } 309 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 310 311 local_addr = fdtbus_get_prop(phandle, "local-mac-address", &len); 312 if (local_addr && len == ETHER_ADDR_LEN) { 313 memcpy(enaddr, local_addr, ETHER_ADDR_LEN); 314 315 uint32_t a1 = ((uint32_t)enaddr[0] << 16) | 316 ((uint32_t)enaddr[1] << 8) | 317 (uint32_t)enaddr[2]; 318 uint32_t a0 = ((uint32_t)enaddr[3] << 16) | 319 ((uint32_t)enaddr[4] << 8) | 320 (uint32_t)enaddr[5]; 321 322 sun4i_emac_write(sc, EMAC_MAC_A1_REG, a1); 323 sun4i_emac_write(sc, EMAC_MAC_A0_REG, a0); 324 } 325 326 uint32_t a1 = sun4i_emac_read(sc, EMAC_MAC_A1_REG); 327 uint32_t a0 = sun4i_emac_read(sc, EMAC_MAC_A0_REG); 328 if (a0 != 0 || a1 != 0) { 329 enaddr[0] = a1 >> 16; 330 enaddr[1] = a1 >> 8; 331 enaddr[2] = a1 >> 0; 332 enaddr[3] = a0 >> 16; 333 enaddr[4] = a0 >> 8; 334 enaddr[5] = a0 >> 0; 335 } 336 aprint_normal_dev(self, "Ethernet address: %s\n", ether_sprintf(enaddr)); 337 338 snprintf(ifp->if_xname, IFNAMSIZ, EMAC_IFNAME, device_unit(self)); 339 ifp->if_softc = sc; 340 ifp->if_capabilities = 0; 341 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 342 ifp->if_start = sun4i_emac_ifstart; 343 ifp->if_ioctl = sun4i_emac_ifioctl; 344 ifp->if_init = sun4i_emac_ifinit; 345 ifp->if_stop = sun4i_emac_ifstop; 346 ifp->if_watchdog = sun4i_emac_ifwatchdog; 347 IFQ_SET_READY(&ifp->if_snd); 348 349 /* 802.1Q VLAN-sized frames are supported */ 350 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 351 352 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 353 354 mii->mii_ifp = ifp; 355 mii->mii_readreg = sun4i_emac_miibus_read_reg; 356 mii->mii_writereg = sun4i_emac_miibus_write_reg; 357 mii->mii_statchg = sun4i_emac_miibus_statchg; 358 359 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 0); 360 361 if (LIST_EMPTY(&mii->mii_phys)) { 362 aprint_error_dev(self, "no PHY found!\n"); 363 ifmedia_add(&mii->mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 364 ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_MANUAL); 365 } else { 366 ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_AUTO); 367 } 368 369 /* 370 * Attach the interface. 371 */ 372 if_attach(ifp); 373 if_deferred_start_init(ifp, NULL); 374 ether_ifattach(ifp, enaddr); 375 rnd_attach_source(&sc->sc_rnd_source, device_xname(self), 376 RND_TYPE_NET, RND_FLAG_DEFAULT); 377 } 378 379 static inline void 380 sun4i_emac_int_enable(struct sun4i_emac_softc *sc) 381 { 382 sun4i_emac_clear_set(sc, EMAC_INT_CTL_REG, 0, 383 EMAC_INT_ENABLE); 384 sun4i_emac_write(sc, EMAC_INT_STA_REG, 385 sun4i_emac_read(sc, EMAC_INT_STA_REG)); 386 } 387 388 int 389 sun4i_emac_miibus_read_reg(device_t self, int phy, int reg) 390 { 391 struct sun4i_emac_softc * const sc = device_private(self); 392 int retry = 100; 393 394 sun4i_emac_write(sc, EMAC_MAC_MADR_REG, (phy << 8) | reg); 395 sun4i_emac_write(sc, EMAC_MAC_MCMD_REG, 1); 396 397 while (--retry > 0 && (sun4i_emac_read(sc, EMAC_MAC_MIND_REG) & 1) != 0) 398 delay(1000); 399 if (retry == 0) 400 device_printf(self, "PHY read timeout\n"); 401 402 sun4i_emac_write(sc, EMAC_MAC_MCMD_REG, 0); 403 const uint32_t rv = sun4i_emac_read(sc, EMAC_MAC_MRDD_REG); 404 405 return rv; 406 } 407 408 void 409 sun4i_emac_miibus_write_reg(device_t self, int phy, int reg, int val) 410 { 411 struct sun4i_emac_softc * const sc = device_private(self); 412 int retry = 100; 413 414 sun4i_emac_write(sc, EMAC_MAC_MADR_REG, (phy << 8) | reg); 415 sun4i_emac_write(sc, EMAC_MAC_MCMD_REG, 1); 416 417 while (--retry > 0 && (sun4i_emac_read(sc, EMAC_MAC_MIND_REG) & 1) != 0) 418 delay(1000); 419 if (retry == 0) 420 device_printf(self, "PHY write timeout\n"); 421 422 sun4i_emac_write(sc, EMAC_MAC_MCMD_REG, 0); 423 sun4i_emac_write(sc, EMAC_MAC_MWTD_REG, val); 424 } 425 426 void 427 sun4i_emac_miibus_statchg(struct ifnet *ifp) 428 { 429 struct sun4i_emac_softc * const sc = ifp->if_softc; 430 struct mii_data * const mii = &sc->sc_mii; 431 const u_int media = mii->mii_media_active; 432 433 /* 434 * Set MII interface based on the speed 435 * negotiated by the PHY. 436 */ 437 switch (IFM_SUBTYPE(media)) { 438 case IFM_10_T: 439 sun4i_emac_clear_set(sc, EMAC_MAC_SUPP_REG, 440 EMAC_MAC_SUPP_100M, 0); 441 break; 442 case IFM_100_TX: 443 sun4i_emac_clear_set(sc, EMAC_MAC_SUPP_REG, 444 0, EMAC_MAC_SUPP_100M); 445 break; 446 } 447 448 const bool link = (IFM_SUBTYPE(media) & (IFM_10_T|IFM_100_TX)) != 0; 449 if (link) { 450 if (media & IFM_FDX) { 451 sun4i_emac_clear_set(sc, EMAC_MAC_CTL1_REG, 452 0, EMAC_MAC_CTL1_FD); 453 } else { 454 sun4i_emac_clear_set(sc, EMAC_MAC_CTL1_REG, 455 EMAC_MAC_CTL1_FD, 0); 456 } 457 } 458 } 459 460 static void 461 sun4i_emac_tick(void *softc) 462 { 463 struct sun4i_emac_softc * const sc = softc; 464 struct mii_data * const mii = &sc->sc_mii; 465 int s; 466 467 s = splnet(); 468 mii_tick(mii); 469 callout_schedule(&sc->sc_stat_ch, hz); 470 splx(s); 471 } 472 473 static inline void 474 sun4i_emac_rxfifo_flush(struct sun4i_emac_softc *sc) 475 { 476 sun4i_emac_clear_set(sc, EMAC_CTL_REG, EMAC_CTL_RX_EN, 0); 477 478 sun4i_emac_clear_set(sc, EMAC_RX_CTL_REG, 0, EMAC_RX_CTL_FIFO_RESET); 479 480 for (;;) { 481 uint32_t v0 = sun4i_emac_read(sc, EMAC_RX_CTL_REG); 482 if ((v0 & EMAC_RX_CTL_FIFO_RESET) == 0) 483 break; 484 } 485 486 sun4i_emac_clear_set(sc, EMAC_CTL_REG, 0, EMAC_CTL_RX_EN); 487 } 488 489 static void 490 sun4i_emac_rxfifo_consume(struct sun4i_emac_softc *sc, size_t len) 491 { 492 for (len = (len + 3) >> 2; len > 0; len--) { 493 (void) sun4i_emac_read(sc, EMAC_RX_IO_DATA_REG); 494 } 495 } 496 497 static void 498 sun4i_emac_rxfifo_transfer(struct sun4i_emac_softc *sc, struct mbuf *m) 499 { 500 uint32_t *dp32 = mtod(m, uint32_t *); 501 const int len = roundup2(m->m_len, 4); 502 503 bus_space_read_multi_4(sc->sc_bst, sc->sc_bsh, 504 EMAC_RX_IO_DATA_REG, dp32, len / 4); 505 } 506 507 static struct mbuf * 508 sun4i_emac_mgethdr(struct sun4i_emac_softc *sc, size_t rxlen) 509 { 510 struct mbuf *m = m_gethdr(M_DONTWAIT, MT_DATA); 511 512 if (m == NULL) { 513 return NULL; 514 } 515 if (rxlen + 2 > MHLEN) { 516 MCLGET(m, M_DONTWAIT); 517 if ((m->m_flags & M_EXT) == 0) { 518 m_free(m); 519 return NULL; 520 } 521 } 522 523 m_adj(m, 2); 524 m->m_len = rxlen; 525 m->m_pkthdr.len = rxlen; 526 m_set_rcvif(m, &sc->sc_ec.ec_if); 527 m->m_flags |= M_HASFCS; 528 529 return m; 530 } 531 532 static void 533 sun4i_emac_if_input(struct sun4i_emac_softc *sc, struct mbuf *m) 534 { 535 struct ifnet * const ifp = &sc->sc_ec.ec_if; 536 537 if_percpuq_enqueue(ifp->if_percpuq, m); 538 } 539 540 static void 541 sun4i_emac_rx_intr(struct sun4i_emac_softc *sc) 542 { 543 for (;;) { 544 uint32_t rx_count = sun4i_emac_read(sc, EMAC_RX_FBC_REG); 545 struct mbuf *m; 546 547 if (rx_count == 0) { 548 rx_count = sun4i_emac_read(sc, EMAC_RX_FBC_REG); 549 if (rx_count == 0) 550 return; 551 } 552 553 uint32_t v = sun4i_emac_read(sc, EMAC_RX_IO_DATA_REG); 554 if (v != EMAC_RX_MAGIC) { 555 sun4i_emac_rxfifo_flush(sc); 556 return; 557 } 558 559 uint32_t rxhdr = sun4i_emac_read(sc, EMAC_RX_IO_DATA_REG); 560 uint32_t rxlen = __SHIFTOUT(rxhdr, EMAC_RXHDR_LEN); 561 uint32_t rxsts = __SHIFTOUT(rxhdr, EMAC_RXHDR_STS); 562 563 if (rxlen < ETHER_MIN_LEN || (rxsts & EMAC_RX_STA_PKTOK) == 0) { 564 sc->sc_ec.ec_if.if_ierrors++; 565 continue; 566 } 567 568 m = sun4i_emac_mgethdr(sc, rxlen); 569 if (m == NULL) { 570 sc->sc_ec.ec_if.if_ierrors++; 571 sun4i_emac_rxfifo_consume(sc, rxlen); 572 return; 573 } 574 575 sun4i_emac_rxfifo_transfer(sc, m); 576 sun4i_emac_if_input(sc, m); 577 } 578 } 579 580 static int 581 sun4i_emac_txfifo_transfer(struct sun4i_emac_softc *sc, struct mbuf *m, u_int slot) 582 { 583 bus_size_t const io_data_reg = EMAC_TX_IO_DATA_REG(0); 584 const int len = m->m_pkthdr.len; 585 uint32_t *pktdata; 586 587 KASSERT(len > 0 && len <= sizeof(sc->sc_txbuf)); 588 589 if (m->m_next != NULL) { 590 m_copydata(m, 0, len, sc->sc_txbuf); 591 pktdata = sc->sc_txbuf; 592 } else { 593 pktdata = mtod(m, uint32_t *); 594 } 595 596 bus_space_write_multi_4(sc->sc_bst, sc->sc_bsh, io_data_reg, 597 pktdata, roundup2(len, 4) / 4); 598 599 return len; 600 } 601 602 static void 603 sun4i_emac_tx_enqueue(struct sun4i_emac_softc *sc, struct mbuf *m, u_int slot) 604 { 605 struct ifnet * const ifp = &sc->sc_ec.ec_if; 606 607 sun4i_emac_write(sc, EMAC_TX_INS_REG, slot); 608 609 const int len = sun4i_emac_txfifo_transfer(sc, m, slot); 610 611 bus_size_t const pl_reg = EMAC_TX_PL_REG(slot); 612 bus_size_t const ctl_reg = EMAC_TX_CTL_REG(slot); 613 614 sun4i_emac_write(sc, pl_reg, len); 615 sun4i_emac_clear_set(sc, ctl_reg, 0, EMAC_TX_CTL_START); 616 617 bpf_mtap(ifp, m); 618 619 m_freem(m); 620 } 621 622 static void 623 sun4i_emac_tx_intr(struct sun4i_emac_softc *sc, u_int slot) 624 { 625 struct ifnet * const ifp = &sc->sc_ec.ec_if; 626 627 sc->sc_tx_active &= ~__BIT(slot); 628 ifp->if_flags &= ~IFF_OACTIVE; 629 } 630 631 int 632 sun4i_emac_intr(void *arg) 633 { 634 struct sun4i_emac_softc * const sc = arg; 635 struct ifnet * const ifp = &sc->sc_ec.ec_if; 636 637 mutex_enter(&sc->sc_intr_lock); 638 639 uint32_t sts = sun4i_emac_read(sc, EMAC_INT_STA_REG); 640 sun4i_emac_write(sc, EMAC_INT_STA_REG, sts); 641 rnd_add_uint32(&sc->sc_rnd_source, sts); 642 643 if (sts & EMAC_INT_RX) { 644 sun4i_emac_rx_intr(sc); 645 } 646 if (sts & EMAC_INT_TX0) { 647 sun4i_emac_tx_intr(sc, 0); 648 } 649 if (sts & EMAC_INT_TX1) { 650 sun4i_emac_tx_intr(sc, 1); 651 } 652 if (sts & (EMAC_INT_TX0|EMAC_INT_TX1)) { 653 if (sc->sc_tx_active == 0) 654 ifp->if_timer = 0; 655 if_schedule_deferred_start(ifp); 656 } 657 658 mutex_exit(&sc->sc_intr_lock); 659 660 return 1; 661 } 662 663 void 664 sun4i_emac_ifstart(struct ifnet *ifp) 665 { 666 struct sun4i_emac_softc * const sc = ifp->if_softc; 667 668 mutex_enter(&sc->sc_intr_lock); 669 670 if ((sc->sc_tx_active & 1) == 0) { 671 struct mbuf *m; 672 IFQ_DEQUEUE(&ifp->if_snd, m); 673 if (m == NULL) { 674 mutex_exit(&sc->sc_intr_lock); 675 return; 676 } 677 sun4i_emac_tx_enqueue(sc, m, 0); 678 sc->sc_tx_active |= 1; 679 } 680 681 if ((sc->sc_tx_active & 2) == 0) { 682 struct mbuf *m; 683 IFQ_DEQUEUE(&ifp->if_snd, m); 684 if (m == NULL) { 685 mutex_exit(&sc->sc_intr_lock); 686 return; 687 } 688 sun4i_emac_tx_enqueue(sc, m, 1); 689 sc->sc_tx_active |= 2; 690 } 691 692 if (sc->sc_tx_active == 3) 693 ifp->if_flags |= IFF_OACTIVE; 694 695 ifp->if_timer = 5; 696 697 mutex_exit(&sc->sc_intr_lock); 698 } 699 700 701 static int 702 sun4i_emac_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 703 { 704 struct sun4i_emac_softc * const sc = ifp->if_softc; 705 struct ifreq *ifr = (struct ifreq *)data; 706 int error; 707 708 switch (cmd) { 709 case SIOCGIFMEDIA: 710 case SIOCSIFMEDIA: 711 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 712 break; 713 default: 714 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 715 break; 716 error = 0; 717 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 718 break; 719 if (ifp->if_flags & IFF_RUNNING) { 720 /* 721 * Multicast list has changed; set the hardware filter 722 * accordingly. 723 */ 724 mutex_enter(&sc->sc_intr_lock); 725 sun4i_emac_ifstop(ifp, 0); 726 error = sun4i_emac_ifinit(ifp); 727 mutex_exit(&sc->sc_intr_lock); 728 } 729 break; 730 } 731 732 return error; 733 } 734 735 static void 736 sun4i_emac_ifstop(struct ifnet *ifp, int discard) 737 { 738 struct sun4i_emac_softc * const sc = ifp->if_softc; 739 struct mii_data * const mii = &sc->sc_mii; 740 741 KASSERT(mutex_owned(&sc->sc_intr_lock)); 742 743 callout_stop(&sc->sc_stat_ch); 744 mii_down(mii); 745 746 sun4i_emac_write(sc, EMAC_INT_CTL_REG, 0); 747 sun4i_emac_write(sc, EMAC_INT_STA_REG, 748 sun4i_emac_read(sc, EMAC_INT_STA_REG)); 749 750 sun4i_emac_clear_set(sc, EMAC_CTL_REG, 751 EMAC_CTL_RST | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN, 0); 752 753 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 754 ifp->if_timer = 0; 755 } 756 757 int 758 sun4i_emac_ifinit(struct ifnet *ifp) 759 { 760 struct sun4i_emac_softc * const sc = ifp->if_softc; 761 struct mii_data * const mii = &sc->sc_mii; 762 763 sun4i_emac_clear_set(sc, EMAC_RX_CTL_REG, 764 0, EMAC_RX_CTL_FIFO_RESET); 765 766 delay(1); 767 768 sun4i_emac_clear_set(sc, EMAC_MAC_CTL0_REG, 769 EMAC_MAC_CTL0_SOFT_RESET, 0); 770 771 sun4i_emac_clear_set(sc, EMAC_MAC_MCFG_REG, 772 EMAC_MAC_MCFG_CLK, __SHIFTIN(0xd, EMAC_MAC_MCFG_CLK)); 773 774 sun4i_emac_write(sc, EMAC_RX_FBC_REG, 0); 775 776 sun4i_emac_write(sc, EMAC_INT_CTL_REG, 0); 777 sun4i_emac_write(sc, EMAC_INT_STA_REG, 778 sun4i_emac_read(sc, EMAC_INT_STA_REG)); 779 780 delay(1); 781 782 sun4i_emac_clear_set(sc, EMAC_TX_MODE_REG, 783 EMAC_TX_MODE_DMA, EMAC_TX_MODE_ABF_ENA); 784 785 sun4i_emac_clear_set(sc, EMAC_MAC_CTL0_REG, 786 0, EMAC_MAC_CTL0_TFC | EMAC_MAC_CTL0_RFC); 787 788 sun4i_emac_clear_set(sc, EMAC_RX_CTL_REG, 789 EMAC_RX_CTL_DMA, 0); 790 791 sun4i_emac_clear_set(sc, EMAC_MAC_CTL1_REG, 792 0, 793 EMAC_MAC_CTL1_FLC | EMAC_MAC_CTL1_CRC | 794 EMAC_MAC_CTL1_PC); 795 796 sun4i_emac_write(sc, EMAC_MAC_IPGT_REG, EMAC_MAC_IPGT_FD); 797 sun4i_emac_write(sc, EMAC_MAC_IPGR_REG, 798 __SHIFTIN(0x0c, EMAC_MAC_IPGR_IPG1) | 799 __SHIFTIN(0x12, EMAC_MAC_IPGR_IPG2)); 800 801 sun4i_emac_write(sc, EMAC_MAC_CLRT_REG, 802 __SHIFTIN(0x0f, EMAC_MAC_CLRT_RM) | 803 __SHIFTIN(0x37, EMAC_MAC_CLRT_CW)); 804 805 sun4i_emac_write(sc, EMAC_MAC_MAXF_REG, 0x600); 806 807 sun4i_emac_rx_hash(sc); 808 809 sun4i_emac_int_enable(sc); 810 811 ifp->if_flags |= IFF_RUNNING; 812 ifp->if_flags &= ~IFF_OACTIVE; 813 814 /* Enable RX/TX */ 815 sun4i_emac_clear_set(sc, EMAC_CTL_REG, 816 0, EMAC_CTL_RST | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN); 817 818 mii_mediachg(mii); 819 callout_schedule(&sc->sc_stat_ch, hz); 820 821 return 0; 822 } 823 824 static void 825 sun4i_emac_ifwatchdog(struct ifnet *ifp) 826 { 827 struct sun4i_emac_softc * const sc = ifp->if_softc; 828 829 device_printf(sc->sc_dev, "device timeout\n"); 830 831 ifp->if_oerrors++; 832 sun4i_emac_ifinit(ifp); 833 sun4i_emac_ifstart(ifp); 834 } 835 836 static void 837 sun4i_emac_rx_hash(struct sun4i_emac_softc *sc) 838 { 839 struct ifnet * const ifp = &sc->sc_ec.ec_if; 840 struct ether_multistep step; 841 struct ether_multi *enm; 842 uint32_t hash[2]; 843 uint32_t rxctl; 844 845 rxctl = sun4i_emac_read(sc, EMAC_RX_CTL_REG); 846 rxctl &= ~EMAC_RX_CTL_MHF; 847 rxctl |= EMAC_RX_CTL_UCAD; 848 rxctl |= EMAC_RX_CTL_DAF; 849 rxctl |= EMAC_RX_CTL_MC0; 850 rxctl |= EMAC_RX_CTL_BC0; 851 rxctl |= EMAC_RX_CTL_POR; 852 853 hash[0] = hash[1] = ~0; 854 if (ifp->if_flags & IFF_PROMISC) { 855 ifp->if_flags |= IFF_ALLMULTI; 856 rxctl |= EMAC_RX_CTL_PROMISC; 857 } else { 858 rxctl &= ~EMAC_RX_CTL_PROMISC; 859 } 860 861 if ((ifp->if_flags & IFF_PROMISC) == 0) { 862 hash[0] = hash[1] = 0; 863 864 ETHER_FIRST_MULTI(step, &sc->sc_ec, enm); 865 while (enm != NULL) { 866 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 867 /* 868 * We must listen to a range of multicast addresses. 869 * For now, just accept all multicasts, rather than 870 * trying to set only those filter bits needed to match 871 * the range. (At this time, the only use of address 872 * ranges is for IP multicast routing, for which the 873 * range is big enough to require all bits set.) 874 */ 875 hash[0] = hash[1] = ~0; 876 ifp->if_flags |= IFF_ALLMULTI; 877 goto done; 878 } 879 880 u_int crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 881 882 /* Just want the 6 most significant bits. */ 883 crc >>= 26; 884 885 /* Set the corresponding bit in the filter. */ 886 hash[crc >> 5] |= __BIT(crc & 31); 887 ETHER_NEXT_MULTI(step, enm); 888 } 889 ifp->if_flags &= ~IFF_ALLMULTI; 890 rxctl |= EMAC_RX_CTL_MHF; 891 } 892 893 done: 894 895 sun4i_emac_write(sc, EMAC_RX_HASH0_REG, hash[0]); 896 sun4i_emac_write(sc, EMAC_RX_HASH1_REG, hash[1]); 897 898 sun4i_emac_write(sc, EMAC_RX_CTL_REG, rxctl); 899 } 900
Indexes created Thu Oct 02 01:09:59 GMT 2025