1 1.1 tnn /* $NetBSD: sun4i_spireg.h,v 1.1 2019/08/03 13:28:42 tnn Exp $ */ 2 1.1 tnn 3 1.1 tnn /* 4 1.1 tnn * Copyright (c) 2019 Tobias Nygren 5 1.1 tnn * All rights reserved. 6 1.1 tnn * 7 1.1 tnn * Redistribution and use in source and binary forms, with or without 8 1.1 tnn * modification, are permitted provided that the following conditions 9 1.1 tnn * are met: 10 1.1 tnn * 1. Redistributions of source code must retain the above copyright 11 1.1 tnn * notice, this list of conditions and the following disclaimer. 12 1.1 tnn * 2. Redistributions in binary form must reproduce the above copyright 13 1.1 tnn * notice, this list of conditions and the following disclaimer in the 14 1.1 tnn * documentation and/or other materials provided with the distribution. 15 1.1 tnn * 16 1.1 tnn * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 1.1 tnn * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 1.1 tnn * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 1.1 tnn * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 1.1 tnn * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 1.1 tnn * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 1.1 tnn * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 1.1 tnn * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 1.1 tnn * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 1.1 tnn * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 1.1 tnn * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 1.1 tnn */ 28 1.1 tnn 29 1.1 tnn #ifndef _SUNXI_SUN4I_SPIREG_H_ 30 1.1 tnn #define _SUNXI_SUN4I_SPIREG_H_ 31 1.1 tnn 32 1.1 tnn #include <sys/cdefs.h> 33 1.1 tnn 34 1.1 tnn #define SPI_RXDATA 0x00 35 1.1 tnn 36 1.1 tnn #define SPI_TXDATA 0x04 37 1.1 tnn 38 1.1 tnn #define SPI_CTL 0x08 39 1.1 tnn #define SPI_CTL_SDM __BIT(20) 40 1.1 tnn #define SPI_CTL_SDC __BIT(19) 41 1.1 tnn #define SPI_CTL_TP_EN __BIT(18) 42 1.1 tnn #define SPI_CTL_SS_LEVEL __BIT(17) 43 1.1 tnn #define SPI_CTL_SS_CTRL __BIT(16) 44 1.1 tnn #define SPI_CTL_DHB __BIT(15) 45 1.1 tnn #define SPI_CTL_DDB __BIT(14) 46 1.1 tnn #define SPI_CTL_SS __BITS(13, 12) 47 1.1 tnn #define SPI_CTL_RPSM __BIT(11) 48 1.1 tnn #define SPI_CTL_XCH __BIT(10) 49 1.1 tnn #define SPI_CTL_RF_RST __BIT(9) 50 1.1 tnn #define SPI_CTL_TF_RST __BIT(8) 51 1.1 tnn #define SPI_CTL_SSCTL __BIT(7) 52 1.1 tnn #define SPI_CTL_LMTF __BIT(6) 53 1.1 tnn #define SPI_CTL_DMAMC __BIT(5) 54 1.1 tnn #define SPI_CTL_SSPOL __BIT(4) 55 1.1 tnn #define SPI_CTL_POL __BIT(3) 56 1.1 tnn #define SPI_CTL_PHA __BIT(2) 57 1.1 tnn #define SPI_CTL_MODE __BIT(1) 58 1.1 tnn #define SPI_CTL_EN __BIT(0) 59 1.1 tnn 60 1.1 tnn #define SPI_INTCTL 0x0c 61 1.1 tnn #define SPI_INTCTL_SS_INT_EN __BIT(17) 62 1.1 tnn #define SPI_INTCTL_TX_INT_EN __BIT(16) 63 1.1 tnn #define SPI_INTCTL_TF_UR_INT_EN __BIT(14) 64 1.1 tnn #define SPI_INTCTL_TF_OF_INT_EN __BIT(13) 65 1.1 tnn #define SPI_INTCTL_TF_E34_INT_EN __BIT(12) 66 1.1 tnn #define SPI_INTCTL_TF_E14_INT_EN __BIT(11) 67 1.1 tnn #define SPI_INTCTL_TF_FL_INT_EN __BIT(10) 68 1.1 tnn #define SPI_INTCTL_TF_HALF_EMP_INT_EN __BIT(9) 69 1.1 tnn #define SPI_INTCTL_TF_EMP_INT_EN __BIT(8) 70 1.1 tnn #define SPI_INTCTL_RF_UR_INT_EN __BIT(6) 71 1.1 tnn #define SPI_INTCTL_RF_OF_INT_EN __BIT(5) 72 1.1 tnn #define SPI_INTCTL_RF_F34_INT_EN __BIT(4) 73 1.1 tnn #define SPI_INTCTL_RF_F14_INT_EN __BIT(3) 74 1.1 tnn #define SPI_INTCTL_RF_FU_INT_EN __BIT(2) 75 1.1 tnn #define SPI_INTCTL_RF_HALF_FU_INT_EN __BIT(1) 76 1.1 tnn #define SPI_INTCTL_RF_RDY_INT_EN __BIT(0) 77 1.1 tnn 78 1.1 tnn #define SPI_INT_STA 0x10 79 1.1 tnn #define SPI_INT_STA_INT_CBF __BIT(31) 80 1.1 tnn #define SPI_INT_STA_SSI __BIT(17) 81 1.1 tnn #define SPI_INT_STA_TC __BIT(16) 82 1.1 tnn #define SPI_INT_STA_TU __BIT(14) 83 1.1 tnn #define SPI_INT_STA_TO __BIT(13) 84 1.1 tnn #define SPI_INT_STA_TE34 __BIT(12) 85 1.1 tnn #define SPI_INT_STA_TE14 __BIT(11) 86 1.1 tnn #define SPI_INT_STA_TF __BIT(10) 87 1.1 tnn #define SPI_INT_STA_THE __BIT(9) 88 1.1 tnn #define SPI_INT_STA_TE __BIT(8) 89 1.1 tnn #define SPI_INT_STA_RU __BIT(6) 90 1.1 tnn #define SPI_INT_STA_RO __BIT(5) 91 1.1 tnn #define SPI_INT_STA_RF34 __BIT(4) 92 1.1 tnn #define SPI_INT_STA_RF14 __BIT(3) 93 1.1 tnn #define SPI_INT_STA_RF __BIT(2) 94 1.1 tnn #define SPI_INT_STA_RHF __BIT(1) 95 1.1 tnn #define SPI_INT_STA_RR __BIT(0) 96 1.1 tnn 97 1.1 tnn #define SPI_DMACTL 0x14 98 1.1 tnn #define SPI_DMACTL_TF_EMP34_DMA __BIT(12) 99 1.1 tnn #define SPI_DMACTL_TF_EMP14_DMA __BIT(11) 100 1.1 tnn #define SPI_DMACTL_TF_NF_DMA __BIT(10) 101 1.1 tnn #define SPI_DMACTL_TF_HE_DMA __BIT(9) 102 1.1 tnn #define SPI_DMACTL_TF_EMP_DMA __BIT(8) 103 1.1 tnn #define SPI_DMACTL_RF_FU34_DMA __BIT(4) 104 1.1 tnn #define SPI_DMACTL_RF_FU14_DMA __BIT(3) 105 1.1 tnn #define SPI_DMACTL_RF_FU_DMA __BIT(2) 106 1.1 tnn #define SPI_DMACTL_RF_HF_DMA __BIT(1) 107 1.1 tnn #define SPI_DMACTL_RF_RDY_DMA __BIT(0) 108 1.1 tnn 109 1.1 tnn #define SPI_WAIT 0x18 110 1.1 tnn #define SPI_WAIT_WCC __BITS(15, 0) 111 1.1 tnn 112 1.1 tnn #define SPI_CCTL 0x1c 113 1.1 tnn #define SPI_CCTL_DRS __BIT(12) 114 1.1 tnn #define SPI_CCTL_CDR1 __BITS(11, 8) 115 1.1 tnn #define SPI_CCTL_CDR2 __BITS(7, 0) 116 1.1 tnn 117 1.1 tnn #define SPI_BC 0x20 118 1.1 tnn #define SPI_BC_BC __BITS(23, 0) 119 1.1 tnn 120 1.1 tnn #define SPI_TC 0x24 121 1.1 tnn #define SPI_TC_WTC __BITS(23, 0) 122 1.1 tnn 123 1.1 tnn #define SPI_FIFO_STA 0x28 124 1.1 tnn #define SPI_FIFO_STA_TF_CNT __BITS(22, 16) 125 1.1 tnn #define SPI_FIFO_STA_RF_CNT __BITS(6, 0) 126 1.1 tnn 127 1.1 tnn #endif /* _SUNXI_SUN4I_SPIREG_H_ */ 128