sun50i_h6_ccu.c revision 1.1
1 /* $NetBSD: sun50i_h6_ccu.c,v 1.1 2018/05/01 19:53:14 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(1, "$NetBSD: sun50i_h6_ccu.c,v 1.1 2018/05/01 19:53:14 jmcneill Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/systm.h> 37 38 #include <dev/fdt/fdtvar.h> 39 40 #include <arm/sunxi/sunxi_ccu.h> 41 #include <arm/sunxi/sun50i_h6_ccu.h> 42 43 #define PLL_PERI0_CTRL_REG 0x020 44 #define AHB3_CFG_REG 0x51c 45 #define APB2_CFG_REG 0x524 46 #define MBUS_CFG_REG 0x540 47 #define DE_BGR_REG 0x60c 48 #define DI_BGR_REG 0x62c 49 #define GPU_BGR_REG 0x67c 50 #define CE_BGR_REG 0x68c 51 #define VE_BGR_REG 0x69c 52 #define EMCE_BGR_REG 0x6bc 53 #define VP9_BGR_REG 0x6cc 54 #define DMA_BGR_REG 0x70c 55 #define MSGBOX_BGR_REG 0x71c 56 #define SPINLOCK_BGR_REG 0x72c 57 #define HSTIMER_BGR_REG 0x73c 58 #define DBGSYS_BGR_REG 0x78c 59 #define PSI_BGR_REG 0x79c 60 #define PWM_BGR_REG 0x7ac 61 #define DRAM_CLK_REG 0x800 62 #define NAND_BGR_REG 0x82c 63 #define SMHC0_CLK_REG 0x830 64 #define SMHC1_CLK_REG 0x834 65 #define SMHC2_CLK_REG 0x838 66 #define SMHC_BGR_REG 0x84c 67 #define UART_BGR_REG 0x90c 68 #define TWI_BGR_REG 0x91c 69 #define SCR_BGR_REG 0x93c 70 #define SPI_BGR_REG 0x96c 71 #define EMAC_BGR_REG 0x97c 72 #define TS_BGR_REG 0x9bc 73 #define CIRTX_BGR_REG 0x9cc 74 #define THS_BGR_REG 0x9fc 75 #define I2S_PCM_BGR_REG 0xa1c 76 #define OWA_BGR_REG 0xa2c 77 #define DMIC_BGR_REG 0xa4c 78 #define AUDIO_HUB_BGR_REG 0xa6c 79 #define USB0_CLK_REG 0xa70 80 #define USB1_CLK_REG 0xa74 81 #define USB3_CLK_REG 0xa7c 82 #define USB_BGR_REG 0xa8c 83 #define PCIE_BGR_REG 0xabc 84 #define HDMI_BGR_REG 0xb1c 85 #define DISPLAY_IF_TOP_BGR_REG 0xb5c 86 #define TCON_LCD_BGR_REG 0xb7c 87 #define TCON_TV_BGR_REG 0xb9c 88 #define CSI_BGR_REG 0xc2c 89 #define HDMI_HDCP_BGR_REG 0xc4c 90 91 static int sun50i_h6_ccu_match(device_t, cfdata_t, void *); 92 static void sun50i_h6_ccu_attach(device_t, device_t, void *); 93 94 static const char * const compatible[] = { 95 "allwinner,sun50i-h6-ccu", 96 NULL 97 }; 98 99 CFATTACH_DECL_NEW(sunxi_h6_ccu, sizeof(struct sunxi_ccu_softc), 100 sun50i_h6_ccu_match, sun50i_h6_ccu_attach, NULL, NULL); 101 102 static struct sunxi_ccu_reset sun50i_h6_ccu_resets[] = { 103 SUNXI_CCU_RESET(H6_RST_MBUS, MBUS_CFG_REG, 30), 104 105 SUNXI_CCU_RESET(H6_RST_BUS_DE, DE_BGR_REG, 16), 106 107 SUNXI_CCU_RESET(H6_RST_BUS_DEINTERLACE, DI_BGR_REG, 16), 108 109 SUNXI_CCU_RESET(H6_RST_BUS_GPU, GPU_BGR_REG, 16), 110 111 SUNXI_CCU_RESET(H6_RST_BUS_CE, CE_BGR_REG, 16), 112 113 SUNXI_CCU_RESET(H6_RST_BUS_VE, VE_BGR_REG, 16), 114 115 SUNXI_CCU_RESET(H6_RST_BUS_EMCE, EMCE_BGR_REG, 16), 116 117 SUNXI_CCU_RESET(H6_RST_BUS_VP9, VP9_BGR_REG, 16), 118 119 SUNXI_CCU_RESET(H6_RST_BUS_DMA, DMA_BGR_REG, 16), 120 121 SUNXI_CCU_RESET(H6_RST_BUS_MSGBOX, MSGBOX_BGR_REG, 16), 122 123 SUNXI_CCU_RESET(H6_RST_BUS_SPINLOCK, SPINLOCK_BGR_REG, 16), 124 125 SUNXI_CCU_RESET(H6_RST_BUS_HSTIMER, HSTIMER_BGR_REG, 16), 126 127 SUNXI_CCU_RESET(H6_RST_BUS_DBG, DBGSYS_BGR_REG, 16), 128 129 SUNXI_CCU_RESET(H6_RST_BUS_PSI, PSI_BGR_REG, 16), 130 131 SUNXI_CCU_RESET(H6_RST_BUS_PWM, PWM_BGR_REG, 16), 132 133 /* H6_RST_BUS_IOMMU: No bit defined in user manual */ 134 135 SUNXI_CCU_RESET(H6_RST_BUS_DRAM, DRAM_CLK_REG, 30), 136 137 SUNXI_CCU_RESET(H6_RST_BUS_NAND, NAND_BGR_REG, 16), 138 139 SUNXI_CCU_RESET(H6_RST_BUS_MMC0, SMHC_BGR_REG, 16), 140 SUNXI_CCU_RESET(H6_RST_BUS_MMC1, SMHC_BGR_REG, 17), 141 SUNXI_CCU_RESET(H6_RST_BUS_MMC2, SMHC_BGR_REG, 18), 142 143 SUNXI_CCU_RESET(H6_RST_BUS_UART0, UART_BGR_REG, 16), 144 SUNXI_CCU_RESET(H6_RST_BUS_UART1, UART_BGR_REG, 17), 145 SUNXI_CCU_RESET(H6_RST_BUS_UART2, UART_BGR_REG, 18), 146 SUNXI_CCU_RESET(H6_RST_BUS_UART3, UART_BGR_REG, 19), 147 148 SUNXI_CCU_RESET(H6_RST_BUS_I2C0, TWI_BGR_REG, 16), 149 SUNXI_CCU_RESET(H6_RST_BUS_I2C1, TWI_BGR_REG, 17), 150 SUNXI_CCU_RESET(H6_RST_BUS_I2C2, TWI_BGR_REG, 18), 151 SUNXI_CCU_RESET(H6_RST_BUS_I2C3, TWI_BGR_REG, 19), 152 153 SUNXI_CCU_RESET(H6_RST_BUS_SCR0, SCR_BGR_REG, 16), 154 SUNXI_CCU_RESET(H6_RST_BUS_SCR1, SCR_BGR_REG, 17), 155 156 SUNXI_CCU_RESET(H6_RST_BUS_SPI0, SPI_BGR_REG, 16), 157 SUNXI_CCU_RESET(H6_RST_BUS_SPI1, SPI_BGR_REG, 17), 158 159 SUNXI_CCU_RESET(H6_RST_BUS_EMAC, EMAC_BGR_REG, 16), 160 161 SUNXI_CCU_RESET(H6_RST_BUS_TS, TS_BGR_REG, 16), 162 163 SUNXI_CCU_RESET(H6_RST_BUS_IR_TX, CIRTX_BGR_REG, 16), 164 165 SUNXI_CCU_RESET(H6_RST_BUS_THS, THS_BGR_REG, 16), 166 167 SUNXI_CCU_RESET(H6_RST_BUS_I2S0, I2S_PCM_BGR_REG, 16), 168 SUNXI_CCU_RESET(H6_RST_BUS_I2S1, I2S_PCM_BGR_REG, 17), 169 SUNXI_CCU_RESET(H6_RST_BUS_I2S2, I2S_PCM_BGR_REG, 18), 170 SUNXI_CCU_RESET(H6_RST_BUS_I2S3, I2S_PCM_BGR_REG, 19), 171 172 SUNXI_CCU_RESET(H6_RST_BUS_SPDIF, OWA_BGR_REG, 16), 173 174 SUNXI_CCU_RESET(H6_RST_BUS_DMIC, DMIC_BGR_REG, 16), 175 176 SUNXI_CCU_RESET(H6_RST_BUS_AUDIO_HUB, AUDIO_HUB_BGR_REG, 16), 177 178 SUNXI_CCU_RESET(H6_RST_USB_PHY0, USB0_CLK_REG, 30), 179 180 SUNXI_CCU_RESET(H6_RST_USB_PHY1, USB1_CLK_REG, 30), 181 182 SUNXI_CCU_RESET(H6_RST_USB_PHY3, USB3_CLK_REG, 30), 183 SUNXI_CCU_RESET(H6_RST_USB_HSIC, USB3_CLK_REG, 28), 184 185 SUNXI_CCU_RESET(H6_RST_BUS_OHCI0, USB_BGR_REG, 16), 186 SUNXI_CCU_RESET(H6_RST_BUS_OHCI3, USB_BGR_REG, 19), 187 SUNXI_CCU_RESET(H6_RST_BUS_EHCI0, USB_BGR_REG, 20), 188 SUNXI_CCU_RESET(H6_RST_BUS_XHCI, USB_BGR_REG, 21), 189 SUNXI_CCU_RESET(H6_RST_BUS_EHCI3, USB_BGR_REG, 23), 190 SUNXI_CCU_RESET(H6_RST_BUS_OTG, USB_BGR_REG, 24), 191 192 SUNXI_CCU_RESET(H6_RST_BUS_PCIE, PCIE_BGR_REG, 16), 193 SUNXI_CCU_RESET(H6_RST_PCIE_POWERUP, PCIE_BGR_REG, 17), 194 195 SUNXI_CCU_RESET(H6_RST_BUS_HDMI, HDMI_BGR_REG, 16), 196 SUNXI_CCU_RESET(H6_RST_BUS_HDMI_SUB, HDMI_BGR_REG, 17), 197 198 SUNXI_CCU_RESET(H6_RST_BUS_TCON_TOP, DISPLAY_IF_TOP_BGR_REG, 16), 199 200 SUNXI_CCU_RESET(H6_RST_BUS_TCON_LCD0, TCON_LCD_BGR_REG, 16), 201 202 SUNXI_CCU_RESET(H6_RST_BUS_TCON_TV0, TCON_TV_BGR_REG, 16), 203 204 SUNXI_CCU_RESET(H6_RST_BUS_CSI, CSI_BGR_REG, 16), 205 206 SUNXI_CCU_RESET(H6_RST_BUS_HDCP, HDMI_HDCP_BGR_REG, 16), 207 }; 208 209 static const char *ahb3_parents[] = { "hosc", "losc", "psi", "pll_periph0" }; 210 static const char *apb2_parents[] = { "hosc", "losc", "psi", "pll_periph0" }; 211 static const char *mod_parents[] = { "hosc", "pll_periph0_2x", "pll_periph1_2x" }; 212 213 static struct sunxi_ccu_clk sun50i_h6_ccu_clks[] = { 214 SUNXI_CCU_FIXED_FACTOR(H6_CLK_OSC12M, "osc12m", "hosc", 2, 1), 215 216 SUNXI_CCU_NKMP(H6_CLK_PLL_PERIPH0_4X, "pll_periph0_4x", "hosc", 217 PLL_PERI0_CTRL_REG, /* reg */ 218 __BITS(15,8), /* n */ 219 0, /* k */ 220 __BIT(1), /* m */ 221 __BIT(0), /* p */ 222 __BIT(31), /* enable */ 223 0), 224 SUNXI_CCU_FIXED_FACTOR(H6_CLK_PLL_PERIPH0_2X, "pll_periph0_2x", "pll_periph0_4x", 2, 1), 225 SUNXI_CCU_FIXED_FACTOR(H6_CLK_PLL_PERIPH0, "pll_periph0", "pll_periph0_4x", 4, 1), 226 227 SUNXI_CCU_NM(H6_CLK_AHB3, "ahb3", ahb3_parents, 228 AHB3_CFG_REG, /* reg */ 229 __BITS(9,8), /* n */ 230 __BITS(1,0), /* m */ 231 __BITS(25,24), /* sel */ 232 0, /* enable */ 233 SUNXI_CCU_NM_POWER_OF_TWO), 234 235 SUNXI_CCU_NM(H6_CLK_APB2, "apb2", apb2_parents, 236 APB2_CFG_REG, /* reg */ 237 __BITS(9,8), /* n */ 238 __BITS(1,0), /* m */ 239 __BITS(25,24), /* sel */ 240 0, /* enable */ 241 SUNXI_CCU_NM_POWER_OF_TWO), 242 243 SUNXI_CCU_NM(H6_CLK_MMC0, "mmc0", mod_parents, 244 SMHC0_CLK_REG, /* reg */ 245 __BITS(9,8), /* n */ 246 __BITS(3,0), /* m */ 247 __BITS(25,24), /* sel */ 248 __BIT(31), /* enable */ 249 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 250 SUNXI_CCU_NM(H6_CLK_MMC1, "mmc1", mod_parents, 251 SMHC1_CLK_REG, /* reg */ 252 __BITS(9,8), /* n */ 253 __BITS(3,0), /* m */ 254 __BITS(25,24), /* sel */ 255 __BIT(31), /* enable */ 256 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 257 SUNXI_CCU_NM(H6_CLK_MMC2, "mmc2", mod_parents, 258 SMHC2_CLK_REG, /* reg */ 259 __BITS(9,8), /* n */ 260 __BITS(3,0), /* m */ 261 __BITS(25,24), /* sel */ 262 __BIT(31), /* enable */ 263 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 264 SUNXI_CCU_GATE(H6_CLK_BUS_MMC0, "bus-mmc0", "mmc0", 265 SMHC_BGR_REG, 0), 266 SUNXI_CCU_GATE(H6_CLK_BUS_MMC1, "bus-mmc1", "mmc1", 267 SMHC_BGR_REG, 1), 268 SUNXI_CCU_GATE(H6_CLK_BUS_MMC2, "bus-mmc2", "mmc2", 269 SMHC_BGR_REG, 2), 270 271 SUNXI_CCU_GATE(H6_CLK_BUS_UART0, "bus-uart0", "apb2", 272 UART_BGR_REG, 0), 273 SUNXI_CCU_GATE(H6_CLK_BUS_UART1, "bus-uart1", "apb2", 274 UART_BGR_REG, 1), 275 SUNXI_CCU_GATE(H6_CLK_BUS_UART2, "bus-uart2", "apb2", 276 UART_BGR_REG, 2), 277 SUNXI_CCU_GATE(H6_CLK_BUS_UART3, "bus-uart3", "apb2", 278 UART_BGR_REG, 3), 279 280 SUNXI_CCU_GATE(H6_CLK_BUS_I2C0, "bus-i2c0", "apb2", 281 TWI_BGR_REG, 0), 282 SUNXI_CCU_GATE(H6_CLK_BUS_I2C1, "bus-i2c1", "apb2", 283 TWI_BGR_REG, 1), 284 SUNXI_CCU_GATE(H6_CLK_BUS_I2C2, "bus-i2c2", "apb2", 285 TWI_BGR_REG, 2), 286 SUNXI_CCU_GATE(H6_CLK_BUS_I2C3, "bus-i2c3", "apb2", 287 TWI_BGR_REG, 3), 288 289 SUNXI_CCU_GATE(H6_CLK_USB_OHCI0, "usb-ohci0", "ahb3", 290 USB0_CLK_REG, 31), 291 SUNXI_CCU_GATE(H6_CLK_USB_PHY0, "usb-phy0", "ahb3", 292 USB0_CLK_REG, 29), 293 294 SUNXI_CCU_GATE(H6_CLK_USB_PHY1, "usb-phy1", "ahb3", 295 USB1_CLK_REG, 29), 296 297 SUNXI_CCU_GATE(H6_CLK_USB_OHCI3, "usb-ohci3", "ahb3", 298 USB3_CLK_REG, 31), 299 SUNXI_CCU_GATE(H6_CLK_USB_PHY3, "usb-phy3", "ahb3", 300 USB3_CLK_REG, 29), 301 SUNXI_CCU_GATE(H6_CLK_USB_HSIC_12M, "usb-hsic-12m", "osc12m", 302 USB3_CLK_REG, 27), 303 SUNXI_CCU_GATE(H6_CLK_USB_HSIC, "usb-hsic", "ahb3", 304 USB3_CLK_REG, 26), 305 306 SUNXI_CCU_GATE(H6_CLK_BUS_OHCI0, "bus-ohci0", "ahb3", 307 USB_BGR_REG, 0), 308 SUNXI_CCU_GATE(H6_CLK_BUS_OHCI3, "bus-ohci3", "ahb3", 309 USB_BGR_REG, 3), 310 SUNXI_CCU_GATE(H6_CLK_BUS_EHCI0, "bus-ehci0", "ahb3", 311 USB_BGR_REG, 4), 312 SUNXI_CCU_GATE(H6_CLK_BUS_XHCI, "bus-xhci", "ahb3", 313 USB_BGR_REG, 5), 314 SUNXI_CCU_GATE(H6_CLK_BUS_EHCI3, "bus-ehci3", "ahb3", 315 USB_BGR_REG, 7), 316 SUNXI_CCU_GATE(H6_CLK_BUS_OTG, "bus-otg", "ahb3", 317 USB_BGR_REG, 8), 318 319 SUNXI_CCU_GATE(H6_CLK_BUS_EMAC, "bus-emac", "ahb3", 320 EMAC_BGR_REG, 0), 321 }; 322 323 static int 324 sun50i_h6_ccu_match(device_t parent, cfdata_t cf, void *aux) 325 { 326 struct fdt_attach_args * const faa = aux; 327 328 return of_match_compatible(faa->faa_phandle, compatible); 329 } 330 331 static void 332 sun50i_h6_ccu_attach(device_t parent, device_t self, void *aux) 333 { 334 struct sunxi_ccu_softc * const sc = device_private(self); 335 struct fdt_attach_args * const faa = aux; 336 337 sc->sc_dev = self; 338 sc->sc_phandle = faa->faa_phandle; 339 sc->sc_bst = faa->faa_bst; 340 341 sc->sc_resets = sun50i_h6_ccu_resets; 342 sc->sc_nresets = __arraycount(sun50i_h6_ccu_resets); 343 344 sc->sc_clks = sun50i_h6_ccu_clks; 345 sc->sc_nclks = __arraycount(sun50i_h6_ccu_clks); 346 347 if (sunxi_ccu_attach(sc) != 0) 348 return; 349 350 aprint_naive("\n"); 351 aprint_normal(": H6 CCU\n"); 352 353 sunxi_ccu_print(sc); 354 } 355
Indexes created Fri Oct 03 15:10:06 GMT 2025