sun50i_h6_ccu.c revision 1.2
1 /* $NetBSD: sun50i_h6_ccu.c,v 1.2 2019/02/13 18:18:38 jakllsch Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(1, "$NetBSD: sun50i_h6_ccu.c,v 1.2 2019/02/13 18:18:38 jakllsch Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/systm.h> 37 38 #include <dev/fdt/fdtvar.h> 39 40 #include <arm/sunxi/sunxi_ccu.h> 41 #include <arm/sunxi/sun50i_h6_ccu.h> 42 43 #define PLL_CPUX_CTRL_REG 0x000 44 #define PLL_PERI0_CTRL_REG 0x020 45 #define AHB3_CFG_REG 0x51c 46 #define APB2_CFG_REG 0x524 47 #define MBUS_CFG_REG 0x540 48 #define DE_BGR_REG 0x60c 49 #define DI_BGR_REG 0x62c 50 #define GPU_BGR_REG 0x67c 51 #define CE_BGR_REG 0x68c 52 #define VE_BGR_REG 0x69c 53 #define EMCE_BGR_REG 0x6bc 54 #define VP9_BGR_REG 0x6cc 55 #define DMA_BGR_REG 0x70c 56 #define MSGBOX_BGR_REG 0x71c 57 #define SPINLOCK_BGR_REG 0x72c 58 #define HSTIMER_BGR_REG 0x73c 59 #define DBGSYS_BGR_REG 0x78c 60 #define PSI_BGR_REG 0x79c 61 #define PWM_BGR_REG 0x7ac 62 #define DRAM_CLK_REG 0x800 63 #define NAND_BGR_REG 0x82c 64 #define SMHC0_CLK_REG 0x830 65 #define SMHC1_CLK_REG 0x834 66 #define SMHC2_CLK_REG 0x838 67 #define SMHC_BGR_REG 0x84c 68 #define UART_BGR_REG 0x90c 69 #define TWI_BGR_REG 0x91c 70 #define SCR_BGR_REG 0x93c 71 #define SPI_BGR_REG 0x96c 72 #define EMAC_BGR_REG 0x97c 73 #define TS_BGR_REG 0x9bc 74 #define CIRTX_BGR_REG 0x9cc 75 #define THS_BGR_REG 0x9fc 76 #define I2S_PCM_BGR_REG 0xa1c 77 #define OWA_BGR_REG 0xa2c 78 #define DMIC_BGR_REG 0xa4c 79 #define AUDIO_HUB_BGR_REG 0xa6c 80 #define USB0_CLK_REG 0xa70 81 #define USB1_CLK_REG 0xa74 82 #define USB3_CLK_REG 0xa7c 83 #define USB_BGR_REG 0xa8c 84 #define PCIE_BGR_REG 0xabc 85 #define HDMI_BGR_REG 0xb1c 86 #define DISPLAY_IF_TOP_BGR_REG 0xb5c 87 #define TCON_LCD_BGR_REG 0xb7c 88 #define TCON_TV_BGR_REG 0xb9c 89 #define CSI_BGR_REG 0xc2c 90 #define HDMI_HDCP_BGR_REG 0xc4c 91 92 static int sun50i_h6_ccu_match(device_t, cfdata_t, void *); 93 static void sun50i_h6_ccu_attach(device_t, device_t, void *); 94 95 static const char * const compatible[] = { 96 "allwinner,sun50i-h6-ccu", 97 NULL 98 }; 99 100 CFATTACH_DECL_NEW(sunxi_h6_ccu, sizeof(struct sunxi_ccu_softc), 101 sun50i_h6_ccu_match, sun50i_h6_ccu_attach, NULL, NULL); 102 103 static struct sunxi_ccu_reset sun50i_h6_ccu_resets[] = { 104 SUNXI_CCU_RESET(H6_RST_MBUS, MBUS_CFG_REG, 30), 105 106 SUNXI_CCU_RESET(H6_RST_BUS_DE, DE_BGR_REG, 16), 107 108 SUNXI_CCU_RESET(H6_RST_BUS_DEINTERLACE, DI_BGR_REG, 16), 109 110 SUNXI_CCU_RESET(H6_RST_BUS_GPU, GPU_BGR_REG, 16), 111 112 SUNXI_CCU_RESET(H6_RST_BUS_CE, CE_BGR_REG, 16), 113 114 SUNXI_CCU_RESET(H6_RST_BUS_VE, VE_BGR_REG, 16), 115 116 SUNXI_CCU_RESET(H6_RST_BUS_EMCE, EMCE_BGR_REG, 16), 117 118 SUNXI_CCU_RESET(H6_RST_BUS_VP9, VP9_BGR_REG, 16), 119 120 SUNXI_CCU_RESET(H6_RST_BUS_DMA, DMA_BGR_REG, 16), 121 122 SUNXI_CCU_RESET(H6_RST_BUS_MSGBOX, MSGBOX_BGR_REG, 16), 123 124 SUNXI_CCU_RESET(H6_RST_BUS_SPINLOCK, SPINLOCK_BGR_REG, 16), 125 126 SUNXI_CCU_RESET(H6_RST_BUS_HSTIMER, HSTIMER_BGR_REG, 16), 127 128 SUNXI_CCU_RESET(H6_RST_BUS_DBG, DBGSYS_BGR_REG, 16), 129 130 SUNXI_CCU_RESET(H6_RST_BUS_PSI, PSI_BGR_REG, 16), 131 132 SUNXI_CCU_RESET(H6_RST_BUS_PWM, PWM_BGR_REG, 16), 133 134 /* H6_RST_BUS_IOMMU: No bit defined in user manual */ 135 136 SUNXI_CCU_RESET(H6_RST_BUS_DRAM, DRAM_CLK_REG, 30), 137 138 SUNXI_CCU_RESET(H6_RST_BUS_NAND, NAND_BGR_REG, 16), 139 140 SUNXI_CCU_RESET(H6_RST_BUS_MMC0, SMHC_BGR_REG, 16), 141 SUNXI_CCU_RESET(H6_RST_BUS_MMC1, SMHC_BGR_REG, 17), 142 SUNXI_CCU_RESET(H6_RST_BUS_MMC2, SMHC_BGR_REG, 18), 143 144 SUNXI_CCU_RESET(H6_RST_BUS_UART0, UART_BGR_REG, 16), 145 SUNXI_CCU_RESET(H6_RST_BUS_UART1, UART_BGR_REG, 17), 146 SUNXI_CCU_RESET(H6_RST_BUS_UART2, UART_BGR_REG, 18), 147 SUNXI_CCU_RESET(H6_RST_BUS_UART3, UART_BGR_REG, 19), 148 149 SUNXI_CCU_RESET(H6_RST_BUS_I2C0, TWI_BGR_REG, 16), 150 SUNXI_CCU_RESET(H6_RST_BUS_I2C1, TWI_BGR_REG, 17), 151 SUNXI_CCU_RESET(H6_RST_BUS_I2C2, TWI_BGR_REG, 18), 152 SUNXI_CCU_RESET(H6_RST_BUS_I2C3, TWI_BGR_REG, 19), 153 154 SUNXI_CCU_RESET(H6_RST_BUS_SCR0, SCR_BGR_REG, 16), 155 SUNXI_CCU_RESET(H6_RST_BUS_SCR1, SCR_BGR_REG, 17), 156 157 SUNXI_CCU_RESET(H6_RST_BUS_SPI0, SPI_BGR_REG, 16), 158 SUNXI_CCU_RESET(H6_RST_BUS_SPI1, SPI_BGR_REG, 17), 159 160 SUNXI_CCU_RESET(H6_RST_BUS_EMAC, EMAC_BGR_REG, 16), 161 162 SUNXI_CCU_RESET(H6_RST_BUS_TS, TS_BGR_REG, 16), 163 164 SUNXI_CCU_RESET(H6_RST_BUS_IR_TX, CIRTX_BGR_REG, 16), 165 166 SUNXI_CCU_RESET(H6_RST_BUS_THS, THS_BGR_REG, 16), 167 168 SUNXI_CCU_RESET(H6_RST_BUS_I2S0, I2S_PCM_BGR_REG, 16), 169 SUNXI_CCU_RESET(H6_RST_BUS_I2S1, I2S_PCM_BGR_REG, 17), 170 SUNXI_CCU_RESET(H6_RST_BUS_I2S2, I2S_PCM_BGR_REG, 18), 171 SUNXI_CCU_RESET(H6_RST_BUS_I2S3, I2S_PCM_BGR_REG, 19), 172 173 SUNXI_CCU_RESET(H6_RST_BUS_SPDIF, OWA_BGR_REG, 16), 174 175 SUNXI_CCU_RESET(H6_RST_BUS_DMIC, DMIC_BGR_REG, 16), 176 177 SUNXI_CCU_RESET(H6_RST_BUS_AUDIO_HUB, AUDIO_HUB_BGR_REG, 16), 178 179 SUNXI_CCU_RESET(H6_RST_USB_PHY0, USB0_CLK_REG, 30), 180 181 SUNXI_CCU_RESET(H6_RST_USB_PHY1, USB1_CLK_REG, 30), 182 183 SUNXI_CCU_RESET(H6_RST_USB_PHY3, USB3_CLK_REG, 30), 184 SUNXI_CCU_RESET(H6_RST_USB_HSIC, USB3_CLK_REG, 28), 185 186 SUNXI_CCU_RESET(H6_RST_BUS_OHCI0, USB_BGR_REG, 16), 187 SUNXI_CCU_RESET(H6_RST_BUS_OHCI3, USB_BGR_REG, 19), 188 SUNXI_CCU_RESET(H6_RST_BUS_EHCI0, USB_BGR_REG, 20), 189 SUNXI_CCU_RESET(H6_RST_BUS_XHCI, USB_BGR_REG, 21), 190 SUNXI_CCU_RESET(H6_RST_BUS_EHCI3, USB_BGR_REG, 23), 191 SUNXI_CCU_RESET(H6_RST_BUS_OTG, USB_BGR_REG, 24), 192 193 SUNXI_CCU_RESET(H6_RST_BUS_PCIE, PCIE_BGR_REG, 16), 194 SUNXI_CCU_RESET(H6_RST_PCIE_POWERUP, PCIE_BGR_REG, 17), 195 196 SUNXI_CCU_RESET(H6_RST_BUS_HDMI, HDMI_BGR_REG, 16), 197 SUNXI_CCU_RESET(H6_RST_BUS_HDMI_SUB, HDMI_BGR_REG, 17), 198 199 SUNXI_CCU_RESET(H6_RST_BUS_TCON_TOP, DISPLAY_IF_TOP_BGR_REG, 16), 200 201 SUNXI_CCU_RESET(H6_RST_BUS_TCON_LCD0, TCON_LCD_BGR_REG, 16), 202 203 SUNXI_CCU_RESET(H6_RST_BUS_TCON_TV0, TCON_TV_BGR_REG, 16), 204 205 SUNXI_CCU_RESET(H6_RST_BUS_CSI, CSI_BGR_REG, 16), 206 207 SUNXI_CCU_RESET(H6_RST_BUS_HDCP, HDMI_HDCP_BGR_REG, 16), 208 }; 209 210 static const char *ahb3_parents[] = { "hosc", "losc", "psi", "pll_periph0" }; 211 static const char *apb2_parents[] = { "hosc", "losc", "psi", "pll_periph0" }; 212 static const char *mod_parents[] = { "hosc", "pll_periph0_2x", "pll_periph1_2x" }; 213 214 static struct sunxi_ccu_clk sun50i_h6_ccu_clks[] = { 215 SUNXI_CCU_FIXED_FACTOR(H6_CLK_OSC12M, "osc12m", "hosc", 2, 1), 216 217 SUNXI_CCU_NKMP_TABLE(H6_CLK_PLL_CPUX, "pll_cpux", "hosc", 218 PLL_CPUX_CTRL_REG, /* reg */ 219 __BITS(15,8), /* n */ 220 0, /* k */ 221 __BITS(1,0), /* m */ 222 __BITS(17,16), /* p */ 223 __BIT(31), /* enable */ 224 __BIT(28), /* lock */ 225 NULL, /* table */ 226 SUNXI_CCU_NKMP_SCALE_CLOCK | SUNXI_CCU_NKMP_FACTOR_P_POW2), 227 228 SUNXI_CCU_NKMP(H6_CLK_PLL_PERIPH0_4X, "pll_periph0_4x", "hosc", 229 PLL_PERI0_CTRL_REG, /* reg */ 230 __BITS(15,8), /* n */ 231 0, /* k */ 232 __BIT(1), /* m */ 233 __BIT(0), /* p */ 234 __BIT(31), /* enable */ 235 0), 236 SUNXI_CCU_FIXED_FACTOR(H6_CLK_PLL_PERIPH0_2X, "pll_periph0_2x", "pll_periph0_4x", 2, 1), 237 SUNXI_CCU_FIXED_FACTOR(H6_CLK_PLL_PERIPH0, "pll_periph0", "pll_periph0_4x", 4, 1), 238 239 SUNXI_CCU_NM(H6_CLK_AHB3, "ahb3", ahb3_parents, 240 AHB3_CFG_REG, /* reg */ 241 __BITS(9,8), /* n */ 242 __BITS(1,0), /* m */ 243 __BITS(25,24), /* sel */ 244 0, /* enable */ 245 SUNXI_CCU_NM_POWER_OF_TWO), 246 247 SUNXI_CCU_NM(H6_CLK_APB2, "apb2", apb2_parents, 248 APB2_CFG_REG, /* reg */ 249 __BITS(9,8), /* n */ 250 __BITS(1,0), /* m */ 251 __BITS(25,24), /* sel */ 252 0, /* enable */ 253 SUNXI_CCU_NM_POWER_OF_TWO), 254 255 SUNXI_CCU_NM(H6_CLK_MMC0, "mmc0", mod_parents, 256 SMHC0_CLK_REG, /* reg */ 257 __BITS(9,8), /* n */ 258 __BITS(3,0), /* m */ 259 __BITS(25,24), /* sel */ 260 __BIT(31), /* enable */ 261 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 262 SUNXI_CCU_NM(H6_CLK_MMC1, "mmc1", mod_parents, 263 SMHC1_CLK_REG, /* reg */ 264 __BITS(9,8), /* n */ 265 __BITS(3,0), /* m */ 266 __BITS(25,24), /* sel */ 267 __BIT(31), /* enable */ 268 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 269 SUNXI_CCU_NM(H6_CLK_MMC2, "mmc2", mod_parents, 270 SMHC2_CLK_REG, /* reg */ 271 __BITS(9,8), /* n */ 272 __BITS(3,0), /* m */ 273 __BITS(25,24), /* sel */ 274 __BIT(31), /* enable */ 275 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 276 SUNXI_CCU_GATE(H6_CLK_BUS_MMC0, "bus-mmc0", "mmc0", 277 SMHC_BGR_REG, 0), 278 SUNXI_CCU_GATE(H6_CLK_BUS_MMC1, "bus-mmc1", "mmc1", 279 SMHC_BGR_REG, 1), 280 SUNXI_CCU_GATE(H6_CLK_BUS_MMC2, "bus-mmc2", "mmc2", 281 SMHC_BGR_REG, 2), 282 283 SUNXI_CCU_GATE(H6_CLK_BUS_UART0, "bus-uart0", "apb2", 284 UART_BGR_REG, 0), 285 SUNXI_CCU_GATE(H6_CLK_BUS_UART1, "bus-uart1", "apb2", 286 UART_BGR_REG, 1), 287 SUNXI_CCU_GATE(H6_CLK_BUS_UART2, "bus-uart2", "apb2", 288 UART_BGR_REG, 2), 289 SUNXI_CCU_GATE(H6_CLK_BUS_UART3, "bus-uart3", "apb2", 290 UART_BGR_REG, 3), 291 292 SUNXI_CCU_GATE(H6_CLK_BUS_I2C0, "bus-i2c0", "apb2", 293 TWI_BGR_REG, 0), 294 SUNXI_CCU_GATE(H6_CLK_BUS_I2C1, "bus-i2c1", "apb2", 295 TWI_BGR_REG, 1), 296 SUNXI_CCU_GATE(H6_CLK_BUS_I2C2, "bus-i2c2", "apb2", 297 TWI_BGR_REG, 2), 298 SUNXI_CCU_GATE(H6_CLK_BUS_I2C3, "bus-i2c3", "apb2", 299 TWI_BGR_REG, 3), 300 301 SUNXI_CCU_GATE(H6_CLK_USB_OHCI0, "usb-ohci0", "ahb3", 302 USB0_CLK_REG, 31), 303 SUNXI_CCU_GATE(H6_CLK_USB_PHY0, "usb-phy0", "ahb3", 304 USB0_CLK_REG, 29), 305 306 SUNXI_CCU_GATE(H6_CLK_USB_PHY1, "usb-phy1", "ahb3", 307 USB1_CLK_REG, 29), 308 309 SUNXI_CCU_GATE(H6_CLK_USB_OHCI3, "usb-ohci3", "ahb3", 310 USB3_CLK_REG, 31), 311 SUNXI_CCU_GATE(H6_CLK_USB_PHY3, "usb-phy3", "ahb3", 312 USB3_CLK_REG, 29), 313 SUNXI_CCU_GATE(H6_CLK_USB_HSIC_12M, "usb-hsic-12m", "osc12m", 314 USB3_CLK_REG, 27), 315 SUNXI_CCU_GATE(H6_CLK_USB_HSIC, "usb-hsic", "ahb3", 316 USB3_CLK_REG, 26), 317 318 SUNXI_CCU_GATE(H6_CLK_BUS_OHCI0, "bus-ohci0", "ahb3", 319 USB_BGR_REG, 0), 320 SUNXI_CCU_GATE(H6_CLK_BUS_OHCI3, "bus-ohci3", "ahb3", 321 USB_BGR_REG, 3), 322 SUNXI_CCU_GATE(H6_CLK_BUS_EHCI0, "bus-ehci0", "ahb3", 323 USB_BGR_REG, 4), 324 SUNXI_CCU_GATE(H6_CLK_BUS_XHCI, "bus-xhci", "ahb3", 325 USB_BGR_REG, 5), 326 SUNXI_CCU_GATE(H6_CLK_BUS_EHCI3, "bus-ehci3", "ahb3", 327 USB_BGR_REG, 7), 328 SUNXI_CCU_GATE(H6_CLK_BUS_OTG, "bus-otg", "ahb3", 329 USB_BGR_REG, 8), 330 331 SUNXI_CCU_GATE(H6_CLK_BUS_EMAC, "bus-emac", "ahb3", 332 EMAC_BGR_REG, 0), 333 }; 334 335 static int 336 sun50i_h6_ccu_match(device_t parent, cfdata_t cf, void *aux) 337 { 338 struct fdt_attach_args * const faa = aux; 339 340 return of_match_compatible(faa->faa_phandle, compatible); 341 } 342 343 static void 344 sun50i_h6_ccu_attach(device_t parent, device_t self, void *aux) 345 { 346 struct sunxi_ccu_softc * const sc = device_private(self); 347 struct fdt_attach_args * const faa = aux; 348 349 sc->sc_dev = self; 350 sc->sc_phandle = faa->faa_phandle; 351 sc->sc_bst = faa->faa_bst; 352 353 sc->sc_resets = sun50i_h6_ccu_resets; 354 sc->sc_nresets = __arraycount(sun50i_h6_ccu_resets); 355 356 sc->sc_clks = sun50i_h6_ccu_clks; 357 sc->sc_nclks = __arraycount(sun50i_h6_ccu_clks); 358 359 if (sunxi_ccu_attach(sc) != 0) 360 return; 361 362 aprint_naive("\n"); 363 aprint_normal(": H6 CCU\n"); 364 365 sunxi_ccu_print(sc); 366 } 367
Indexes created Fri Oct 03 15:10:06 GMT 2025