sun5i_a13_ccu.c revision 1.3.2.2
1 1.3.2.2 skrll /* $NetBSD: sun5i_a13_ccu.c,v 1.3.2.2 2017/08/28 17:51:32 skrll Exp $ */ 2 1.3.2.2 skrll 3 1.3.2.2 skrll /*- 4 1.3.2.2 skrll * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 1.3.2.2 skrll * All rights reserved. 6 1.3.2.2 skrll * 7 1.3.2.2 skrll * Redistribution and use in source and binary forms, with or without 8 1.3.2.2 skrll * modification, are permitted provided that the following conditions 9 1.3.2.2 skrll * are met: 10 1.3.2.2 skrll * 1. Redistributions of source code must retain the above copyright 11 1.3.2.2 skrll * notice, this list of conditions and the following disclaimer. 12 1.3.2.2 skrll * 2. Redistributions in binary form must reproduce the above copyright 13 1.3.2.2 skrll * notice, this list of conditions and the following disclaimer in the 14 1.3.2.2 skrll * documentation and/or other materials provided with the distribution. 15 1.3.2.2 skrll * 16 1.3.2.2 skrll * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 1.3.2.2 skrll * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 1.3.2.2 skrll * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 1.3.2.2 skrll * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 1.3.2.2 skrll * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 1.3.2.2 skrll * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 1.3.2.2 skrll * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 1.3.2.2 skrll * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 1.3.2.2 skrll * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 1.3.2.2 skrll * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 1.3.2.2 skrll * SUCH DAMAGE. 27 1.3.2.2 skrll */ 28 1.3.2.2 skrll 29 1.3.2.2 skrll #include <sys/cdefs.h> 30 1.3.2.2 skrll 31 1.3.2.2 skrll __KERNEL_RCSID(1, "$NetBSD: sun5i_a13_ccu.c,v 1.3.2.2 2017/08/28 17:51:32 skrll Exp $"); 32 1.3.2.2 skrll 33 1.3.2.2 skrll #include <sys/param.h> 34 1.3.2.2 skrll #include <sys/bus.h> 35 1.3.2.2 skrll #include <sys/device.h> 36 1.3.2.2 skrll #include <sys/systm.h> 37 1.3.2.2 skrll 38 1.3.2.2 skrll #include <dev/fdt/fdtvar.h> 39 1.3.2.2 skrll 40 1.3.2.2 skrll #include <arm/sunxi/sunxi_ccu.h> 41 1.3.2.2 skrll #include <arm/sunxi/sun5i_a13_ccu.h> 42 1.3.2.2 skrll 43 1.3.2.2 skrll #define PLL1_CFG_REG 0x000 44 1.3.2.2 skrll #define PLL6_CFG_REG 0x028 45 1.3.2.2 skrll #define OSC24M_CFG_REG 0x050 46 1.3.2.2 skrll #define CPU_AHB_APB0_CFG_REG 0x054 47 1.3.2.2 skrll #define APB1_CLK_DIV_REG 0x058 48 1.3.2.2 skrll #define AHB_GATING_REG0 0x060 49 1.3.2.2 skrll #define AHB_GATING_REG1 0x064 50 1.3.2.2 skrll #define APB0_GATING_REG 0x068 51 1.3.2.2 skrll #define APB1_GATING_REG 0x06c 52 1.3.2.2 skrll #define USBPHY_CFG_REG 0x0cc 53 1.3.2.2 skrll #define BE_CFG_REG 0x104 54 1.3.2.2 skrll #define FE_CFG_REG 0x10c 55 1.3.2.2 skrll #define CSI_CFG_REG 0x134 56 1.3.2.2 skrll #define VE_CFG_REG 0x13c 57 1.3.2.2 skrll #define MALI_CLOCK_CFG_REG 0x154 58 1.3.2.2 skrll #define IEP_SCLK_CFG_REG 0x160 59 1.3.2.2 skrll 60 1.3.2.2 skrll static int sun5i_a13_ccu_match(device_t, cfdata_t, void *); 61 1.3.2.2 skrll static void sun5i_a13_ccu_attach(device_t, device_t, void *); 62 1.3.2.2 skrll 63 1.3.2.2 skrll static const char * const compatible[] = { 64 1.3.2.2 skrll "allwinner,sun5i-a13-ccu", 65 1.3.2.2 skrll NULL 66 1.3.2.2 skrll }; 67 1.3.2.2 skrll 68 1.3.2.2 skrll CFATTACH_DECL_NEW(sunxi_a13_ccu, sizeof(struct sunxi_ccu_softc), 69 1.3.2.2 skrll sun5i_a13_ccu_match, sun5i_a13_ccu_attach, NULL, NULL); 70 1.3.2.2 skrll 71 1.3.2.2 skrll static struct sunxi_ccu_reset sun5i_a13_ccu_resets[] = { 72 1.3.2.2 skrll SUNXI_CCU_RESET(A13_RST_USB_PHY0, USBPHY_CFG_REG, 0), 73 1.3.2.2 skrll SUNXI_CCU_RESET(A13_RST_USB_PHY1, USBPHY_CFG_REG, 1), 74 1.3.2.2 skrll 75 1.3.2.2 skrll /* Missing: GPS */ 76 1.3.2.2 skrll 77 1.3.2.2 skrll SUNXI_CCU_RESET(A13_RST_DE_BE, BE_CFG_REG, 30), 78 1.3.2.2 skrll 79 1.3.2.2 skrll SUNXI_CCU_RESET(A13_RST_DE_FE, FE_CFG_REG, 30), 80 1.3.2.2 skrll 81 1.3.2.2 skrll /* Missing: TVE */ 82 1.3.2.2 skrll 83 1.3.2.2 skrll /* Missing: LCD */ 84 1.3.2.2 skrll 85 1.3.2.2 skrll SUNXI_CCU_RESET(A13_RST_CSI, CSI_CFG_REG, 30), 86 1.3.2.2 skrll 87 1.3.2.2 skrll SUNXI_CCU_RESET(A13_RST_VE, VE_CFG_REG, 0), 88 1.3.2.2 skrll 89 1.3.2.2 skrll SUNXI_CCU_RESET(A13_RST_GPU, MALI_CLOCK_CFG_REG, 30), 90 1.3.2.2 skrll 91 1.3.2.2 skrll SUNXI_CCU_RESET(A13_RST_IEP, IEP_SCLK_CFG_REG, 30), 92 1.3.2.2 skrll }; 93 1.3.2.2 skrll 94 1.3.2.2 skrll static const char *cpu_parents[] = { "losc", "osc24m", "pll_core", "pll_periph" }; 95 1.3.2.2 skrll static const char *axi_parents[] = { "cpu" }; 96 1.3.2.2 skrll static const char *ahb_parents[] = { "axi", "cpu", "pll_periph", NULL }; 97 1.3.2.2 skrll static const char *apb0_parents[] = { "ahb" }; 98 1.3.2.2 skrll static const char *apb1_parents[] = { "osc24m", "pll_periph", "losc", NULL }; 99 1.3.2.2 skrll 100 1.3.2.2 skrll static struct sunxi_ccu_clk sun5i_a13_ccu_clks[] = { 101 1.3.2.2 skrll SUNXI_CCU_GATE(A13_CLK_HOSC, "osc24m", "hosc", 102 1.3.2.2 skrll OSC24M_CFG_REG, 0), 103 1.3.2.2 skrll 104 1.3.2.2 skrll SUNXI_CCU_NKMP(A13_CLK_PLL_CORE, "pll_core", "osc24m", 105 1.3.2.2 skrll PLL1_CFG_REG, /* reg */ 106 1.3.2.2 skrll __BITS(12,8), /* n */ 107 1.3.2.2 skrll __BITS(5,4), /* k */ 108 1.3.2.2 skrll __BITS(1,0), /* m */ 109 1.3.2.2 skrll __BITS(17,16), /* p */ 110 1.3.2.2 skrll __BIT(31), /* enable */ 111 1.3.2.2 skrll SUNXI_CCU_NKMP_FACTOR_P_POW2 | SUNXI_CCU_NKMP_FACTOR_N_EXACT), 112 1.3.2.2 skrll 113 1.3.2.2 skrll SUNXI_CCU_NKMP(A13_CLK_PERIPH, "pll_periph", "osc24m", 114 1.3.2.2 skrll PLL6_CFG_REG, /* reg */ 115 1.3.2.2 skrll __BITS(12,8), /* n */ 116 1.3.2.2 skrll __BITS(5,4), /* k */ 117 1.3.2.2 skrll __BITS(1,0), /* m */ 118 1.3.2.2 skrll 0, /* p */ 119 1.3.2.2 skrll __BIT(31), /* enable */ 120 1.3.2.2 skrll SUNXI_CCU_NKMP_DIVIDE_BY_TWO | SUNXI_CCU_NKMP_FACTOR_N_EXACT), 121 1.3.2.2 skrll 122 1.3.2.2 skrll SUNXI_CCU_PREDIV_FIXED(A13_CLK_CPU, "cpu", cpu_parents, 123 1.3.2.2 skrll CPU_AHB_APB0_CFG_REG, /* reg */ 124 1.3.2.2 skrll 0, /* prediv */ 125 1.3.2.2 skrll __BIT(3), /* prediv_sel */ 126 1.3.2.2 skrll 6, /* prediv_fixed */ 127 1.3.2.2 skrll 0, /* div */ 128 1.3.2.2 skrll __BITS(17,16), /* sel */ 129 1.3.2.2 skrll 0), 130 1.3.2.2 skrll 131 1.3.2.2 skrll SUNXI_CCU_DIV(A13_CLK_AXI, "axi", axi_parents, 132 1.3.2.2 skrll CPU_AHB_APB0_CFG_REG, /* reg */ 133 1.3.2.2 skrll __BITS(1,0), /* div */ 134 1.3.2.2 skrll 0, /* sel */ 135 1.3.2.2 skrll 0), 136 1.3.2.2 skrll 137 1.3.2.2 skrll SUNXI_CCU_DIV(A13_CLK_AHB, "ahb", ahb_parents, 138 1.3.2.2 skrll CPU_AHB_APB0_CFG_REG, /* reg */ 139 1.3.2.2 skrll 0, /* div */ 140 1.3.2.2 skrll __BITS(5,4), /* sel */ 141 1.3.2.2 skrll SUNXI_CCU_DIV_POWER_OF_TWO), 142 1.3.2.2 skrll 143 1.3.2.2 skrll SUNXI_CCU_DIV(A13_CLK_APB0, "apb0", apb0_parents, 144 1.3.2.2 skrll CPU_AHB_APB0_CFG_REG, /* reg */ 145 1.3.2.2 skrll __BITS(9,8), /* div */ 146 1.3.2.2 skrll 0, /* sel */ 147 1.3.2.2 skrll SUNXI_CCU_DIV_ZERO_IS_ONE | SUNXI_CCU_DIV_POWER_OF_TWO), 148 1.3.2.2 skrll 149 1.3.2.2 skrll SUNXI_CCU_NM(A13_CLK_APB1, "apb1", apb1_parents, 150 1.3.2.2 skrll APB1_CLK_DIV_REG, /* reg */ 151 1.3.2.2 skrll __BITS(17,16), /* n */ 152 1.3.2.2 skrll __BITS(4,0), /* m */ 153 1.3.2.2 skrll __BITS(25,24), /* sel */ 154 1.3.2.2 skrll 0, /* enable */ 155 1.3.2.2 skrll SUNXI_CCU_NM_POWER_OF_TWO), 156 1.3.2.2 skrll 157 1.3.2.2 skrll /* AHB_GATING_REG0. Missing: SS, EMAC, TS, GPS */ 158 1.3.2.2 skrll SUNXI_CCU_GATE(A13_CLK_AHB_OTG, "ahb-otg", "ahb", 159 1.3.2.2 skrll AHB_GATING_REG0, 0), 160 1.3.2.2 skrll SUNXI_CCU_GATE(A13_CLK_AHB_EHCI, "ahb-ehci", "ahb", 161 1.3.2.2 skrll AHB_GATING_REG0, 1), 162 1.3.2.2 skrll SUNXI_CCU_GATE(A13_CLK_AHB_OHCI, "ahb-ohci", "ahb", 163 1.3.2.2 skrll AHB_GATING_REG0, 2), 164 1.3.2.2 skrll SUNXI_CCU_GATE(A13_CLK_AHB_DMA, "ahb-dma", "ahb", 165 1.3.2.2 skrll AHB_GATING_REG0, 6), 166 1.3.2.2 skrll SUNXI_CCU_GATE(A13_CLK_AHB_BIST, "ahb-bist", "ahb", 167 1.3.2.2 skrll AHB_GATING_REG0, 7), 168 1.3.2.2 skrll SUNXI_CCU_GATE(A13_CLK_AHB_MMC0, "ahb-mmc0", "ahb", 169 1.3.2.2 skrll AHB_GATING_REG0, 8), 170 1.3.2.2 skrll SUNXI_CCU_GATE(A13_CLK_AHB_MMC1, "ahb-mmc1", "ahb", 171 1.3.2.2 skrll AHB_GATING_REG0, 9), 172 1.3.2.2 skrll SUNXI_CCU_GATE(A13_CLK_AHB_MMC2, "ahb-mmc2", "ahb", 173 1.3.2.2 skrll AHB_GATING_REG0, 10), 174 1.3.2.2 skrll SUNXI_CCU_GATE(A13_CLK_AHB_NAND, "ahb-nand", "ahb", 175 1.3.2.2 skrll AHB_GATING_REG0, 13), 176 1.3.2.2 skrll SUNXI_CCU_GATE(A13_CLK_AHB_SDRAM, "ahb-sdram", "ahb", 177 1.3.2.2 skrll AHB_GATING_REG0, 14), 178 1.3.2.2 skrll SUNXI_CCU_GATE(A13_CLK_AHB_SPI0, "ahb-spi0", "ahb", 179 1.3.2.2 skrll AHB_GATING_REG0, 20), 180 1.3.2.2 skrll SUNXI_CCU_GATE(A13_CLK_AHB_SPI1, "ahb-spi1", "ahb", 181 1.3.2.2 skrll AHB_GATING_REG0, 21), 182 1.3.2.2 skrll SUNXI_CCU_GATE(A13_CLK_AHB_SPI2, "ahb-spi2", "ahb", 183 1.3.2.2 skrll AHB_GATING_REG0, 22), 184 1.3.2.2 skrll SUNXI_CCU_GATE(A13_CLK_AHB_HSTIMER, "ahb-hstimer", "ahb", 185 1.3.2.2 skrll AHB_GATING_REG0, 28), 186 1.3.2.2 skrll 187 1.3.2.2 skrll /* AHB_GATING_REG1. Missing: TVE, HDMI */ 188 1.3.2.2 skrll SUNXI_CCU_GATE(A13_CLK_AHB_VE, "ahb-ve", "ahb", 189 1.3.2.2 skrll AHB_GATING_REG1, 0), 190 1.3.2.2 skrll SUNXI_CCU_GATE(A13_CLK_AHB_LCD, "ahb-lcd", "ahb", 191 1.3.2.2 skrll AHB_GATING_REG1, 4), 192 1.3.2.2 skrll SUNXI_CCU_GATE(A13_CLK_AHB_CSI, "ahb-csi", "ahb", 193 1.3.2.2 skrll AHB_GATING_REG1, 8), 194 1.3.2.2 skrll SUNXI_CCU_GATE(A13_CLK_AHB_DE_BE, "ahb-de_be", "ahb", 195 1.3.2.2 skrll AHB_GATING_REG1, 12), 196 1.3.2.2 skrll SUNXI_CCU_GATE(A13_CLK_AHB_DE_FE, "ahb-de_fe", "ahb", 197 1.3.2.2 skrll AHB_GATING_REG1, 14), 198 1.3.2.2 skrll SUNXI_CCU_GATE(A13_CLK_AHB_IEP, "ahb-iep", "ahb", 199 1.3.2.2 skrll AHB_GATING_REG1, 19), 200 1.3.2.2 skrll SUNXI_CCU_GATE(A13_CLK_AHB_GPU, "ahb-gpu", "ahb", 201 1.3.2.2 skrll AHB_GATING_REG1, 20), 202 1.3.2.2 skrll 203 1.3.2.2 skrll /* APB0_GATING_REG. Missing: SPDIF, I2S, KEYPAD */ 204 1.3.2.2 skrll SUNXI_CCU_GATE(A13_CLK_APB0_CODEC, "apb0-codec", "apb0", 205 1.3.2.2 skrll APB0_GATING_REG, 0), 206 1.3.2.2 skrll SUNXI_CCU_GATE(A13_CLK_APB0_PIO, "apb0-pio", "apb0", 207 1.3.2.2 skrll APB0_GATING_REG, 5), 208 1.3.2.2 skrll SUNXI_CCU_GATE(A13_CLK_APB0_IR, "apb0-ir", "apb0", 209 1.3.2.2 skrll APB0_GATING_REG, 6), 210 1.3.2.2 skrll 211 1.3.2.2 skrll /* APB1_GATING_REG. Missing: UART0, UART2 */ 212 1.3.2.2 skrll SUNXI_CCU_GATE(A13_CLK_APB1_I2C0, "apb1-i2c0", "apb1", 213 1.3.2.2 skrll APB1_GATING_REG, 0), 214 1.3.2.2 skrll SUNXI_CCU_GATE(A13_CLK_APB1_I2C1, "apb1-i2c1", "apb1", 215 1.3.2.2 skrll APB1_GATING_REG, 1), 216 1.3.2.2 skrll SUNXI_CCU_GATE(A13_CLK_APB1_I2C2, "apb1-i2c2", "apb1", 217 1.3.2.2 skrll APB1_GATING_REG, 2), 218 1.3.2.2 skrll SUNXI_CCU_GATE(A13_CLK_APB1_UART1, "apb1-uart1", "apb1", 219 1.3.2.2 skrll APB1_GATING_REG, 17), 220 1.3.2.2 skrll SUNXI_CCU_GATE(A13_CLK_APB1_UART3, "apb1-uart3", "apb1", 221 1.3.2.2 skrll APB1_GATING_REG, 19), 222 1.3.2.2 skrll 223 1.3.2.2 skrll /* USBPHY_CFG_REG */ 224 1.3.2.2 skrll SUNXI_CCU_GATE(A13_CLK_USB_OHCI, "usb-ohci", "osc24m", 225 1.3.2.2 skrll USBPHY_CFG_REG, 6), 226 1.3.2.2 skrll SUNXI_CCU_GATE(A13_CLK_USB_PHY0, "usb-phy0", "osc24m", 227 1.3.2.2 skrll USBPHY_CFG_REG, 8), 228 1.3.2.2 skrll SUNXI_CCU_GATE(A13_CLK_USB_PHY1, "usb-phy1", "osc24m", 229 1.3.2.2 skrll USBPHY_CFG_REG, 9), 230 1.3.2.2 skrll }; 231 1.3.2.2 skrll 232 1.3.2.2 skrll static int 233 1.3.2.2 skrll sun5i_a13_ccu_match(device_t parent, cfdata_t cf, void *aux) 234 1.3.2.2 skrll { 235 1.3.2.2 skrll struct fdt_attach_args * const faa = aux; 236 1.3.2.2 skrll 237 1.3.2.2 skrll return of_match_compatible(faa->faa_phandle, compatible); 238 1.3.2.2 skrll } 239 1.3.2.2 skrll 240 1.3.2.2 skrll static void 241 1.3.2.2 skrll sun5i_a13_ccu_attach(device_t parent, device_t self, void *aux) 242 1.3.2.2 skrll { 243 1.3.2.2 skrll struct sunxi_ccu_softc * const sc = device_private(self); 244 1.3.2.2 skrll struct fdt_attach_args * const faa = aux; 245 1.3.2.2 skrll 246 1.3.2.2 skrll sc->sc_dev = self; 247 1.3.2.2 skrll sc->sc_phandle = faa->faa_phandle; 248 1.3.2.2 skrll sc->sc_bst = faa->faa_bst; 249 1.3.2.2 skrll 250 1.3.2.2 skrll sc->sc_resets = sun5i_a13_ccu_resets; 251 1.3.2.2 skrll sc->sc_nresets = __arraycount(sun5i_a13_ccu_resets); 252 1.3.2.2 skrll 253 1.3.2.2 skrll sc->sc_clks = sun5i_a13_ccu_clks; 254 1.3.2.2 skrll sc->sc_nclks = __arraycount(sun5i_a13_ccu_clks); 255 1.3.2.2 skrll 256 1.3.2.2 skrll if (sunxi_ccu_attach(sc) != 0) 257 1.3.2.2 skrll return; 258 1.3.2.2 skrll 259 1.3.2.2 skrll aprint_naive("\n"); 260 1.3.2.2 skrll aprint_normal(": A13 CCU\n"); 261 1.3.2.2 skrll 262 1.3.2.2 skrll sunxi_ccu_print(sc); 263 1.3.2.2 skrll } 264
Indexes created Thu Oct 23 22:10:10 GMT 2025