sun5i_a13_ccu.c revision 1.5.2.2
1 1.5.2.2 jdolecek /* $NetBSD: sun5i_a13_ccu.c,v 1.5.2.2 2017/12/03 11:35:56 jdolecek Exp $ */ 2 1.5.2.2 jdolecek 3 1.5.2.2 jdolecek /*- 4 1.5.2.2 jdolecek * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 1.5.2.2 jdolecek * All rights reserved. 6 1.5.2.2 jdolecek * 7 1.5.2.2 jdolecek * Redistribution and use in source and binary forms, with or without 8 1.5.2.2 jdolecek * modification, are permitted provided that the following conditions 9 1.5.2.2 jdolecek * are met: 10 1.5.2.2 jdolecek * 1. Redistributions of source code must retain the above copyright 11 1.5.2.2 jdolecek * notice, this list of conditions and the following disclaimer. 12 1.5.2.2 jdolecek * 2. Redistributions in binary form must reproduce the above copyright 13 1.5.2.2 jdolecek * notice, this list of conditions and the following disclaimer in the 14 1.5.2.2 jdolecek * documentation and/or other materials provided with the distribution. 15 1.5.2.2 jdolecek * 16 1.5.2.2 jdolecek * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 1.5.2.2 jdolecek * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 1.5.2.2 jdolecek * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 1.5.2.2 jdolecek * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 1.5.2.2 jdolecek * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 1.5.2.2 jdolecek * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 1.5.2.2 jdolecek * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 1.5.2.2 jdolecek * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 1.5.2.2 jdolecek * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 1.5.2.2 jdolecek * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 1.5.2.2 jdolecek * SUCH DAMAGE. 27 1.5.2.2 jdolecek */ 28 1.5.2.2 jdolecek 29 1.5.2.2 jdolecek #include <sys/cdefs.h> 30 1.5.2.2 jdolecek 31 1.5.2.2 jdolecek __KERNEL_RCSID(1, "$NetBSD: sun5i_a13_ccu.c,v 1.5.2.2 2017/12/03 11:35:56 jdolecek Exp $"); 32 1.5.2.2 jdolecek 33 1.5.2.2 jdolecek #include <sys/param.h> 34 1.5.2.2 jdolecek #include <sys/bus.h> 35 1.5.2.2 jdolecek #include <sys/device.h> 36 1.5.2.2 jdolecek #include <sys/systm.h> 37 1.5.2.2 jdolecek 38 1.5.2.2 jdolecek #include <dev/fdt/fdtvar.h> 39 1.5.2.2 jdolecek 40 1.5.2.2 jdolecek #include <arm/sunxi/sunxi_ccu.h> 41 1.5.2.2 jdolecek #include <arm/sunxi/sun5i_a13_ccu.h> 42 1.5.2.2 jdolecek 43 1.5.2.2 jdolecek #define PLL1_CFG_REG 0x000 44 1.5.2.2 jdolecek #define PLL2_CFG_REG 0x008 45 1.5.2.2 jdolecek #define PLL6_CFG_REG 0x028 46 1.5.2.2 jdolecek #define OSC24M_CFG_REG 0x050 47 1.5.2.2 jdolecek #define CPU_AHB_APB0_CFG_REG 0x054 48 1.5.2.2 jdolecek #define APB1_CLK_DIV_REG 0x058 49 1.5.2.2 jdolecek #define AHB_GATING_REG0 0x060 50 1.5.2.2 jdolecek #define AHB_GATING_REG1 0x064 51 1.5.2.2 jdolecek #define APB0_GATING_REG 0x068 52 1.5.2.2 jdolecek #define APB1_GATING_REG 0x06c 53 1.5.2.2 jdolecek #define NAND_SCLK_CFG_REG 0x080 54 1.5.2.2 jdolecek #define SD0_SCLK_CFG_REG 0x088 55 1.5.2.2 jdolecek #define SD1_SCLK_CFG_REG 0x08c 56 1.5.2.2 jdolecek #define SD2_SCLK_CFG_REG 0x090 57 1.5.2.2 jdolecek #define USBPHY_CFG_REG 0x0cc 58 1.5.2.2 jdolecek #define BE_CFG_REG 0x104 59 1.5.2.2 jdolecek #define FE_CFG_REG 0x10c 60 1.5.2.2 jdolecek #define CSI_CFG_REG 0x134 61 1.5.2.2 jdolecek #define VE_CFG_REG 0x13c 62 1.5.2.2 jdolecek #define AUDIO_CODEC_SCLK_CFG_REG 0x140 63 1.5.2.2 jdolecek #define MALI_CLOCK_CFG_REG 0x154 64 1.5.2.2 jdolecek #define IEP_SCLK_CFG_REG 0x160 65 1.5.2.2 jdolecek 66 1.5.2.2 jdolecek static int sun5i_a13_ccu_match(device_t, cfdata_t, void *); 67 1.5.2.2 jdolecek static void sun5i_a13_ccu_attach(device_t, device_t, void *); 68 1.5.2.2 jdolecek 69 1.5.2.2 jdolecek static const char * const compatible[] = { 70 1.5.2.2 jdolecek "allwinner,sun5i-a13-ccu", 71 1.5.2.2 jdolecek "nextthing,gr8-ccu", 72 1.5.2.2 jdolecek NULL 73 1.5.2.2 jdolecek }; 74 1.5.2.2 jdolecek 75 1.5.2.2 jdolecek CFATTACH_DECL_NEW(sunxi_a13_ccu, sizeof(struct sunxi_ccu_softc), 76 1.5.2.2 jdolecek sun5i_a13_ccu_match, sun5i_a13_ccu_attach, NULL, NULL); 77 1.5.2.2 jdolecek 78 1.5.2.2 jdolecek static struct sunxi_ccu_reset sun5i_a13_ccu_resets[] = { 79 1.5.2.2 jdolecek SUNXI_CCU_RESET(A13_RST_USB_PHY0, USBPHY_CFG_REG, 0), 80 1.5.2.2 jdolecek SUNXI_CCU_RESET(A13_RST_USB_PHY1, USBPHY_CFG_REG, 1), 81 1.5.2.2 jdolecek 82 1.5.2.2 jdolecek /* Missing: GPS */ 83 1.5.2.2 jdolecek 84 1.5.2.2 jdolecek SUNXI_CCU_RESET(A13_RST_DE_BE, BE_CFG_REG, 30), 85 1.5.2.2 jdolecek 86 1.5.2.2 jdolecek SUNXI_CCU_RESET(A13_RST_DE_FE, FE_CFG_REG, 30), 87 1.5.2.2 jdolecek 88 1.5.2.2 jdolecek /* Missing: TVE */ 89 1.5.2.2 jdolecek 90 1.5.2.2 jdolecek /* Missing: LCD */ 91 1.5.2.2 jdolecek 92 1.5.2.2 jdolecek SUNXI_CCU_RESET(A13_RST_CSI, CSI_CFG_REG, 30), 93 1.5.2.2 jdolecek 94 1.5.2.2 jdolecek SUNXI_CCU_RESET(A13_RST_VE, VE_CFG_REG, 0), 95 1.5.2.2 jdolecek 96 1.5.2.2 jdolecek SUNXI_CCU_RESET(A13_RST_GPU, MALI_CLOCK_CFG_REG, 30), 97 1.5.2.2 jdolecek 98 1.5.2.2 jdolecek SUNXI_CCU_RESET(A13_RST_IEP, IEP_SCLK_CFG_REG, 30), 99 1.5.2.2 jdolecek }; 100 1.5.2.2 jdolecek 101 1.5.2.2 jdolecek static const char *cpu_parents[] = { "losc", "osc24m", "pll_core", "pll_periph" }; 102 1.5.2.2 jdolecek static const char *axi_parents[] = { "cpu" }; 103 1.5.2.2 jdolecek static const char *ahb_parents[] = { "axi", "cpu", "pll_periph" }; 104 1.5.2.2 jdolecek static const char *apb0_parents[] = { "ahb" }; 105 1.5.2.2 jdolecek static const char *apb1_parents[] = { "osc24m", "pll_periph", "losc" }; 106 1.5.2.2 jdolecek static const char *mod_parents[] = { "osc24m", "pll_periph", "pll_ddr" }; 107 1.5.2.2 jdolecek 108 1.5.2.2 jdolecek static const struct sunxi_ccu_nkmp_tbl sun5i_a13_ac_dig_table[] = { 109 1.5.2.2 jdolecek { 24576000, 86, 0, 21, 3 }, 110 1.5.2.2 jdolecek { 0 } 111 1.5.2.2 jdolecek }; 112 1.5.2.2 jdolecek 113 1.5.2.2 jdolecek static struct sunxi_ccu_clk sun5i_a13_ccu_clks[] = { 114 1.5.2.2 jdolecek SUNXI_CCU_GATE(A13_CLK_HOSC, "osc24m", "hosc", 115 1.5.2.2 jdolecek OSC24M_CFG_REG, 0), 116 1.5.2.2 jdolecek 117 1.5.2.2 jdolecek SUNXI_CCU_NKMP(A13_CLK_PLL_CORE, "pll_core", "osc24m", 118 1.5.2.2 jdolecek PLL1_CFG_REG, /* reg */ 119 1.5.2.2 jdolecek __BITS(12,8), /* n */ 120 1.5.2.2 jdolecek __BITS(5,4), /* k */ 121 1.5.2.2 jdolecek __BITS(1,0), /* m */ 122 1.5.2.2 jdolecek __BITS(17,16), /* p */ 123 1.5.2.2 jdolecek __BIT(31), /* enable */ 124 1.5.2.2 jdolecek SUNXI_CCU_NKMP_FACTOR_P_POW2 | SUNXI_CCU_NKMP_FACTOR_N_EXACT), 125 1.5.2.2 jdolecek 126 1.5.2.2 jdolecek SUNXI_CCU_NKMP_TABLE(A13_CLK_PLL_AUDIO_BASE, "pll_audio", "osc24m", 127 1.5.2.2 jdolecek PLL2_CFG_REG, /* reg */ 128 1.5.2.2 jdolecek __BITS(14,8), /* n */ 129 1.5.2.2 jdolecek 0, /* k */ 130 1.5.2.2 jdolecek __BITS(4,0), /* m */ 131 1.5.2.2 jdolecek __BITS(29,26), /* p */ 132 1.5.2.2 jdolecek __BIT(31), /* enable */ 133 1.5.2.2 jdolecek 0, /* lock */ 134 1.5.2.2 jdolecek sun5i_a13_ac_dig_table, /* table */ 135 1.5.2.2 jdolecek 0), 136 1.5.2.2 jdolecek 137 1.5.2.2 jdolecek SUNXI_CCU_NKMP(A13_CLK_PERIPH, "pll_periph", "osc24m", 138 1.5.2.2 jdolecek PLL6_CFG_REG, /* reg */ 139 1.5.2.2 jdolecek __BITS(12,8), /* n */ 140 1.5.2.2 jdolecek __BITS(5,4), /* k */ 141 1.5.2.2 jdolecek __BITS(1,0), /* m */ 142 1.5.2.2 jdolecek 0, /* p */ 143 1.5.2.2 jdolecek __BIT(31), /* enable */ 144 1.5.2.2 jdolecek SUNXI_CCU_NKMP_DIVIDE_BY_TWO | SUNXI_CCU_NKMP_FACTOR_N_EXACT), 145 1.5.2.2 jdolecek 146 1.5.2.2 jdolecek SUNXI_CCU_PREDIV_FIXED(A13_CLK_CPU, "cpu", cpu_parents, 147 1.5.2.2 jdolecek CPU_AHB_APB0_CFG_REG, /* reg */ 148 1.5.2.2 jdolecek 0, /* prediv */ 149 1.5.2.2 jdolecek __BIT(3), /* prediv_sel */ 150 1.5.2.2 jdolecek 6, /* prediv_fixed */ 151 1.5.2.2 jdolecek 0, /* div */ 152 1.5.2.2 jdolecek __BITS(17,16), /* sel */ 153 1.5.2.2 jdolecek 0), 154 1.5.2.2 jdolecek 155 1.5.2.2 jdolecek SUNXI_CCU_DIV(A13_CLK_AXI, "axi", axi_parents, 156 1.5.2.2 jdolecek CPU_AHB_APB0_CFG_REG, /* reg */ 157 1.5.2.2 jdolecek __BITS(1,0), /* div */ 158 1.5.2.2 jdolecek 0, /* sel */ 159 1.5.2.2 jdolecek 0), 160 1.5.2.2 jdolecek 161 1.5.2.2 jdolecek SUNXI_CCU_DIV(A13_CLK_AHB, "ahb", ahb_parents, 162 1.5.2.2 jdolecek CPU_AHB_APB0_CFG_REG, /* reg */ 163 1.5.2.2 jdolecek 0, /* div */ 164 1.5.2.2 jdolecek __BITS(5,4), /* sel */ 165 1.5.2.2 jdolecek SUNXI_CCU_DIV_POWER_OF_TWO), 166 1.5.2.2 jdolecek 167 1.5.2.2 jdolecek SUNXI_CCU_DIV(A13_CLK_APB0, "apb0", apb0_parents, 168 1.5.2.2 jdolecek CPU_AHB_APB0_CFG_REG, /* reg */ 169 1.5.2.2 jdolecek __BITS(9,8), /* div */ 170 1.5.2.2 jdolecek 0, /* sel */ 171 1.5.2.2 jdolecek SUNXI_CCU_DIV_ZERO_IS_ONE | SUNXI_CCU_DIV_POWER_OF_TWO), 172 1.5.2.2 jdolecek 173 1.5.2.2 jdolecek SUNXI_CCU_NM(A13_CLK_APB1, "apb1", apb1_parents, 174 1.5.2.2 jdolecek APB1_CLK_DIV_REG, /* reg */ 175 1.5.2.2 jdolecek __BITS(17,16), /* n */ 176 1.5.2.2 jdolecek __BITS(4,0), /* m */ 177 1.5.2.2 jdolecek __BITS(25,24), /* sel */ 178 1.5.2.2 jdolecek 0, /* enable */ 179 1.5.2.2 jdolecek SUNXI_CCU_NM_POWER_OF_TWO), 180 1.5.2.2 jdolecek 181 1.5.2.2 jdolecek SUNXI_CCU_NM(A13_CLK_MMC0, "mmc0", mod_parents, 182 1.5.2.2 jdolecek SD0_SCLK_CFG_REG, /* reg */ 183 1.5.2.2 jdolecek __BITS(17,16), /* n */ 184 1.5.2.2 jdolecek __BITS(3,0), /* m */ 185 1.5.2.2 jdolecek __BITS(25,24), /* sel */ 186 1.5.2.2 jdolecek __BIT(31), /* enable */ 187 1.5.2.2 jdolecek SUNXI_CCU_NM_POWER_OF_TWO), 188 1.5.2.2 jdolecek SUNXI_CCU_NM(A13_CLK_MMC1, "mmc1", mod_parents, 189 1.5.2.2 jdolecek SD1_SCLK_CFG_REG, /* reg */ 190 1.5.2.2 jdolecek __BITS(17,16), /* n */ 191 1.5.2.2 jdolecek __BITS(3,0), /* m */ 192 1.5.2.2 jdolecek __BITS(25,24), /* sel */ 193 1.5.2.2 jdolecek __BIT(31), /* enable */ 194 1.5.2.2 jdolecek SUNXI_CCU_NM_POWER_OF_TWO), 195 1.5.2.2 jdolecek SUNXI_CCU_NM(A13_CLK_MMC2, "mmc2", mod_parents, 196 1.5.2.2 jdolecek SD2_SCLK_CFG_REG, /* reg */ 197 1.5.2.2 jdolecek __BITS(17,16), /* n */ 198 1.5.2.2 jdolecek __BITS(3,0), /* m */ 199 1.5.2.2 jdolecek __BITS(25,24), /* sel */ 200 1.5.2.2 jdolecek __BIT(31), /* enable */ 201 1.5.2.2 jdolecek SUNXI_CCU_NM_POWER_OF_TWO), 202 1.5.2.2 jdolecek 203 1.5.2.2 jdolecek SUNXI_CCU_NM(A13_CLK_NAND, "nand", mod_parents, 204 1.5.2.2 jdolecek NAND_SCLK_CFG_REG, /* reg */ 205 1.5.2.2 jdolecek __BITS(17,16), /* n */ 206 1.5.2.2 jdolecek __BITS(3,0), /* m */ 207 1.5.2.2 jdolecek __BITS(25,24), /* sel */ 208 1.5.2.2 jdolecek __BIT(31), /* enable */ 209 1.5.2.2 jdolecek SUNXI_CCU_NM_POWER_OF_TWO), 210 1.5.2.2 jdolecek 211 1.5.2.2 jdolecek /* AHB_GATING_REG0. Missing: SS, EMAC, TS, GPS */ 212 1.5.2.2 jdolecek SUNXI_CCU_GATE(A13_CLK_AHB_OTG, "ahb-otg", "ahb", 213 1.5.2.2 jdolecek AHB_GATING_REG0, 0), 214 1.5.2.2 jdolecek SUNXI_CCU_GATE(A13_CLK_AHB_EHCI, "ahb-ehci", "ahb", 215 1.5.2.2 jdolecek AHB_GATING_REG0, 1), 216 1.5.2.2 jdolecek SUNXI_CCU_GATE(A13_CLK_AHB_OHCI, "ahb-ohci", "ahb", 217 1.5.2.2 jdolecek AHB_GATING_REG0, 2), 218 1.5.2.2 jdolecek SUNXI_CCU_GATE(A13_CLK_AHB_DMA, "ahb-dma", "ahb", 219 1.5.2.2 jdolecek AHB_GATING_REG0, 6), 220 1.5.2.2 jdolecek SUNXI_CCU_GATE(A13_CLK_AHB_BIST, "ahb-bist", "ahb", 221 1.5.2.2 jdolecek AHB_GATING_REG0, 7), 222 1.5.2.2 jdolecek SUNXI_CCU_GATE(A13_CLK_AHB_MMC0, "ahb-mmc0", "ahb", 223 1.5.2.2 jdolecek AHB_GATING_REG0, 8), 224 1.5.2.2 jdolecek SUNXI_CCU_GATE(A13_CLK_AHB_MMC1, "ahb-mmc1", "ahb", 225 1.5.2.2 jdolecek AHB_GATING_REG0, 9), 226 1.5.2.2 jdolecek SUNXI_CCU_GATE(A13_CLK_AHB_MMC2, "ahb-mmc2", "ahb", 227 1.5.2.2 jdolecek AHB_GATING_REG0, 10), 228 1.5.2.2 jdolecek SUNXI_CCU_GATE(A13_CLK_AHB_NAND, "ahb-nand", "ahb", 229 1.5.2.2 jdolecek AHB_GATING_REG0, 13), 230 1.5.2.2 jdolecek SUNXI_CCU_GATE(A13_CLK_AHB_SDRAM, "ahb-sdram", "ahb", 231 1.5.2.2 jdolecek AHB_GATING_REG0, 14), 232 1.5.2.2 jdolecek SUNXI_CCU_GATE(A13_CLK_AHB_SPI0, "ahb-spi0", "ahb", 233 1.5.2.2 jdolecek AHB_GATING_REG0, 20), 234 1.5.2.2 jdolecek SUNXI_CCU_GATE(A13_CLK_AHB_SPI1, "ahb-spi1", "ahb", 235 1.5.2.2 jdolecek AHB_GATING_REG0, 21), 236 1.5.2.2 jdolecek SUNXI_CCU_GATE(A13_CLK_AHB_SPI2, "ahb-spi2", "ahb", 237 1.5.2.2 jdolecek AHB_GATING_REG0, 22), 238 1.5.2.2 jdolecek SUNXI_CCU_GATE(A13_CLK_AHB_HSTIMER, "ahb-hstimer", "ahb", 239 1.5.2.2 jdolecek AHB_GATING_REG0, 28), 240 1.5.2.2 jdolecek 241 1.5.2.2 jdolecek /* AHB_GATING_REG1. Missing: TVE, HDMI */ 242 1.5.2.2 jdolecek SUNXI_CCU_GATE(A13_CLK_AHB_VE, "ahb-ve", "ahb", 243 1.5.2.2 jdolecek AHB_GATING_REG1, 0), 244 1.5.2.2 jdolecek SUNXI_CCU_GATE(A13_CLK_AHB_LCD, "ahb-lcd", "ahb", 245 1.5.2.2 jdolecek AHB_GATING_REG1, 4), 246 1.5.2.2 jdolecek SUNXI_CCU_GATE(A13_CLK_AHB_CSI, "ahb-csi", "ahb", 247 1.5.2.2 jdolecek AHB_GATING_REG1, 8), 248 1.5.2.2 jdolecek SUNXI_CCU_GATE(A13_CLK_AHB_DE_BE, "ahb-de_be", "ahb", 249 1.5.2.2 jdolecek AHB_GATING_REG1, 12), 250 1.5.2.2 jdolecek SUNXI_CCU_GATE(A13_CLK_AHB_DE_FE, "ahb-de_fe", "ahb", 251 1.5.2.2 jdolecek AHB_GATING_REG1, 14), 252 1.5.2.2 jdolecek SUNXI_CCU_GATE(A13_CLK_AHB_IEP, "ahb-iep", "ahb", 253 1.5.2.2 jdolecek AHB_GATING_REG1, 19), 254 1.5.2.2 jdolecek SUNXI_CCU_GATE(A13_CLK_AHB_GPU, "ahb-gpu", "ahb", 255 1.5.2.2 jdolecek AHB_GATING_REG1, 20), 256 1.5.2.2 jdolecek 257 1.5.2.2 jdolecek /* APB0_GATING_REG. Missing: SPDIF, I2S, KEYPAD */ 258 1.5.2.2 jdolecek SUNXI_CCU_GATE(A13_CLK_APB0_CODEC, "apb0-codec", "apb0", 259 1.5.2.2 jdolecek APB0_GATING_REG, 0), 260 1.5.2.2 jdolecek SUNXI_CCU_GATE(A13_CLK_APB0_PIO, "apb0-pio", "apb0", 261 1.5.2.2 jdolecek APB0_GATING_REG, 5), 262 1.5.2.2 jdolecek SUNXI_CCU_GATE(A13_CLK_APB0_IR, "apb0-ir", "apb0", 263 1.5.2.2 jdolecek APB0_GATING_REG, 6), 264 1.5.2.2 jdolecek 265 1.5.2.2 jdolecek /* APB1_GATING_REG. Missing: UART0, UART2 */ 266 1.5.2.2 jdolecek SUNXI_CCU_GATE(A13_CLK_APB1_I2C0, "apb1-i2c0", "apb1", 267 1.5.2.2 jdolecek APB1_GATING_REG, 0), 268 1.5.2.2 jdolecek SUNXI_CCU_GATE(A13_CLK_APB1_I2C1, "apb1-i2c1", "apb1", 269 1.5.2.2 jdolecek APB1_GATING_REG, 1), 270 1.5.2.2 jdolecek SUNXI_CCU_GATE(A13_CLK_APB1_I2C2, "apb1-i2c2", "apb1", 271 1.5.2.2 jdolecek APB1_GATING_REG, 2), 272 1.5.2.2 jdolecek SUNXI_CCU_GATE(A13_CLK_APB1_UART1, "apb1-uart1", "apb1", 273 1.5.2.2 jdolecek APB1_GATING_REG, 17), 274 1.5.2.2 jdolecek SUNXI_CCU_GATE(A13_CLK_APB1_UART3, "apb1-uart3", "apb1", 275 1.5.2.2 jdolecek APB1_GATING_REG, 19), 276 1.5.2.2 jdolecek 277 1.5.2.2 jdolecek /* AUDIO_CODEC_SCLK_CFG_REG */ 278 1.5.2.2 jdolecek SUNXI_CCU_GATE(A13_CLK_CODEC, "codec", "pll_audio", 279 1.5.2.2 jdolecek AUDIO_CODEC_SCLK_CFG_REG, 31), 280 1.5.2.2 jdolecek 281 1.5.2.2 jdolecek /* USBPHY_CFG_REG */ 282 1.5.2.2 jdolecek SUNXI_CCU_GATE(A13_CLK_USB_OHCI, "usb-ohci", "osc24m", 283 1.5.2.2 jdolecek USBPHY_CFG_REG, 6), 284 1.5.2.2 jdolecek SUNXI_CCU_GATE(A13_CLK_USB_PHY0, "usb-phy0", "osc24m", 285 1.5.2.2 jdolecek USBPHY_CFG_REG, 8), 286 1.5.2.2 jdolecek SUNXI_CCU_GATE(A13_CLK_USB_PHY1, "usb-phy1", "osc24m", 287 1.5.2.2 jdolecek USBPHY_CFG_REG, 9), 288 1.5.2.2 jdolecek }; 289 1.5.2.2 jdolecek 290 1.5.2.2 jdolecek static int 291 1.5.2.2 jdolecek sun5i_a13_ccu_match(device_t parent, cfdata_t cf, void *aux) 292 1.5.2.2 jdolecek { 293 1.5.2.2 jdolecek struct fdt_attach_args * const faa = aux; 294 1.5.2.2 jdolecek 295 1.5.2.2 jdolecek return of_match_compatible(faa->faa_phandle, compatible); 296 1.5.2.2 jdolecek } 297 1.5.2.2 jdolecek 298 1.5.2.2 jdolecek static void 299 1.5.2.2 jdolecek sun5i_a13_ccu_attach(device_t parent, device_t self, void *aux) 300 1.5.2.2 jdolecek { 301 1.5.2.2 jdolecek struct sunxi_ccu_softc * const sc = device_private(self); 302 1.5.2.2 jdolecek struct fdt_attach_args * const faa = aux; 303 1.5.2.2 jdolecek 304 1.5.2.2 jdolecek sc->sc_dev = self; 305 1.5.2.2 jdolecek sc->sc_phandle = faa->faa_phandle; 306 1.5.2.2 jdolecek sc->sc_bst = faa->faa_bst; 307 1.5.2.2 jdolecek 308 1.5.2.2 jdolecek sc->sc_resets = sun5i_a13_ccu_resets; 309 1.5.2.2 jdolecek sc->sc_nresets = __arraycount(sun5i_a13_ccu_resets); 310 1.5.2.2 jdolecek 311 1.5.2.2 jdolecek sc->sc_clks = sun5i_a13_ccu_clks; 312 1.5.2.2 jdolecek sc->sc_nclks = __arraycount(sun5i_a13_ccu_clks); 313 1.5.2.2 jdolecek 314 1.5.2.2 jdolecek if (sunxi_ccu_attach(sc) != 0) 315 1.5.2.2 jdolecek return; 316 1.5.2.2 jdolecek 317 1.5.2.2 jdolecek aprint_naive("\n"); 318 1.5.2.2 jdolecek aprint_normal(": A13 CCU\n"); 319 1.5.2.2 jdolecek 320 1.5.2.2 jdolecek sunxi_ccu_print(sc); 321 1.5.2.2 jdolecek } 322
Indexes created Thu Oct 23 22:10:10 GMT 2025