sun5i_a13_ccu.c revision 1.1
1 /* $NetBSD: sun5i_a13_ccu.c,v 1.1 2017/08/25 00:07:03 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(1, "$NetBSD: sun5i_a13_ccu.c,v 1.1 2017/08/25 00:07:03 jmcneill Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/systm.h> 37 38 #include <dev/fdt/fdtvar.h> 39 40 #include <arm/sunxi/sunxi_ccu.h> 41 #include <arm/sunxi/sun5i_a13_ccu.h> 42 43 #define PLL1_CFG_REG 0x000 44 #define PLL6_CFG_REG 0x028 45 #define OSC24M_CFG_REG 0x050 46 #define CPU_AHB_APB0_CFG_REG 0x054 47 #define APB1_CLK_DIV_REG 0x058 48 #define AHB_GATING_REG0 0x060 49 #define AHB_GATING_REG1 0x064 50 #define APB0_GATING_REG 0x068 51 #define APB1_GATING_REG 0x06c 52 #define USBPHY_CFG_REG 0x0cc 53 #define BE_CFG_REG 0x104 54 #define FE_CFG_REG 0x10c 55 #define CSI_CFG_REG 0x134 56 #define VE_CFG_REG 0x13c 57 #define MALI_CLOCK_CFG_REG 0x154 58 #define IEP_SCLK_CFG_REG 0x160 59 60 static int sun5i_a13_ccu_match(device_t, cfdata_t, void *); 61 static void sun5i_a13_ccu_attach(device_t, device_t, void *); 62 63 static const char * const compatible[] = { 64 "allwinner,sun5i-a13-ccu", 65 NULL 66 }; 67 68 CFATTACH_DECL_NEW(sunxi_a13_ccu, sizeof(struct sunxi_ccu_softc), 69 sun5i_a13_ccu_match, sun5i_a13_ccu_attach, NULL, NULL); 70 71 static struct sunxi_ccu_reset sun5i_a13_ccu_resets[] = { 72 SUNXI_CCU_RESET(A13_RST_USB_PHY0, USBPHY_CFG_REG, 0), 73 SUNXI_CCU_RESET(A13_RST_USB_PHY1, USBPHY_CFG_REG, 1), 74 75 /* Missing: GPS */ 76 77 SUNXI_CCU_RESET(A13_RST_DE_BE, BE_CFG_REG, 30), 78 79 SUNXI_CCU_RESET(A13_RST_DE_FE, FE_CFG_REG, 30), 80 81 /* Missing: TVE */ 82 83 /* Missing: LCD */ 84 85 SUNXI_CCU_RESET(A13_RST_CSI, CSI_CFG_REG, 30), 86 87 SUNXI_CCU_RESET(A13_RST_VE, VE_CFG_REG, 0), 88 89 SUNXI_CCU_RESET(A13_RST_GPU, MALI_CLOCK_CFG_REG, 30), 90 91 SUNXI_CCU_RESET(A13_RST_IEP, IEP_SCLK_CFG_REG, 30), 92 }; 93 94 static const char *cpu_parents[] = { "losc", "osc24m", "pll_core", "pll_periph" }; 95 static const char *axi_parents[] = { "cpu" }; 96 static const char *ahb_parents[] = { "axi", "cpu", "pll_periph", NULL }; 97 static const char *apb0_parents[] = { "ahb" }; 98 static const char *apb1_parents[] = { "osc24m", "pll_periph", "losc", NULL }; 99 100 static struct sunxi_ccu_clk sun5i_a13_ccu_clks[] = { 101 SUNXI_CCU_GATE(A13_CLK_HOSC, "osc24m", "hosc", 102 OSC24M_CFG_REG, 0), 103 104 SUNXI_CCU_NKMP(A13_CLK_PLL_CORE, "pll_core", "osc24m", 105 PLL1_CFG_REG, /* reg */ 106 __BITS(12,8), /* n */ 107 __BITS(5,4), /* k */ 108 __BITS(1,0), /* m */ 109 __BITS(17,16), /* p */ 110 __BIT(31), /* enable */ 111 SUNXI_CCU_NKMP_FACTOR_P_POW2 | SUNXI_CCU_NKMP_FACTOR_N_EXACT), 112 113 SUNXI_CCU_NKMP(A13_CLK_PERIPH, "pll_periph", "osc24m", 114 PLL6_CFG_REG, /* reg */ 115 __BITS(12,8), /* n */ 116 __BITS(5,4), /* k */ 117 __BITS(1,0), /* m */ 118 0, /* p */ 119 __BIT(31), /* enable */ 120 SUNXI_CCU_NKMP_DIVIDE_BY_TWO | SUNXI_CCU_NKMP_FACTOR_N_EXACT), 121 122 SUNXI_CCU_PREDIV_FIXED(A13_CLK_CPU, "cpu", cpu_parents, 123 CPU_AHB_APB0_CFG_REG, /* reg */ 124 0, /* prediv */ 125 __BIT(3), /* prediv_sel */ 126 6, /* prediv_fixed */ 127 0, /* div */ 128 __BITS(17,16), /* sel */ 129 0), 130 131 SUNXI_CCU_DIV(A13_CLK_AXI, "axi", axi_parents, 132 CPU_AHB_APB0_CFG_REG, /* reg */ 133 __BITS(1,0), /* div */ 134 0, /* sel */ 135 0), 136 137 SUNXI_CCU_DIV(A13_CLK_AHB, "ahb", ahb_parents, 138 CPU_AHB_APB0_CFG_REG, /* reg */ 139 0, /* div */ 140 __BITS(5,4), /* sel */ 141 SUNXI_CCU_DIV_POWER_OF_TWO), 142 143 SUNXI_CCU_DIV(A13_CLK_APB0, "apb0", apb0_parents, 144 CPU_AHB_APB0_CFG_REG, /* reg */ 145 __BITS(9,8), /* div */ 146 0, /* sel */ 147 SUNXI_CCU_DIV_ZERO_IS_ONE | SUNXI_CCU_DIV_POWER_OF_TWO), 148 149 SUNXI_CCU_NM(A13_CLK_APB1, "apb1", apb1_parents, 150 APB1_CLK_DIV_REG, /* reg */ 151 __BITS(17,16), /* n */ 152 __BITS(4,0), /* m */ 153 __BITS(25,24), /* sel */ 154 0, /* enable */ 155 SUNXI_CCU_NM_POWER_OF_TWO), 156 157 /* AHB_GATING_REG0. Missing: SS, EMAC, TS, GPS */ 158 SUNXI_CCU_GATE(A13_CLK_AHB_OTG, "ahb-otg", "ahb", 159 AHB_GATING_REG0, 0), 160 SUNXI_CCU_GATE(A13_CLK_AHB_EHCI, "ahb-ehci", "ahb", 161 AHB_GATING_REG0, 1), 162 SUNXI_CCU_GATE(A13_CLK_AHB_OHCI, "ahb-ohci", "ahb", 163 AHB_GATING_REG0, 2), 164 SUNXI_CCU_GATE(A13_CLK_AHB_DMA, "ahb-dma", "ahb", 165 AHB_GATING_REG0, 6), 166 SUNXI_CCU_GATE(A13_CLK_AHB_BIST, "ahb-bist", "ahb", 167 AHB_GATING_REG0, 7), 168 SUNXI_CCU_GATE(A13_CLK_AHB_MMC0, "ahb-mmc0", "ahb", 169 AHB_GATING_REG0, 8), 170 SUNXI_CCU_GATE(A13_CLK_AHB_MMC1, "ahb-mmc1", "ahb", 171 AHB_GATING_REG0, 9), 172 SUNXI_CCU_GATE(A13_CLK_AHB_MMC2, "ahb-mmc2", "ahb", 173 AHB_GATING_REG0, 10), 174 SUNXI_CCU_GATE(A13_CLK_AHB_NAND, "ahb-nand", "ahb", 175 AHB_GATING_REG0, 13), 176 SUNXI_CCU_GATE(A13_CLK_AHB_SDRAM, "ahb-sdram", "ahb", 177 AHB_GATING_REG0, 14), 178 SUNXI_CCU_GATE(A13_CLK_AHB_SPI0, "ahb-spi0", "ahb", 179 AHB_GATING_REG0, 20), 180 SUNXI_CCU_GATE(A13_CLK_AHB_SPI1, "ahb-spi1", "ahb", 181 AHB_GATING_REG0, 21), 182 SUNXI_CCU_GATE(A13_CLK_AHB_SPI2, "ahb-spi2", "ahb", 183 AHB_GATING_REG0, 22), 184 SUNXI_CCU_GATE(A13_CLK_AHB_HSTIMER, "ahb-hstimer", "ahb", 185 AHB_GATING_REG0, 28), 186 187 /* AHB_GATING_REG1. Missing: TVE, HDMI */ 188 SUNXI_CCU_GATE(A13_CLK_AHB_VE, "ahb-ve", "ahb", 189 AHB_GATING_REG1, 0), 190 SUNXI_CCU_GATE(A13_CLK_AHB_LCD, "ahb-lcd", "ahb", 191 AHB_GATING_REG1, 4), 192 SUNXI_CCU_GATE(A13_CLK_AHB_CSI, "ahb-csi", "ahb", 193 AHB_GATING_REG1, 8), 194 SUNXI_CCU_GATE(A13_CLK_AHB_DE_BE, "ahb-de_be", "ahb", 195 AHB_GATING_REG1, 12), 196 SUNXI_CCU_GATE(A13_CLK_AHB_DE_FE, "ahb-de_fe", "ahb", 197 AHB_GATING_REG1, 14), 198 SUNXI_CCU_GATE(A13_CLK_AHB_IEP, "ahb-iep", "ahb", 199 AHB_GATING_REG1, 19), 200 SUNXI_CCU_GATE(A13_CLK_AHB_GPU, "ahb-gpu", "ahb", 201 AHB_GATING_REG1, 20), 202 203 /* APB0_GATING_REG. Missing: SPDIF, I2S, KEYPAD */ 204 SUNXI_CCU_GATE(A13_CLK_APB0_CODEC, "apb0-codec", "apb0", 205 APB0_GATING_REG, 0), 206 SUNXI_CCU_GATE(A13_CLK_APB0_PIO, "apb0-pio", "apb0", 207 APB0_GATING_REG, 5), 208 SUNXI_CCU_GATE(A13_CLK_APB0_IR, "apb0-ir", "apb0", 209 APB0_GATING_REG, 6), 210 211 /* APB1_GATING_REG. Missing: UART0, UART2 */ 212 SUNXI_CCU_GATE(A13_CLK_APB1_I2C0, "apb1-i2c0", "apb1", 213 APB1_GATING_REG, 0), 214 SUNXI_CCU_GATE(A13_CLK_APB1_I2C1, "apb1-i2c1", "apb1", 215 APB1_GATING_REG, 1), 216 SUNXI_CCU_GATE(A13_CLK_APB1_I2C2, "apb1-i2c2", "apb1", 217 APB1_GATING_REG, 2), 218 SUNXI_CCU_GATE(A13_CLK_APB1_UART1, "apb1-uart1", "apb1", 219 APB1_GATING_REG, 17), 220 SUNXI_CCU_GATE(A13_CLK_APB1_UART3, "apb1-uart3", "apb1", 221 APB1_GATING_REG, 19), 222 223 /* USBPHY_CFG_REG */ 224 SUNXI_CCU_GATE(A13_CLK_USB_OHCI, "usb-ohci", "osc24m", 225 USBPHY_CFG_REG, 6), 226 SUNXI_CCU_GATE(A13_CLK_USB_PHY0, "usb-phy0", "osc24m", 227 USBPHY_CFG_REG, 8), 228 SUNXI_CCU_GATE(A13_CLK_USB_PHY1, "usb-phy1", "osc24m", 229 USBPHY_CFG_REG, 9), 230 }; 231 232 static int 233 sun5i_a13_ccu_match(device_t parent, cfdata_t cf, void *aux) 234 { 235 struct fdt_attach_args * const faa = aux; 236 237 return of_match_compatible(faa->faa_phandle, compatible); 238 } 239 240 static void 241 sun5i_a13_ccu_attach(device_t parent, device_t self, void *aux) 242 { 243 struct sunxi_ccu_softc * const sc = device_private(self); 244 struct fdt_attach_args * const faa = aux; 245 246 sc->sc_dev = self; 247 sc->sc_phandle = faa->faa_phandle; 248 sc->sc_bst = faa->faa_bst; 249 250 sc->sc_resets = sun5i_a13_ccu_resets; 251 sc->sc_nresets = __arraycount(sun5i_a13_ccu_resets); 252 253 sc->sc_clks = sun5i_a13_ccu_clks; 254 sc->sc_nclks = __arraycount(sun5i_a13_ccu_clks); 255 256 if (sunxi_ccu_attach(sc) != 0) 257 return; 258 259 aprint_naive("\n"); 260 aprint_normal(": A13 CCU\n"); 261 262 sunxi_ccu_print(sc); 263 } 264
Indexes created Thu Oct 02 14:10:14 GMT 2025