sun5i_a13_ccu.c revision 1.2
1 /* $NetBSD: sun5i_a13_ccu.c,v 1.2 2017/08/27 16:05:08 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(1, "$NetBSD: sun5i_a13_ccu.c,v 1.2 2017/08/27 16:05:08 jmcneill Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/systm.h> 37 38 #include <dev/fdt/fdtvar.h> 39 40 #include <arm/sunxi/sunxi_ccu.h> 41 #include <arm/sunxi/sun5i_a13_ccu.h> 42 43 #define PLL1_CFG_REG 0x000 44 #define PLL2_CFG_REG 0x008 45 #define PLL6_CFG_REG 0x028 46 #define OSC24M_CFG_REG 0x050 47 #define CPU_AHB_APB0_CFG_REG 0x054 48 #define APB1_CLK_DIV_REG 0x058 49 #define AHB_GATING_REG0 0x060 50 #define AHB_GATING_REG1 0x064 51 #define APB0_GATING_REG 0x068 52 #define APB1_GATING_REG 0x06c 53 #define USBPHY_CFG_REG 0x0cc 54 #define BE_CFG_REG 0x104 55 #define FE_CFG_REG 0x10c 56 #define CSI_CFG_REG 0x134 57 #define VE_CFG_REG 0x13c 58 #define AUDIO_CODEC_SCLK_CFG_REG 0x140 59 #define MALI_CLOCK_CFG_REG 0x154 60 #define IEP_SCLK_CFG_REG 0x160 61 62 static int sun5i_a13_ccu_match(device_t, cfdata_t, void *); 63 static void sun5i_a13_ccu_attach(device_t, device_t, void *); 64 65 static const char * const compatible[] = { 66 "allwinner,sun5i-a13-ccu", 67 NULL 68 }; 69 70 CFATTACH_DECL_NEW(sunxi_a13_ccu, sizeof(struct sunxi_ccu_softc), 71 sun5i_a13_ccu_match, sun5i_a13_ccu_attach, NULL, NULL); 72 73 static struct sunxi_ccu_reset sun5i_a13_ccu_resets[] = { 74 SUNXI_CCU_RESET(A13_RST_USB_PHY0, USBPHY_CFG_REG, 0), 75 SUNXI_CCU_RESET(A13_RST_USB_PHY1, USBPHY_CFG_REG, 1), 76 77 /* Missing: GPS */ 78 79 SUNXI_CCU_RESET(A13_RST_DE_BE, BE_CFG_REG, 30), 80 81 SUNXI_CCU_RESET(A13_RST_DE_FE, FE_CFG_REG, 30), 82 83 /* Missing: TVE */ 84 85 /* Missing: LCD */ 86 87 SUNXI_CCU_RESET(A13_RST_CSI, CSI_CFG_REG, 30), 88 89 SUNXI_CCU_RESET(A13_RST_VE, VE_CFG_REG, 0), 90 91 SUNXI_CCU_RESET(A13_RST_GPU, MALI_CLOCK_CFG_REG, 30), 92 93 SUNXI_CCU_RESET(A13_RST_IEP, IEP_SCLK_CFG_REG, 30), 94 }; 95 96 static const char *cpu_parents[] = { "losc", "osc24m", "pll_core", "pll_periph" }; 97 static const char *axi_parents[] = { "cpu" }; 98 static const char *ahb_parents[] = { "axi", "cpu", "pll_periph", NULL }; 99 static const char *apb0_parents[] = { "ahb" }; 100 static const char *apb1_parents[] = { "osc24m", "pll_periph", "losc", NULL }; 101 102 static const struct sunxi_ccu_nkmp_tbl sun5i_a13_ac_dig_table[] = { 103 { 24576000, 86, 0, 21, 3 }, 104 { 0 } 105 }; 106 107 static struct sunxi_ccu_clk sun5i_a13_ccu_clks[] = { 108 SUNXI_CCU_GATE(A13_CLK_HOSC, "osc24m", "hosc", 109 OSC24M_CFG_REG, 0), 110 111 SUNXI_CCU_NKMP(A13_CLK_PLL_CORE, "pll_core", "osc24m", 112 PLL1_CFG_REG, /* reg */ 113 __BITS(12,8), /* n */ 114 __BITS(5,4), /* k */ 115 __BITS(1,0), /* m */ 116 __BITS(17,16), /* p */ 117 __BIT(31), /* enable */ 118 SUNXI_CCU_NKMP_FACTOR_P_POW2 | SUNXI_CCU_NKMP_FACTOR_N_EXACT), 119 120 SUNXI_CCU_NKMP_TABLE(A13_CLK_PLL_AUDIO_BASE, "pll_audio", "osc24m", 121 PLL2_CFG_REG, /* reg */ 122 __BITS(14,8), /* n */ 123 0, /* k */ 124 __BITS(4,0), /* m */ 125 __BITS(29,26), /* p */ 126 __BIT(31), /* enable */ 127 0, /* lock */ 128 sun5i_a13_ac_dig_table, /* table */ 129 0), 130 131 SUNXI_CCU_NKMP(A13_CLK_PERIPH, "pll_periph", "osc24m", 132 PLL6_CFG_REG, /* reg */ 133 __BITS(12,8), /* n */ 134 __BITS(5,4), /* k */ 135 __BITS(1,0), /* m */ 136 0, /* p */ 137 __BIT(31), /* enable */ 138 SUNXI_CCU_NKMP_DIVIDE_BY_TWO | SUNXI_CCU_NKMP_FACTOR_N_EXACT), 139 140 SUNXI_CCU_PREDIV_FIXED(A13_CLK_CPU, "cpu", cpu_parents, 141 CPU_AHB_APB0_CFG_REG, /* reg */ 142 0, /* prediv */ 143 __BIT(3), /* prediv_sel */ 144 6, /* prediv_fixed */ 145 0, /* div */ 146 __BITS(17,16), /* sel */ 147 0), 148 149 SUNXI_CCU_DIV(A13_CLK_AXI, "axi", axi_parents, 150 CPU_AHB_APB0_CFG_REG, /* reg */ 151 __BITS(1,0), /* div */ 152 0, /* sel */ 153 0), 154 155 SUNXI_CCU_DIV(A13_CLK_AHB, "ahb", ahb_parents, 156 CPU_AHB_APB0_CFG_REG, /* reg */ 157 0, /* div */ 158 __BITS(5,4), /* sel */ 159 SUNXI_CCU_DIV_POWER_OF_TWO), 160 161 SUNXI_CCU_DIV(A13_CLK_APB0, "apb0", apb0_parents, 162 CPU_AHB_APB0_CFG_REG, /* reg */ 163 __BITS(9,8), /* div */ 164 0, /* sel */ 165 SUNXI_CCU_DIV_ZERO_IS_ONE | SUNXI_CCU_DIV_POWER_OF_TWO), 166 167 SUNXI_CCU_NM(A13_CLK_APB1, "apb1", apb1_parents, 168 APB1_CLK_DIV_REG, /* reg */ 169 __BITS(17,16), /* n */ 170 __BITS(4,0), /* m */ 171 __BITS(25,24), /* sel */ 172 0, /* enable */ 173 SUNXI_CCU_NM_POWER_OF_TWO), 174 175 /* AHB_GATING_REG0. Missing: SS, EMAC, TS, GPS */ 176 SUNXI_CCU_GATE(A13_CLK_AHB_OTG, "ahb-otg", "ahb", 177 AHB_GATING_REG0, 0), 178 SUNXI_CCU_GATE(A13_CLK_AHB_EHCI, "ahb-ehci", "ahb", 179 AHB_GATING_REG0, 1), 180 SUNXI_CCU_GATE(A13_CLK_AHB_OHCI, "ahb-ohci", "ahb", 181 AHB_GATING_REG0, 2), 182 SUNXI_CCU_GATE(A13_CLK_AHB_DMA, "ahb-dma", "ahb", 183 AHB_GATING_REG0, 6), 184 SUNXI_CCU_GATE(A13_CLK_AHB_BIST, "ahb-bist", "ahb", 185 AHB_GATING_REG0, 7), 186 SUNXI_CCU_GATE(A13_CLK_AHB_MMC0, "ahb-mmc0", "ahb", 187 AHB_GATING_REG0, 8), 188 SUNXI_CCU_GATE(A13_CLK_AHB_MMC1, "ahb-mmc1", "ahb", 189 AHB_GATING_REG0, 9), 190 SUNXI_CCU_GATE(A13_CLK_AHB_MMC2, "ahb-mmc2", "ahb", 191 AHB_GATING_REG0, 10), 192 SUNXI_CCU_GATE(A13_CLK_AHB_NAND, "ahb-nand", "ahb", 193 AHB_GATING_REG0, 13), 194 SUNXI_CCU_GATE(A13_CLK_AHB_SDRAM, "ahb-sdram", "ahb", 195 AHB_GATING_REG0, 14), 196 SUNXI_CCU_GATE(A13_CLK_AHB_SPI0, "ahb-spi0", "ahb", 197 AHB_GATING_REG0, 20), 198 SUNXI_CCU_GATE(A13_CLK_AHB_SPI1, "ahb-spi1", "ahb", 199 AHB_GATING_REG0, 21), 200 SUNXI_CCU_GATE(A13_CLK_AHB_SPI2, "ahb-spi2", "ahb", 201 AHB_GATING_REG0, 22), 202 SUNXI_CCU_GATE(A13_CLK_AHB_HSTIMER, "ahb-hstimer", "ahb", 203 AHB_GATING_REG0, 28), 204 205 /* AHB_GATING_REG1. Missing: TVE, HDMI */ 206 SUNXI_CCU_GATE(A13_CLK_AHB_VE, "ahb-ve", "ahb", 207 AHB_GATING_REG1, 0), 208 SUNXI_CCU_GATE(A13_CLK_AHB_LCD, "ahb-lcd", "ahb", 209 AHB_GATING_REG1, 4), 210 SUNXI_CCU_GATE(A13_CLK_AHB_CSI, "ahb-csi", "ahb", 211 AHB_GATING_REG1, 8), 212 SUNXI_CCU_GATE(A13_CLK_AHB_DE_BE, "ahb-de_be", "ahb", 213 AHB_GATING_REG1, 12), 214 SUNXI_CCU_GATE(A13_CLK_AHB_DE_FE, "ahb-de_fe", "ahb", 215 AHB_GATING_REG1, 14), 216 SUNXI_CCU_GATE(A13_CLK_AHB_IEP, "ahb-iep", "ahb", 217 AHB_GATING_REG1, 19), 218 SUNXI_CCU_GATE(A13_CLK_AHB_GPU, "ahb-gpu", "ahb", 219 AHB_GATING_REG1, 20), 220 221 /* APB0_GATING_REG. Missing: SPDIF, I2S, KEYPAD */ 222 SUNXI_CCU_GATE(A13_CLK_APB0_CODEC, "apb0-codec", "apb0", 223 APB0_GATING_REG, 0), 224 SUNXI_CCU_GATE(A13_CLK_APB0_PIO, "apb0-pio", "apb0", 225 APB0_GATING_REG, 5), 226 SUNXI_CCU_GATE(A13_CLK_APB0_IR, "apb0-ir", "apb0", 227 APB0_GATING_REG, 6), 228 229 /* APB1_GATING_REG. Missing: UART0, UART2 */ 230 SUNXI_CCU_GATE(A13_CLK_APB1_I2C0, "apb1-i2c0", "apb1", 231 APB1_GATING_REG, 0), 232 SUNXI_CCU_GATE(A13_CLK_APB1_I2C1, "apb1-i2c1", "apb1", 233 APB1_GATING_REG, 1), 234 SUNXI_CCU_GATE(A13_CLK_APB1_I2C2, "apb1-i2c2", "apb1", 235 APB1_GATING_REG, 2), 236 SUNXI_CCU_GATE(A13_CLK_APB1_UART1, "apb1-uart1", "apb1", 237 APB1_GATING_REG, 17), 238 SUNXI_CCU_GATE(A13_CLK_APB1_UART3, "apb1-uart3", "apb1", 239 APB1_GATING_REG, 19), 240 241 /* AUDIO_CODEC_SCLK_CFG_REG */ 242 SUNXI_CCU_GATE(A13_CLK_CODEC, "codec", "pll_audio", 243 AUDIO_CODEC_SCLK_CFG_REG, 31), 244 245 /* USBPHY_CFG_REG */ 246 SUNXI_CCU_GATE(A13_CLK_USB_OHCI, "usb-ohci", "osc24m", 247 USBPHY_CFG_REG, 6), 248 SUNXI_CCU_GATE(A13_CLK_USB_PHY0, "usb-phy0", "osc24m", 249 USBPHY_CFG_REG, 8), 250 SUNXI_CCU_GATE(A13_CLK_USB_PHY1, "usb-phy1", "osc24m", 251 USBPHY_CFG_REG, 9), 252 }; 253 254 static int 255 sun5i_a13_ccu_match(device_t parent, cfdata_t cf, void *aux) 256 { 257 struct fdt_attach_args * const faa = aux; 258 259 return of_match_compatible(faa->faa_phandle, compatible); 260 } 261 262 static void 263 sun5i_a13_ccu_attach(device_t parent, device_t self, void *aux) 264 { 265 struct sunxi_ccu_softc * const sc = device_private(self); 266 struct fdt_attach_args * const faa = aux; 267 268 sc->sc_dev = self; 269 sc->sc_phandle = faa->faa_phandle; 270 sc->sc_bst = faa->faa_bst; 271 272 sc->sc_resets = sun5i_a13_ccu_resets; 273 sc->sc_nresets = __arraycount(sun5i_a13_ccu_resets); 274 275 sc->sc_clks = sun5i_a13_ccu_clks; 276 sc->sc_nclks = __arraycount(sun5i_a13_ccu_clks); 277 278 if (sunxi_ccu_attach(sc) != 0) 279 return; 280 281 aprint_naive("\n"); 282 aprint_normal(": A13 CCU\n"); 283 284 sunxi_ccu_print(sc); 285 } 286
Indexes created Thu Oct 02 14:10:14 GMT 2025