sun5i_a13_ccu.c revision 1.3
1 /* $NetBSD: sun5i_a13_ccu.c,v 1.3 2017/08/27 17:53:31 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(1, "$NetBSD: sun5i_a13_ccu.c,v 1.3 2017/08/27 17:53:31 jmcneill Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/systm.h> 37 38 #include <dev/fdt/fdtvar.h> 39 40 #include <arm/sunxi/sunxi_ccu.h> 41 #include <arm/sunxi/sun5i_a13_ccu.h> 42 43 #define PLL1_CFG_REG 0x000 44 #define PLL2_CFG_REG 0x008 45 #define PLL6_CFG_REG 0x028 46 #define OSC24M_CFG_REG 0x050 47 #define CPU_AHB_APB0_CFG_REG 0x054 48 #define APB1_CLK_DIV_REG 0x058 49 #define AHB_GATING_REG0 0x060 50 #define AHB_GATING_REG1 0x064 51 #define APB0_GATING_REG 0x068 52 #define APB1_GATING_REG 0x06c 53 #define SD0_SCLK_CFG_REG 0x088 54 #define SD1_SCLK_CFG_REG 0x08c 55 #define SD2_SCLK_CFG_REG 0x090 56 #define USBPHY_CFG_REG 0x0cc 57 #define BE_CFG_REG 0x104 58 #define FE_CFG_REG 0x10c 59 #define CSI_CFG_REG 0x134 60 #define VE_CFG_REG 0x13c 61 #define AUDIO_CODEC_SCLK_CFG_REG 0x140 62 #define MALI_CLOCK_CFG_REG 0x154 63 #define IEP_SCLK_CFG_REG 0x160 64 65 static int sun5i_a13_ccu_match(device_t, cfdata_t, void *); 66 static void sun5i_a13_ccu_attach(device_t, device_t, void *); 67 68 static const char * const compatible[] = { 69 "allwinner,sun5i-a13-ccu", 70 NULL 71 }; 72 73 CFATTACH_DECL_NEW(sunxi_a13_ccu, sizeof(struct sunxi_ccu_softc), 74 sun5i_a13_ccu_match, sun5i_a13_ccu_attach, NULL, NULL); 75 76 static struct sunxi_ccu_reset sun5i_a13_ccu_resets[] = { 77 SUNXI_CCU_RESET(A13_RST_USB_PHY0, USBPHY_CFG_REG, 0), 78 SUNXI_CCU_RESET(A13_RST_USB_PHY1, USBPHY_CFG_REG, 1), 79 80 /* Missing: GPS */ 81 82 SUNXI_CCU_RESET(A13_RST_DE_BE, BE_CFG_REG, 30), 83 84 SUNXI_CCU_RESET(A13_RST_DE_FE, FE_CFG_REG, 30), 85 86 /* Missing: TVE */ 87 88 /* Missing: LCD */ 89 90 SUNXI_CCU_RESET(A13_RST_CSI, CSI_CFG_REG, 30), 91 92 SUNXI_CCU_RESET(A13_RST_VE, VE_CFG_REG, 0), 93 94 SUNXI_CCU_RESET(A13_RST_GPU, MALI_CLOCK_CFG_REG, 30), 95 96 SUNXI_CCU_RESET(A13_RST_IEP, IEP_SCLK_CFG_REG, 30), 97 }; 98 99 static const char *cpu_parents[] = { "losc", "osc24m", "pll_core", "pll_periph" }; 100 static const char *axi_parents[] = { "cpu" }; 101 static const char *ahb_parents[] = { "axi", "cpu", "pll_periph" }; 102 static const char *apb0_parents[] = { "ahb" }; 103 static const char *apb1_parents[] = { "osc24m", "pll_periph", "losc" }; 104 static const char *mod_parents[] = { "osc24m", "pll_periph", "pll_ddr" }; 105 106 static const struct sunxi_ccu_nkmp_tbl sun5i_a13_ac_dig_table[] = { 107 { 24576000, 86, 0, 21, 3 }, 108 { 0 } 109 }; 110 111 static struct sunxi_ccu_clk sun5i_a13_ccu_clks[] = { 112 SUNXI_CCU_GATE(A13_CLK_HOSC, "osc24m", "hosc", 113 OSC24M_CFG_REG, 0), 114 115 SUNXI_CCU_NKMP(A13_CLK_PLL_CORE, "pll_core", "osc24m", 116 PLL1_CFG_REG, /* reg */ 117 __BITS(12,8), /* n */ 118 __BITS(5,4), /* k */ 119 __BITS(1,0), /* m */ 120 __BITS(17,16), /* p */ 121 __BIT(31), /* enable */ 122 SUNXI_CCU_NKMP_FACTOR_P_POW2 | SUNXI_CCU_NKMP_FACTOR_N_EXACT), 123 124 SUNXI_CCU_NKMP_TABLE(A13_CLK_PLL_AUDIO_BASE, "pll_audio", "osc24m", 125 PLL2_CFG_REG, /* reg */ 126 __BITS(14,8), /* n */ 127 0, /* k */ 128 __BITS(4,0), /* m */ 129 __BITS(29,26), /* p */ 130 __BIT(31), /* enable */ 131 0, /* lock */ 132 sun5i_a13_ac_dig_table, /* table */ 133 0), 134 135 SUNXI_CCU_NKMP(A13_CLK_PERIPH, "pll_periph", "osc24m", 136 PLL6_CFG_REG, /* reg */ 137 __BITS(12,8), /* n */ 138 __BITS(5,4), /* k */ 139 __BITS(1,0), /* m */ 140 0, /* p */ 141 __BIT(31), /* enable */ 142 SUNXI_CCU_NKMP_DIVIDE_BY_TWO | SUNXI_CCU_NKMP_FACTOR_N_EXACT), 143 144 SUNXI_CCU_PREDIV_FIXED(A13_CLK_CPU, "cpu", cpu_parents, 145 CPU_AHB_APB0_CFG_REG, /* reg */ 146 0, /* prediv */ 147 __BIT(3), /* prediv_sel */ 148 6, /* prediv_fixed */ 149 0, /* div */ 150 __BITS(17,16), /* sel */ 151 0), 152 153 SUNXI_CCU_DIV(A13_CLK_AXI, "axi", axi_parents, 154 CPU_AHB_APB0_CFG_REG, /* reg */ 155 __BITS(1,0), /* div */ 156 0, /* sel */ 157 0), 158 159 SUNXI_CCU_DIV(A13_CLK_AHB, "ahb", ahb_parents, 160 CPU_AHB_APB0_CFG_REG, /* reg */ 161 0, /* div */ 162 __BITS(5,4), /* sel */ 163 SUNXI_CCU_DIV_POWER_OF_TWO), 164 165 SUNXI_CCU_DIV(A13_CLK_APB0, "apb0", apb0_parents, 166 CPU_AHB_APB0_CFG_REG, /* reg */ 167 __BITS(9,8), /* div */ 168 0, /* sel */ 169 SUNXI_CCU_DIV_ZERO_IS_ONE | SUNXI_CCU_DIV_POWER_OF_TWO), 170 171 SUNXI_CCU_NM(A13_CLK_APB1, "apb1", apb1_parents, 172 APB1_CLK_DIV_REG, /* reg */ 173 __BITS(17,16), /* n */ 174 __BITS(4,0), /* m */ 175 __BITS(25,24), /* sel */ 176 0, /* enable */ 177 SUNXI_CCU_NM_POWER_OF_TWO), 178 179 SUNXI_CCU_NM(A13_CLK_MMC0, "mmc0", mod_parents, 180 SD0_SCLK_CFG_REG, /* reg */ 181 __BITS(17,16), /* n */ 182 __BITS(3,0), /* m */ 183 __BITS(25,24), /* sel */ 184 __BIT(31), /* enable */ 185 SUNXI_CCU_NM_POWER_OF_TWO), 186 SUNXI_CCU_NM(A13_CLK_MMC1, "mmc1", mod_parents, 187 SD1_SCLK_CFG_REG, /* reg */ 188 __BITS(17,16), /* n */ 189 __BITS(3,0), /* m */ 190 __BITS(25,24), /* sel */ 191 __BIT(31), /* enable */ 192 SUNXI_CCU_NM_POWER_OF_TWO), 193 SUNXI_CCU_NM(A13_CLK_MMC2, "mmc2", mod_parents, 194 SD2_SCLK_CFG_REG, /* reg */ 195 __BITS(17,16), /* n */ 196 __BITS(3,0), /* m */ 197 __BITS(25,24), /* sel */ 198 __BIT(31), /* enable */ 199 SUNXI_CCU_NM_POWER_OF_TWO), 200 201 /* AHB_GATING_REG0. Missing: SS, EMAC, TS, GPS */ 202 SUNXI_CCU_GATE(A13_CLK_AHB_OTG, "ahb-otg", "ahb", 203 AHB_GATING_REG0, 0), 204 SUNXI_CCU_GATE(A13_CLK_AHB_EHCI, "ahb-ehci", "ahb", 205 AHB_GATING_REG0, 1), 206 SUNXI_CCU_GATE(A13_CLK_AHB_OHCI, "ahb-ohci", "ahb", 207 AHB_GATING_REG0, 2), 208 SUNXI_CCU_GATE(A13_CLK_AHB_DMA, "ahb-dma", "ahb", 209 AHB_GATING_REG0, 6), 210 SUNXI_CCU_GATE(A13_CLK_AHB_BIST, "ahb-bist", "ahb", 211 AHB_GATING_REG0, 7), 212 SUNXI_CCU_GATE(A13_CLK_AHB_MMC0, "ahb-mmc0", "ahb", 213 AHB_GATING_REG0, 8), 214 SUNXI_CCU_GATE(A13_CLK_AHB_MMC1, "ahb-mmc1", "ahb", 215 AHB_GATING_REG0, 9), 216 SUNXI_CCU_GATE(A13_CLK_AHB_MMC2, "ahb-mmc2", "ahb", 217 AHB_GATING_REG0, 10), 218 SUNXI_CCU_GATE(A13_CLK_AHB_NAND, "ahb-nand", "ahb", 219 AHB_GATING_REG0, 13), 220 SUNXI_CCU_GATE(A13_CLK_AHB_SDRAM, "ahb-sdram", "ahb", 221 AHB_GATING_REG0, 14), 222 SUNXI_CCU_GATE(A13_CLK_AHB_SPI0, "ahb-spi0", "ahb", 223 AHB_GATING_REG0, 20), 224 SUNXI_CCU_GATE(A13_CLK_AHB_SPI1, "ahb-spi1", "ahb", 225 AHB_GATING_REG0, 21), 226 SUNXI_CCU_GATE(A13_CLK_AHB_SPI2, "ahb-spi2", "ahb", 227 AHB_GATING_REG0, 22), 228 SUNXI_CCU_GATE(A13_CLK_AHB_HSTIMER, "ahb-hstimer", "ahb", 229 AHB_GATING_REG0, 28), 230 231 /* AHB_GATING_REG1. Missing: TVE, HDMI */ 232 SUNXI_CCU_GATE(A13_CLK_AHB_VE, "ahb-ve", "ahb", 233 AHB_GATING_REG1, 0), 234 SUNXI_CCU_GATE(A13_CLK_AHB_LCD, "ahb-lcd", "ahb", 235 AHB_GATING_REG1, 4), 236 SUNXI_CCU_GATE(A13_CLK_AHB_CSI, "ahb-csi", "ahb", 237 AHB_GATING_REG1, 8), 238 SUNXI_CCU_GATE(A13_CLK_AHB_DE_BE, "ahb-de_be", "ahb", 239 AHB_GATING_REG1, 12), 240 SUNXI_CCU_GATE(A13_CLK_AHB_DE_FE, "ahb-de_fe", "ahb", 241 AHB_GATING_REG1, 14), 242 SUNXI_CCU_GATE(A13_CLK_AHB_IEP, "ahb-iep", "ahb", 243 AHB_GATING_REG1, 19), 244 SUNXI_CCU_GATE(A13_CLK_AHB_GPU, "ahb-gpu", "ahb", 245 AHB_GATING_REG1, 20), 246 247 /* APB0_GATING_REG. Missing: SPDIF, I2S, KEYPAD */ 248 SUNXI_CCU_GATE(A13_CLK_APB0_CODEC, "apb0-codec", "apb0", 249 APB0_GATING_REG, 0), 250 SUNXI_CCU_GATE(A13_CLK_APB0_PIO, "apb0-pio", "apb0", 251 APB0_GATING_REG, 5), 252 SUNXI_CCU_GATE(A13_CLK_APB0_IR, "apb0-ir", "apb0", 253 APB0_GATING_REG, 6), 254 255 /* APB1_GATING_REG. Missing: UART0, UART2 */ 256 SUNXI_CCU_GATE(A13_CLK_APB1_I2C0, "apb1-i2c0", "apb1", 257 APB1_GATING_REG, 0), 258 SUNXI_CCU_GATE(A13_CLK_APB1_I2C1, "apb1-i2c1", "apb1", 259 APB1_GATING_REG, 1), 260 SUNXI_CCU_GATE(A13_CLK_APB1_I2C2, "apb1-i2c2", "apb1", 261 APB1_GATING_REG, 2), 262 SUNXI_CCU_GATE(A13_CLK_APB1_UART1, "apb1-uart1", "apb1", 263 APB1_GATING_REG, 17), 264 SUNXI_CCU_GATE(A13_CLK_APB1_UART3, "apb1-uart3", "apb1", 265 APB1_GATING_REG, 19), 266 267 /* AUDIO_CODEC_SCLK_CFG_REG */ 268 SUNXI_CCU_GATE(A13_CLK_CODEC, "codec", "pll_audio", 269 AUDIO_CODEC_SCLK_CFG_REG, 31), 270 271 /* USBPHY_CFG_REG */ 272 SUNXI_CCU_GATE(A13_CLK_USB_OHCI, "usb-ohci", "osc24m", 273 USBPHY_CFG_REG, 6), 274 SUNXI_CCU_GATE(A13_CLK_USB_PHY0, "usb-phy0", "osc24m", 275 USBPHY_CFG_REG, 8), 276 SUNXI_CCU_GATE(A13_CLK_USB_PHY1, "usb-phy1", "osc24m", 277 USBPHY_CFG_REG, 9), 278 }; 279 280 static int 281 sun5i_a13_ccu_match(device_t parent, cfdata_t cf, void *aux) 282 { 283 struct fdt_attach_args * const faa = aux; 284 285 return of_match_compatible(faa->faa_phandle, compatible); 286 } 287 288 static void 289 sun5i_a13_ccu_attach(device_t parent, device_t self, void *aux) 290 { 291 struct sunxi_ccu_softc * const sc = device_private(self); 292 struct fdt_attach_args * const faa = aux; 293 294 sc->sc_dev = self; 295 sc->sc_phandle = faa->faa_phandle; 296 sc->sc_bst = faa->faa_bst; 297 298 sc->sc_resets = sun5i_a13_ccu_resets; 299 sc->sc_nresets = __arraycount(sun5i_a13_ccu_resets); 300 301 sc->sc_clks = sun5i_a13_ccu_clks; 302 sc->sc_nclks = __arraycount(sun5i_a13_ccu_clks); 303 304 if (sunxi_ccu_attach(sc) != 0) 305 return; 306 307 aprint_naive("\n"); 308 aprint_normal(": A13 CCU\n"); 309 310 sunxi_ccu_print(sc); 311 } 312
Indexes created Fri Oct 03 02:09:57 GMT 2025