sun6i_a31_ccu.c revision 1.2
1 /* $NetBSD: sun6i_a31_ccu.c,v 1.2 2017/07/02 13:36:46 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * Copyright (c) 2017 Emmanuel Vadot <manu (at) freebsd.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 32 __KERNEL_RCSID(1, "$NetBSD: sun6i_a31_ccu.c,v 1.2 2017/07/02 13:36:46 jmcneill Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/systm.h> 38 39 #include <dev/fdt/fdtvar.h> 40 41 #include <arm/sunxi/sunxi_ccu.h> 42 #include <arm/sunxi/sun6i_a31_ccu.h> 43 44 #define PLL_PERIPH_CTRL_REG 0x028 45 #define AHB1_APB1_CFG_REG 0x054 46 #define APB2_CLK_DIV_REG 0x058 47 #define AHB1_GATING_REG0 0x060 48 #define AHB1_GATING_REG1 0x064 49 #define APB1_GATING_REG 0x068 50 #define APB2_GATING_REG 0x06c 51 #define SD0_CLK_REG 0x088 52 #define SD1_CLK_REG 0x08c 53 #define SD2_CLK_REG 0x090 54 #define SD3_CLK_REG 0x094 55 #define USBPHY_CFG_REG 0x0cc 56 #define BUS_SOFT_RST_REG0 0x2c0 57 #define BUS_SOFT_RST_REG1 0x2c4 58 #define BUS_SOFT_RST_REG2 0x2c8 59 #define BUS_SOFT_RST_REG3 0x2d0 60 #define BUS_SOFT_RST_REG4 0x2d8 61 62 static int sun6i_a31_ccu_match(device_t, cfdata_t, void *); 63 static void sun6i_a31_ccu_attach(device_t, device_t, void *); 64 65 static const char * const compatible[] = { 66 "allwinner,sun6i-a31-ccu", 67 NULL 68 }; 69 70 CFATTACH_DECL_NEW(sunxi_a31_ccu, sizeof(struct sunxi_ccu_softc), 71 sun6i_a31_ccu_match, sun6i_a31_ccu_attach, NULL, NULL); 72 73 static struct sunxi_ccu_reset sun6i_a31_ccu_resets[] = { 74 SUNXI_CCU_RESET(A31_RST_USB_PHY0, USBPHY_CFG_REG, 0), 75 SUNXI_CCU_RESET(A31_RST_USB_PHY1, USBPHY_CFG_REG, 1), 76 SUNXI_CCU_RESET(A31_RST_USB_PHY2, USBPHY_CFG_REG, 2), 77 78 SUNXI_CCU_RESET(A31_RST_AHB1_MIPI_DSI, BUS_SOFT_RST_REG0, 1), 79 SUNXI_CCU_RESET(A31_RST_AHB1_SS, BUS_SOFT_RST_REG0, 5), 80 SUNXI_CCU_RESET(A31_RST_AHB1_DMA, BUS_SOFT_RST_REG0, 6), 81 SUNXI_CCU_RESET(A31_RST_AHB1_MMC0, BUS_SOFT_RST_REG0, 8), 82 SUNXI_CCU_RESET(A31_RST_AHB1_MMC1, BUS_SOFT_RST_REG0, 9), 83 SUNXI_CCU_RESET(A31_RST_AHB1_MMC2, BUS_SOFT_RST_REG0, 10), 84 SUNXI_CCU_RESET(A31_RST_AHB1_MMC3, BUS_SOFT_RST_REG0, 11), 85 SUNXI_CCU_RESET(A31_RST_AHB1_NAND1, BUS_SOFT_RST_REG0, 12), 86 SUNXI_CCU_RESET(A31_RST_AHB1_NAND0, BUS_SOFT_RST_REG0, 13), 87 SUNXI_CCU_RESET(A31_RST_AHB1_SDRAM, BUS_SOFT_RST_REG0, 14), 88 SUNXI_CCU_RESET(A31_RST_AHB1_EMAC, BUS_SOFT_RST_REG0, 17), 89 SUNXI_CCU_RESET(A31_RST_AHB1_TS, BUS_SOFT_RST_REG0, 18), 90 SUNXI_CCU_RESET(A31_RST_AHB1_HSTIMER, BUS_SOFT_RST_REG0, 19), 91 SUNXI_CCU_RESET(A31_RST_AHB1_SPI0, BUS_SOFT_RST_REG0, 20), 92 SUNXI_CCU_RESET(A31_RST_AHB1_SPI1, BUS_SOFT_RST_REG0, 21), 93 SUNXI_CCU_RESET(A31_RST_AHB1_SPI2, BUS_SOFT_RST_REG0, 22), 94 SUNXI_CCU_RESET(A31_RST_AHB1_SPI3, BUS_SOFT_RST_REG0, 23), 95 SUNXI_CCU_RESET(A31_RST_AHB1_OTG, BUS_SOFT_RST_REG0, 24), 96 SUNXI_CCU_RESET(A31_RST_AHB1_EHCI0, BUS_SOFT_RST_REG0, 26), 97 SUNXI_CCU_RESET(A31_RST_AHB1_EHCI1, BUS_SOFT_RST_REG0, 27), 98 SUNXI_CCU_RESET(A31_RST_AHB1_OHCI0, BUS_SOFT_RST_REG0, 29), 99 SUNXI_CCU_RESET(A31_RST_AHB1_OHCI1, BUS_SOFT_RST_REG0, 30), 100 SUNXI_CCU_RESET(A31_RST_AHB1_OHCI2, BUS_SOFT_RST_REG0, 31), 101 102 SUNXI_CCU_RESET(A31_RST_AHB1_VE, BUS_SOFT_RST_REG1, 0), 103 SUNXI_CCU_RESET(A31_RST_AHB1_LCD0, BUS_SOFT_RST_REG1, 4), 104 SUNXI_CCU_RESET(A31_RST_AHB1_LCD1, BUS_SOFT_RST_REG1, 5), 105 SUNXI_CCU_RESET(A31_RST_AHB1_CSI, BUS_SOFT_RST_REG1, 8), 106 SUNXI_CCU_RESET(A31_RST_AHB1_HDMI, BUS_SOFT_RST_REG1, 11), 107 SUNXI_CCU_RESET(A31_RST_AHB1_BE0, BUS_SOFT_RST_REG1, 12), 108 SUNXI_CCU_RESET(A31_RST_AHB1_BE1, BUS_SOFT_RST_REG1, 13), 109 SUNXI_CCU_RESET(A31_RST_AHB1_FE0, BUS_SOFT_RST_REG1, 14), 110 SUNXI_CCU_RESET(A31_RST_AHB1_FE1, BUS_SOFT_RST_REG1, 15), 111 SUNXI_CCU_RESET(A31_RST_AHB1_MP, BUS_SOFT_RST_REG1, 16), 112 SUNXI_CCU_RESET(A31_RST_AHB1_GPU, BUS_SOFT_RST_REG1, 20), 113 SUNXI_CCU_RESET(A31_RST_AHB1_DEU0, BUS_SOFT_RST_REG1, 23), 114 SUNXI_CCU_RESET(A31_RST_AHB1_DEU1, BUS_SOFT_RST_REG1, 24), 115 SUNXI_CCU_RESET(A31_RST_AHB1_DRC0, BUS_SOFT_RST_REG1, 25), 116 SUNXI_CCU_RESET(A31_RST_AHB1_DRC1, BUS_SOFT_RST_REG1, 26), 117 118 SUNXI_CCU_RESET(A31_RST_AHB1_LVDS, BUS_SOFT_RST_REG2, 0), 119 120 SUNXI_CCU_RESET(A31_RST_APB1_CODEC, BUS_SOFT_RST_REG3, 0), 121 SUNXI_CCU_RESET(A31_RST_APB1_SPDIF, BUS_SOFT_RST_REG3, 1), 122 SUNXI_CCU_RESET(A31_RST_APB1_DIGITAL_MIC, BUS_SOFT_RST_REG3, 4), 123 SUNXI_CCU_RESET(A31_RST_APB1_DAUDIO0, BUS_SOFT_RST_REG3, 12), 124 SUNXI_CCU_RESET(A31_RST_APB1_DAUDIO1, BUS_SOFT_RST_REG3, 13), 125 126 SUNXI_CCU_RESET(A31_RST_APB2_I2C0, BUS_SOFT_RST_REG4, 0), 127 SUNXI_CCU_RESET(A31_RST_APB2_I2C1, BUS_SOFT_RST_REG4, 1), 128 SUNXI_CCU_RESET(A31_RST_APB2_I2C2, BUS_SOFT_RST_REG4, 2), 129 SUNXI_CCU_RESET(A31_RST_APB2_I2C3, BUS_SOFT_RST_REG4, 3), 130 SUNXI_CCU_RESET(A31_RST_APB2_UART0, BUS_SOFT_RST_REG4, 16), 131 SUNXI_CCU_RESET(A31_RST_APB2_UART1, BUS_SOFT_RST_REG4, 17), 132 SUNXI_CCU_RESET(A31_RST_APB2_UART2, BUS_SOFT_RST_REG4, 18), 133 SUNXI_CCU_RESET(A31_RST_APB2_UART3, BUS_SOFT_RST_REG4, 19), 134 SUNXI_CCU_RESET(A31_RST_APB2_UART4, BUS_SOFT_RST_REG4, 20), 135 SUNXI_CCU_RESET(A31_RST_APB2_UART5, BUS_SOFT_RST_REG4, 21), 136 }; 137 138 static const char *ahb1_parents[] = { "losc", "hosc", "axi", "pll_periph" }; 139 static const char *apb1_parents[] = { "ahb1" }; 140 static const char *apb2_parents[] = { "losc", "hosc", "pll_periph", "pll_periph" }; 141 static const char *mod_parents[] = { "hosc", "pll_periph" }; 142 143 static struct sunxi_ccu_clk sun6i_a31_ccu_clks[] = { 144 SUNXI_CCU_NKMP(A31_CLK_PLL_PERIPH, "pll_periph", "hosc", 145 PLL_PERIPH_CTRL_REG, /* reg */ 146 __BITS(12,8), /* n */ 147 __BITS(5,4), /* k */ 148 0, /* m */ 149 0, /* p */ 150 __BIT(31), /* enable */ 151 SUNXI_CCU_NKMP_DIVIDE_BY_TWO), 152 153 SUNXI_CCU_DIV(A31_CLK_APB1, "apb1", apb1_parents, 154 AHB1_APB1_CFG_REG, /* reg */ 155 __BITS(9,8), /* div */ 156 0, /* sel */ 157 SUNXI_CCU_DIV_POWER_OF_TWO|SUNXI_CCU_DIV_ZERO_IS_ONE), 158 159 SUNXI_CCU_PREDIV(A31_CLK_AHB1, "ahb1", ahb1_parents, 160 AHB1_APB1_CFG_REG, /* reg */ 161 __BITS(7,6), /* prediv */ 162 __BIT(3), /* prediv_sel */ 163 __BITS(5,4), /* div */ 164 __BITS(13,12), /* sel */ 165 SUNXI_CCU_PREDIV_POWER_OF_TWO), 166 167 SUNXI_CCU_NM(A31_CLK_APB2, "apb2", apb2_parents, 168 APB2_CLK_DIV_REG, /* reg */ 169 __BITS(17,16), /* n */ 170 __BITS(4,0), /* m */ 171 __BITS(25,24), /* sel */ 172 0, /* enable */ 173 SUNXI_CCU_NM_POWER_OF_TWO), 174 175 SUNXI_CCU_NM(A31_CLK_MMC0, "mmc0", mod_parents, 176 SD0_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31), 177 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 178 SUNXI_CCU_NM(A31_CLK_MMC1, "mmc1", mod_parents, 179 SD1_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31), 180 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 181 SUNXI_CCU_NM(A31_CLK_MMC2, "mmc2", mod_parents, 182 SD2_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31), 183 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 184 SUNXI_CCU_NM(A31_CLK_MMC3, "mmc3", mod_parents, 185 SD3_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31), 186 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 187 188 SUNXI_CCU_GATE(A31_CLK_AHB1_MMC0, "ahb1-mmc0", "ahb1", 189 AHB1_GATING_REG0, 8), 190 SUNXI_CCU_GATE(A31_CLK_AHB1_MMC1, "ahb1-mmc1", "ahb1", 191 AHB1_GATING_REG0, 9), 192 SUNXI_CCU_GATE(A31_CLK_AHB1_MMC2, "ahb1-mmc2", "ahb1", 193 AHB1_GATING_REG0, 10), 194 SUNXI_CCU_GATE(A31_CLK_AHB1_MMC3, "ahb1-mmc3", "ahb1", 195 AHB1_GATING_REG0, 11), 196 SUNXI_CCU_GATE(A31_CLK_AHB1_EMAC, "ahb1-emac", "ahb1", 197 AHB1_GATING_REG0, 17), 198 SUNXI_CCU_GATE(A31_CLK_AHB1_OTG, "ahb1-otg", "ahb1", 199 AHB1_GATING_REG0, 24), 200 SUNXI_CCU_GATE(A31_CLK_AHB1_EHCI0, "ahb1-ehci0", "ahb1", 201 AHB1_GATING_REG0, 26), 202 SUNXI_CCU_GATE(A31_CLK_AHB1_EHCI1, "ahb1-ehci1", "ahb1", 203 AHB1_GATING_REG0, 27), 204 SUNXI_CCU_GATE(A31_CLK_AHB1_OHCI0, "ahb1-ohci0", "ahb1", 205 AHB1_GATING_REG0, 29), 206 SUNXI_CCU_GATE(A31_CLK_AHB1_OHCI1, "ahb1-ohci1", "ahb1", 207 AHB1_GATING_REG0, 30), 208 SUNXI_CCU_GATE(A31_CLK_AHB1_OHCI2, "ahb1-ohci2", "ahb1", 209 AHB1_GATING_REG0, 31), 210 211 SUNXI_CCU_GATE(A31_CLK_APB1_PIO, "ahb1-pio", "apb1", 212 APB1_GATING_REG, 5), 213 214 SUNXI_CCU_GATE(A31_CLK_APB2_I2C0, "apb2-i2c0", "apb2", 215 APB2_GATING_REG, 0), 216 SUNXI_CCU_GATE(A31_CLK_APB2_I2C1, "apb2-i2c1", "apb2", 217 APB2_GATING_REG, 1), 218 SUNXI_CCU_GATE(A31_CLK_APB2_I2C2, "apb2-i2c2", "apb2", 219 APB2_GATING_REG, 2), 220 SUNXI_CCU_GATE(A31_CLK_APB2_I2C3, "apb2-i2c3", "apb2", 221 APB2_GATING_REG, 3), 222 SUNXI_CCU_GATE(A31_CLK_APB2_UART0, "apb2-uart0", "apb2", 223 APB2_GATING_REG, 16), 224 SUNXI_CCU_GATE(A31_CLK_APB2_UART1, "apb2-uart1", "apb2", 225 APB2_GATING_REG, 17), 226 SUNXI_CCU_GATE(A31_CLK_APB2_UART2, "apb2-uart2", "apb2", 227 APB2_GATING_REG, 18), 228 SUNXI_CCU_GATE(A31_CLK_APB2_UART3, "apb2-uart3", "apb2", 229 APB2_GATING_REG, 19), 230 SUNXI_CCU_GATE(A31_CLK_APB2_UART4, "apb2-uart4", "apb2", 231 APB2_GATING_REG, 20), 232 SUNXI_CCU_GATE(A31_CLK_APB2_UART5, "apb2-uart5", "apb2", 233 APB2_GATING_REG, 21), 234 235 SUNXI_CCU_GATE(A31_CLK_USB_PHY0, "usb-phy0", "hosc", 236 USBPHY_CFG_REG, 8), 237 SUNXI_CCU_GATE(A31_CLK_USB_PHY1, "usb-phy1", "hosc", 238 USBPHY_CFG_REG, 9), 239 SUNXI_CCU_GATE(A31_CLK_USB_PHY2, "usb-phy2", "hosc", 240 USBPHY_CFG_REG, 10), 241 SUNXI_CCU_GATE(A31_CLK_USB_OHCI0, "usb-ohci0", "hosc", 242 USBPHY_CFG_REG, 16), 243 SUNXI_CCU_GATE(A31_CLK_USB_OHCI1, "usb-ohci1", "hosc", 244 USBPHY_CFG_REG, 17), 245 SUNXI_CCU_GATE(A31_CLK_USB_OHCI2, "usb-ohci2", "hosc", 246 USBPHY_CFG_REG, 18), 247 }; 248 249 static int 250 sun6i_a31_ccu_match(device_t parent, cfdata_t cf, void *aux) 251 { 252 struct fdt_attach_args * const faa = aux; 253 254 return of_match_compatible(faa->faa_phandle, compatible); 255 } 256 257 static void 258 sun6i_a31_ccu_attach(device_t parent, device_t self, void *aux) 259 { 260 struct sunxi_ccu_softc * const sc = device_private(self); 261 struct fdt_attach_args * const faa = aux; 262 263 sc->sc_dev = self; 264 sc->sc_phandle = faa->faa_phandle; 265 sc->sc_bst = faa->faa_bst; 266 267 sc->sc_resets = sun6i_a31_ccu_resets; 268 sc->sc_nresets = __arraycount(sun6i_a31_ccu_resets); 269 270 sc->sc_clks = sun6i_a31_ccu_clks; 271 sc->sc_nclks = __arraycount(sun6i_a31_ccu_clks); 272 273 if (sunxi_ccu_attach(sc) != 0) 274 return; 275 276 aprint_naive("\n"); 277 aprint_normal(": A31 CCU\n"); 278 279 sunxi_ccu_print(sc); 280 } 281
Indexes created Thu Oct 02 14:10:14 GMT 2025