sun6i_a31_ccu.c revision 1.5
1 /* $NetBSD: sun6i_a31_ccu.c,v 1.5 2021/01/27 03:10:20 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * Copyright (c) 2017 Emmanuel Vadot <manu (at) freebsd.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 32 __KERNEL_RCSID(1, "$NetBSD: sun6i_a31_ccu.c,v 1.5 2021/01/27 03:10:20 thorpej Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/systm.h> 38 39 #include <dev/fdt/fdtvar.h> 40 41 #include <arm/sunxi/sunxi_ccu.h> 42 #include <arm/sunxi/sun6i_a31_ccu.h> 43 44 #define PLL2_CFG_REG 0x008 45 #define PLL_PERIPH_CTRL_REG 0x028 46 #define AHB1_APB1_CFG_REG 0x054 47 #define APB2_CLK_DIV_REG 0x058 48 #define AHB1_GATING_REG0 0x060 49 #define AHB1_GATING_REG1 0x064 50 #define APB1_GATING_REG 0x068 51 #define APB2_GATING_REG 0x06c 52 #define SD0_CLK_REG 0x088 53 #define SD1_CLK_REG 0x08c 54 #define SD2_CLK_REG 0x090 55 #define SD3_CLK_REG 0x094 56 #define USBPHY_CFG_REG 0x0cc 57 #define AUDIO_CODEC_CLK_REG 0x140 58 #define BUS_SOFT_RST_REG0 0x2c0 59 #define BUS_SOFT_RST_REG1 0x2c4 60 #define BUS_SOFT_RST_REG2 0x2c8 61 #define BUS_SOFT_RST_REG3 0x2d0 62 #define BUS_SOFT_RST_REG4 0x2d8 63 64 static int sun6i_a31_ccu_match(device_t, cfdata_t, void *); 65 static void sun6i_a31_ccu_attach(device_t, device_t, void *); 66 67 static const struct device_compatible_entry compat_data[] = { 68 { .compat = "allwinner,sun6i-a31-ccu" }, 69 DEVICE_COMPAT_EOL 70 }; 71 72 CFATTACH_DECL_NEW(sunxi_a31_ccu, sizeof(struct sunxi_ccu_softc), 73 sun6i_a31_ccu_match, sun6i_a31_ccu_attach, NULL, NULL); 74 75 static struct sunxi_ccu_reset sun6i_a31_ccu_resets[] = { 76 SUNXI_CCU_RESET(A31_RST_USB_PHY0, USBPHY_CFG_REG, 0), 77 SUNXI_CCU_RESET(A31_RST_USB_PHY1, USBPHY_CFG_REG, 1), 78 SUNXI_CCU_RESET(A31_RST_USB_PHY2, USBPHY_CFG_REG, 2), 79 80 SUNXI_CCU_RESET(A31_RST_AHB1_MIPI_DSI, BUS_SOFT_RST_REG0, 1), 81 SUNXI_CCU_RESET(A31_RST_AHB1_SS, BUS_SOFT_RST_REG0, 5), 82 SUNXI_CCU_RESET(A31_RST_AHB1_DMA, BUS_SOFT_RST_REG0, 6), 83 SUNXI_CCU_RESET(A31_RST_AHB1_MMC0, BUS_SOFT_RST_REG0, 8), 84 SUNXI_CCU_RESET(A31_RST_AHB1_MMC1, BUS_SOFT_RST_REG0, 9), 85 SUNXI_CCU_RESET(A31_RST_AHB1_MMC2, BUS_SOFT_RST_REG0, 10), 86 SUNXI_CCU_RESET(A31_RST_AHB1_MMC3, BUS_SOFT_RST_REG0, 11), 87 SUNXI_CCU_RESET(A31_RST_AHB1_NAND1, BUS_SOFT_RST_REG0, 12), 88 SUNXI_CCU_RESET(A31_RST_AHB1_NAND0, BUS_SOFT_RST_REG0, 13), 89 SUNXI_CCU_RESET(A31_RST_AHB1_SDRAM, BUS_SOFT_RST_REG0, 14), 90 SUNXI_CCU_RESET(A31_RST_AHB1_EMAC, BUS_SOFT_RST_REG0, 17), 91 SUNXI_CCU_RESET(A31_RST_AHB1_TS, BUS_SOFT_RST_REG0, 18), 92 SUNXI_CCU_RESET(A31_RST_AHB1_HSTIMER, BUS_SOFT_RST_REG0, 19), 93 SUNXI_CCU_RESET(A31_RST_AHB1_SPI0, BUS_SOFT_RST_REG0, 20), 94 SUNXI_CCU_RESET(A31_RST_AHB1_SPI1, BUS_SOFT_RST_REG0, 21), 95 SUNXI_CCU_RESET(A31_RST_AHB1_SPI2, BUS_SOFT_RST_REG0, 22), 96 SUNXI_CCU_RESET(A31_RST_AHB1_SPI3, BUS_SOFT_RST_REG0, 23), 97 SUNXI_CCU_RESET(A31_RST_AHB1_OTG, BUS_SOFT_RST_REG0, 24), 98 SUNXI_CCU_RESET(A31_RST_AHB1_EHCI0, BUS_SOFT_RST_REG0, 26), 99 SUNXI_CCU_RESET(A31_RST_AHB1_EHCI1, BUS_SOFT_RST_REG0, 27), 100 SUNXI_CCU_RESET(A31_RST_AHB1_OHCI0, BUS_SOFT_RST_REG0, 29), 101 SUNXI_CCU_RESET(A31_RST_AHB1_OHCI1, BUS_SOFT_RST_REG0, 30), 102 SUNXI_CCU_RESET(A31_RST_AHB1_OHCI2, BUS_SOFT_RST_REG0, 31), 103 104 SUNXI_CCU_RESET(A31_RST_AHB1_VE, BUS_SOFT_RST_REG1, 0), 105 SUNXI_CCU_RESET(A31_RST_AHB1_LCD0, BUS_SOFT_RST_REG1, 4), 106 SUNXI_CCU_RESET(A31_RST_AHB1_LCD1, BUS_SOFT_RST_REG1, 5), 107 SUNXI_CCU_RESET(A31_RST_AHB1_CSI, BUS_SOFT_RST_REG1, 8), 108 SUNXI_CCU_RESET(A31_RST_AHB1_HDMI, BUS_SOFT_RST_REG1, 11), 109 SUNXI_CCU_RESET(A31_RST_AHB1_BE0, BUS_SOFT_RST_REG1, 12), 110 SUNXI_CCU_RESET(A31_RST_AHB1_BE1, BUS_SOFT_RST_REG1, 13), 111 SUNXI_CCU_RESET(A31_RST_AHB1_FE0, BUS_SOFT_RST_REG1, 14), 112 SUNXI_CCU_RESET(A31_RST_AHB1_FE1, BUS_SOFT_RST_REG1, 15), 113 SUNXI_CCU_RESET(A31_RST_AHB1_MP, BUS_SOFT_RST_REG1, 16), 114 SUNXI_CCU_RESET(A31_RST_AHB1_GPU, BUS_SOFT_RST_REG1, 20), 115 SUNXI_CCU_RESET(A31_RST_AHB1_DEU0, BUS_SOFT_RST_REG1, 23), 116 SUNXI_CCU_RESET(A31_RST_AHB1_DEU1, BUS_SOFT_RST_REG1, 24), 117 SUNXI_CCU_RESET(A31_RST_AHB1_DRC0, BUS_SOFT_RST_REG1, 25), 118 SUNXI_CCU_RESET(A31_RST_AHB1_DRC1, BUS_SOFT_RST_REG1, 26), 119 120 SUNXI_CCU_RESET(A31_RST_AHB1_LVDS, BUS_SOFT_RST_REG2, 0), 121 122 SUNXI_CCU_RESET(A31_RST_APB1_CODEC, BUS_SOFT_RST_REG3, 0), 123 SUNXI_CCU_RESET(A31_RST_APB1_SPDIF, BUS_SOFT_RST_REG3, 1), 124 SUNXI_CCU_RESET(A31_RST_APB1_DIGITAL_MIC, BUS_SOFT_RST_REG3, 4), 125 SUNXI_CCU_RESET(A31_RST_APB1_DAUDIO0, BUS_SOFT_RST_REG3, 12), 126 SUNXI_CCU_RESET(A31_RST_APB1_DAUDIO1, BUS_SOFT_RST_REG3, 13), 127 128 SUNXI_CCU_RESET(A31_RST_APB2_I2C0, BUS_SOFT_RST_REG4, 0), 129 SUNXI_CCU_RESET(A31_RST_APB2_I2C1, BUS_SOFT_RST_REG4, 1), 130 SUNXI_CCU_RESET(A31_RST_APB2_I2C2, BUS_SOFT_RST_REG4, 2), 131 SUNXI_CCU_RESET(A31_RST_APB2_I2C3, BUS_SOFT_RST_REG4, 3), 132 SUNXI_CCU_RESET(A31_RST_APB2_UART0, BUS_SOFT_RST_REG4, 16), 133 SUNXI_CCU_RESET(A31_RST_APB2_UART1, BUS_SOFT_RST_REG4, 17), 134 SUNXI_CCU_RESET(A31_RST_APB2_UART2, BUS_SOFT_RST_REG4, 18), 135 SUNXI_CCU_RESET(A31_RST_APB2_UART3, BUS_SOFT_RST_REG4, 19), 136 SUNXI_CCU_RESET(A31_RST_APB2_UART4, BUS_SOFT_RST_REG4, 20), 137 SUNXI_CCU_RESET(A31_RST_APB2_UART5, BUS_SOFT_RST_REG4, 21), 138 }; 139 140 static const char *ahb1_parents[] = { "losc", "hosc", "axi", "pll_periph" }; 141 static const char *apb1_parents[] = { "ahb1" }; 142 static const char *apb2_parents[] = { "losc", "hosc", "pll_periph", "pll_periph" }; 143 static const char *mod_parents[] = { "hosc", "pll_periph" }; 144 145 static const struct sunxi_ccu_nkmp_tbl sun6i_a31_pll_audio_table[] = { 146 { 24576000, 85, 0, 20, 3 }, 147 { 0 } 148 }; 149 150 static struct sunxi_ccu_clk sun6i_a31_ccu_clks[] = { 151 SUNXI_CCU_NKMP_TABLE(A31_CLK_PLL_AUDIO_BASE, "pll_audio", "hosc", 152 PLL2_CFG_REG, /* reg */ 153 __BITS(14,8), /* n */ 154 0, /* k */ 155 __BITS(4,0), /* m */ 156 __BITS(19,16), /* p */ 157 __BIT(31), /* enable */ 158 __BIT(28), /* lock */ 159 sun6i_a31_pll_audio_table, /* table */ 160 0), 161 162 SUNXI_CCU_NKMP(A31_CLK_PLL_PERIPH, "pll_periph", "hosc", 163 PLL_PERIPH_CTRL_REG, /* reg */ 164 __BITS(12,8), /* n */ 165 __BITS(5,4), /* k */ 166 0, /* m */ 167 0, /* p */ 168 __BIT(31), /* enable */ 169 SUNXI_CCU_NKMP_DIVIDE_BY_TWO), 170 171 SUNXI_CCU_DIV(A31_CLK_APB1, "apb1", apb1_parents, 172 AHB1_APB1_CFG_REG, /* reg */ 173 __BITS(9,8), /* div */ 174 0, /* sel */ 175 SUNXI_CCU_DIV_POWER_OF_TWO|SUNXI_CCU_DIV_ZERO_IS_ONE), 176 177 SUNXI_CCU_PREDIV(A31_CLK_AHB1, "ahb1", ahb1_parents, 178 AHB1_APB1_CFG_REG, /* reg */ 179 __BITS(7,6), /* prediv */ 180 __BIT(3), /* prediv_sel */ 181 __BITS(5,4), /* div */ 182 __BITS(13,12), /* sel */ 183 SUNXI_CCU_PREDIV_POWER_OF_TWO), 184 185 SUNXI_CCU_NM(A31_CLK_APB2, "apb2", apb2_parents, 186 APB2_CLK_DIV_REG, /* reg */ 187 __BITS(17,16), /* n */ 188 __BITS(4,0), /* m */ 189 __BITS(25,24), /* sel */ 190 0, /* enable */ 191 SUNXI_CCU_NM_POWER_OF_TWO), 192 193 SUNXI_CCU_NM(A31_CLK_MMC0, "mmc0", mod_parents, 194 SD0_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31), 195 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 196 SUNXI_CCU_NM(A31_CLK_MMC1, "mmc1", mod_parents, 197 SD1_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31), 198 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 199 SUNXI_CCU_NM(A31_CLK_MMC2, "mmc2", mod_parents, 200 SD2_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31), 201 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 202 SUNXI_CCU_NM(A31_CLK_MMC3, "mmc3", mod_parents, 203 SD3_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31), 204 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 205 206 SUNXI_CCU_GATE(A31_CLK_AHB1_DMA, "ahb1-dma", "ahb1", 207 AHB1_GATING_REG0, 6), 208 SUNXI_CCU_GATE(A31_CLK_AHB1_MMC0, "ahb1-mmc0", "ahb1", 209 AHB1_GATING_REG0, 8), 210 SUNXI_CCU_GATE(A31_CLK_AHB1_MMC1, "ahb1-mmc1", "ahb1", 211 AHB1_GATING_REG0, 9), 212 SUNXI_CCU_GATE(A31_CLK_AHB1_MMC2, "ahb1-mmc2", "ahb1", 213 AHB1_GATING_REG0, 10), 214 SUNXI_CCU_GATE(A31_CLK_AHB1_MMC3, "ahb1-mmc3", "ahb1", 215 AHB1_GATING_REG0, 11), 216 SUNXI_CCU_GATE(A31_CLK_AHB1_EMAC, "ahb1-emac", "ahb1", 217 AHB1_GATING_REG0, 17), 218 SUNXI_CCU_GATE(A31_CLK_AHB1_OTG, "ahb1-otg", "ahb1", 219 AHB1_GATING_REG0, 24), 220 SUNXI_CCU_GATE(A31_CLK_AHB1_EHCI0, "ahb1-ehci0", "ahb1", 221 AHB1_GATING_REG0, 26), 222 SUNXI_CCU_GATE(A31_CLK_AHB1_EHCI1, "ahb1-ehci1", "ahb1", 223 AHB1_GATING_REG0, 27), 224 SUNXI_CCU_GATE(A31_CLK_AHB1_OHCI0, "ahb1-ohci0", "ahb1", 225 AHB1_GATING_REG0, 29), 226 SUNXI_CCU_GATE(A31_CLK_AHB1_OHCI1, "ahb1-ohci1", "ahb1", 227 AHB1_GATING_REG0, 30), 228 SUNXI_CCU_GATE(A31_CLK_AHB1_OHCI2, "ahb1-ohci2", "ahb1", 229 AHB1_GATING_REG0, 31), 230 231 SUNXI_CCU_GATE(A31_CLK_APB1_CODEC, "apb1-codec", "apb1", 232 APB1_GATING_REG, 0), 233 SUNXI_CCU_GATE(A31_CLK_APB1_PIO, "apb1-pio", "apb1", 234 APB1_GATING_REG, 5), 235 236 SUNXI_CCU_GATE(A31_CLK_APB2_I2C0, "apb2-i2c0", "apb2", 237 APB2_GATING_REG, 0), 238 SUNXI_CCU_GATE(A31_CLK_APB2_I2C1, "apb2-i2c1", "apb2", 239 APB2_GATING_REG, 1), 240 SUNXI_CCU_GATE(A31_CLK_APB2_I2C2, "apb2-i2c2", "apb2", 241 APB2_GATING_REG, 2), 242 SUNXI_CCU_GATE(A31_CLK_APB2_I2C3, "apb2-i2c3", "apb2", 243 APB2_GATING_REG, 3), 244 SUNXI_CCU_GATE(A31_CLK_APB2_UART0, "apb2-uart0", "apb2", 245 APB2_GATING_REG, 16), 246 SUNXI_CCU_GATE(A31_CLK_APB2_UART1, "apb2-uart1", "apb2", 247 APB2_GATING_REG, 17), 248 SUNXI_CCU_GATE(A31_CLK_APB2_UART2, "apb2-uart2", "apb2", 249 APB2_GATING_REG, 18), 250 SUNXI_CCU_GATE(A31_CLK_APB2_UART3, "apb2-uart3", "apb2", 251 APB2_GATING_REG, 19), 252 SUNXI_CCU_GATE(A31_CLK_APB2_UART4, "apb2-uart4", "apb2", 253 APB2_GATING_REG, 20), 254 SUNXI_CCU_GATE(A31_CLK_APB2_UART5, "apb2-uart5", "apb2", 255 APB2_GATING_REG, 21), 256 257 SUNXI_CCU_GATE(A31_CLK_USB_PHY0, "usb-phy0", "hosc", 258 USBPHY_CFG_REG, 8), 259 SUNXI_CCU_GATE(A31_CLK_USB_PHY1, "usb-phy1", "hosc", 260 USBPHY_CFG_REG, 9), 261 SUNXI_CCU_GATE(A31_CLK_USB_PHY2, "usb-phy2", "hosc", 262 USBPHY_CFG_REG, 10), 263 SUNXI_CCU_GATE(A31_CLK_USB_OHCI0, "usb-ohci0", "hosc", 264 USBPHY_CFG_REG, 16), 265 SUNXI_CCU_GATE(A31_CLK_USB_OHCI1, "usb-ohci1", "hosc", 266 USBPHY_CFG_REG, 17), 267 SUNXI_CCU_GATE(A31_CLK_USB_OHCI2, "usb-ohci2", "hosc", 268 USBPHY_CFG_REG, 18), 269 270 SUNXI_CCU_GATE(A31_CLK_CODEC, "codec", "pll_audio", 271 AUDIO_CODEC_CLK_REG, 31), 272 }; 273 274 static int 275 sun6i_a31_ccu_match(device_t parent, cfdata_t cf, void *aux) 276 { 277 struct fdt_attach_args * const faa = aux; 278 279 return of_compatible_match(faa->faa_phandle, compat_data); 280 } 281 282 static void 283 sun6i_a31_ccu_attach(device_t parent, device_t self, void *aux) 284 { 285 struct sunxi_ccu_softc * const sc = device_private(self); 286 struct fdt_attach_args * const faa = aux; 287 288 sc->sc_dev = self; 289 sc->sc_phandle = faa->faa_phandle; 290 sc->sc_bst = faa->faa_bst; 291 292 sc->sc_resets = sun6i_a31_ccu_resets; 293 sc->sc_nresets = __arraycount(sun6i_a31_ccu_resets); 294 295 sc->sc_clks = sun6i_a31_ccu_clks; 296 sc->sc_nclks = __arraycount(sun6i_a31_ccu_clks); 297 298 if (sunxi_ccu_attach(sc) != 0) 299 return; 300 301 aprint_naive("\n"); 302 aprint_normal(": A31 CCU\n"); 303 304 sunxi_ccu_print(sc); 305 } 306
Indexes created Thu Oct 02 14:10:14 GMT 2025