sun6i_dma.c revision 1.14
1 /* $NetBSD: sun6i_dma.c,v 1.14 2021/01/27 03:10:20 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2014-2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_ddb.h" 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: sun6i_dma.c,v 1.14 2021/01/27 03:10:20 thorpej Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/intr.h> 38 #include <sys/systm.h> 39 #include <sys/mutex.h> 40 #include <sys/bitops.h> 41 #include <sys/kmem.h> 42 43 #include <dev/fdt/fdtvar.h> 44 45 #define DMA_IRQ_EN_REG0_REG 0x0000 46 #define DMA_IRQ_EN_REG1_REG 0x0004 47 #define DMA_IRQ_EN_REG0_QUEUE_IRQ_EN(n) __BIT(n * 4 + 2) 48 #define DMA_IRQ_EN_REG0_PKG_IRQ_EN(n) __BIT(n * 4 + 1) 49 #define DMA_IRQ_EN_REG0_HLAF_IRQ_EN(n) __BIT(n * 4 + 0) 50 #define DMA_IRQ_EN_REG1_QUEUE_IRQ_EN(n) __BIT((n - 8) * 4 + 2) 51 #define DMA_IRQ_EN_REG1_PKG_IRQ_EN(n) __BIT((n - 8) * 4 + 1) 52 #define DMA_IRQ_EN_REG1_HLAF_IRQ_EN(n) __BIT((n - 8) * 4 + 0) 53 #define DMA_IRQ_PEND_REG0_REG 0x0010 54 #define DMA_IRQ_PEND_REG1_REG 0x0014 55 #define DMA_IRQ_QUEUE_MASK 0x4444444444444444ULL 56 #define DMA_IRQ_PKG_MASK 0x2222222222222222ULL 57 #define DMA_IRQ_HF_MASK 0x1111111111111111ULL 58 #define DMA_STA_REG 0x0030 59 #define DMA_EN_REG(n) (0x0100 + (n) * 0x40 + 0x00) 60 #define DMA_EN_EN __BIT(0) 61 #define DMA_PAU_REG(n) (0x0100 + (n) * 0x40 + 0x04) 62 #define DMA_PAU_PAUSE __BIT(0) 63 #define DMA_START_ADDR_REG(n) (0x0100 + (n) * 0x40 + 0x08) 64 #define DMA_CFG_REG(n) (0x0100 + (n) * 0x40 + 0x0C) 65 #define DMA_CFG_DEST_DATA_WIDTH __BITS(26,25) 66 #define DMA_CFG_DATA_WIDTH(n) ((n) >> 4) 67 #define DMA_CFG_BST_LEN(n) ((n) == 1 ? 0 : (((n) >> 3) + 1)) 68 #define DMA_CFG_DEST_ADDR_MODE __BITS(22,21) 69 #define DMA_CFG_ADDR_MODE_LINEAR 0 70 #define DMA_CFG_ADDR_MODE_IO 1 71 #define DMA_CFG_DEST_DRQ_TYPE __BITS(20,16) 72 #define DMA_CFG_DRQ_TYPE_SDRAM 1 73 #define DMA_CFG_SRC_DATA_WIDTH __BITS(10,9) 74 #define DMA_CFG_SRC_ADDR_MODE __BITS(6,5) 75 #define DMA_CFG_SRC_DRQ_TYPE __BITS(4,0) 76 #define DMA_CUR_SRC_REG(n) (0x0100 + (n) * 0x40 + 0x10) 77 #define DMA_CUR_DEST_REG(n) (0x0100 + (n) * 0x40 + 0x14) 78 #define DMA_BCNT_LEFT_REG(n) (0x0100 + (n) * 0x40 + 0x18) 79 #define DMA_PARA_REG(n) (0x0100 + (n) * 0x40 + 0x1C) 80 #define DMA_PARA_DATA_BLK_SIZE __BITS(15,8) 81 #define DMA_PARA_WAIT_CYC __BITS(7,0) 82 #define DMA_MODE_REG(n) (0x0100 + (n) * 0x40 + 0x28) 83 #define MODE_WAIT 0b0 84 #define MODE_HANDSHAKE 0b1 85 #define DMA_MODE_DST(m) __SHIFTIN((m), __BIT(3)) 86 #define DMA_MODE_SRC(m) __SHIFTIN((m), __BIT(2)) 87 #define DMA_FDESC_ADDR_REG(n) (0x0100 + (n) * 0x40 + 0x2C) 88 #define DMA_PKG_NUM_REG(n) (0x0100 + (n) * 0x40 + 0x30) 89 90 struct sun6idma_desc { 91 uint32_t dma_config; 92 uint32_t dma_srcaddr; 93 uint32_t dma_dstaddr; 94 uint32_t dma_bcnt; 95 uint32_t dma_para; 96 uint32_t dma_next; 97 #define DMA_NULL 0xfffff800 98 }; 99 100 struct sun6idma_config { 101 u_int num_channels; 102 bool autogate; 103 uint8_t bursts; 104 uint8_t widths; 105 bus_size_t autogate_reg; 106 uint32_t autogate_mask; 107 uint32_t burst_mask; 108 }; 109 110 #define IL2B(x) __BIT(ilog2(x)) 111 #define IL2B_RANGE(x, y) __BITS(ilog2(x), ilog2(y)) 112 #define WIDTHS_1_2_4 IL2B_RANGE(4, 1) 113 #define WIDTHS_1_2_4_8 IL2B_RANGE(8, 1) 114 #define BURSTS_1_8 (IL2B(8)|IL2B(1)) 115 #define BURSTS_1_4_8_16 (IL2B(16)|IL2B(8)|IL2B(4)|IL2B(1)) 116 117 static const struct sun6idma_config sun6i_a31_dma_config = { 118 .num_channels = 16, 119 .burst_mask = __BITS(8,7), 120 .bursts = BURSTS_1_8, 121 .widths = WIDTHS_1_2_4, 122 }; 123 124 static const struct sun6idma_config sun8i_a83t_dma_config = { 125 .num_channels = 8, 126 .autogate = true, 127 .autogate_reg = 0x20, 128 .autogate_mask = 0x4, 129 .burst_mask = __BITS(8,7), 130 .bursts = BURSTS_1_8, 131 .widths = WIDTHS_1_2_4, 132 }; 133 134 static const struct sun6idma_config sun8i_h3_dma_config = { 135 .num_channels = 12, 136 .autogate = true, 137 .autogate_reg = 0x28, 138 .autogate_mask = 0x4, 139 .burst_mask = __BITS(7,6), 140 .bursts = BURSTS_1_4_8_16, 141 .widths = WIDTHS_1_2_4_8, 142 }; 143 144 static const struct sun6idma_config sun50i_a64_dma_config = { 145 .num_channels = 8, 146 .autogate = true, 147 .autogate_reg = 0x28, 148 .autogate_mask = 0x4, 149 .burst_mask = __BITS(7,6), 150 .bursts = BURSTS_1_4_8_16, 151 .widths = WIDTHS_1_2_4_8, 152 }; 153 154 static const struct device_compatible_entry compat_data[] = { 155 { .compat = "allwinner,sun6i-a31-dma", 156 .data = &sun6i_a31_dma_config }, 157 { .compat = "allwinner,sun8i-a83t-dma", 158 .data = &sun8i_a83t_dma_config }, 159 { .compat = "allwinner,sun8i-h3-dma", 160 .data = &sun8i_h3_dma_config }, 161 { .compat = "allwinner,sun50i-a64-dma", 162 .data = &sun50i_a64_dma_config }, 163 164 DEVICE_COMPAT_EOL 165 }; 166 167 struct sun6idma_channel { 168 uint8_t ch_index; 169 void (*ch_callback)(void *); 170 void *ch_callbackarg; 171 u_int ch_portid; 172 void *ch_dmadesc; 173 }; 174 175 struct sun6idma_softc { 176 device_t sc_dev; 177 bus_space_tag_t sc_bst; 178 bus_space_handle_t sc_bsh; 179 bus_dma_tag_t sc_dmat; 180 int sc_phandle; 181 void *sc_ih; 182 183 uint32_t sc_burst_mask; 184 185 kmutex_t sc_lock; 186 187 struct sun6idma_channel *sc_chan; 188 u_int sc_nchan; 189 u_int sc_ndesc_ch; 190 uint8_t sc_widths; 191 uint8_t sc_bursts; 192 193 bus_dma_segment_t sc_dmasegs[1]; 194 bus_dmamap_t sc_dmamap; 195 void *sc_dmadescs; 196 }; 197 198 #define DMA_READ(sc, reg) \ 199 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 200 #define DMA_WRITE(sc, reg, val) \ 201 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 202 203 #define DESC_NUM ((MAXPHYS / MIN_PAGE_SIZE + 1) + 1) 204 #define DESC_LEN(n) \ 205 (sizeof(struct sun6idma_desc) * (n)) 206 #define DESC_OFFS(ch, n) \ 207 ((ch) * roundup2(DESC_LEN(DESC_NUM), COHERENCY_UNIT) + DESC_LEN(n)) 208 #define DESC_ADDR(sc, chp, n) \ 209 ((sc)->sc_dmamap->dm_segs[0].ds_addr + DESC_OFFS((chp)->ch_index, (n))) 210 211 static void * 212 sun6idma_acquire(device_t dev, const void *data, size_t len, 213 void (*cb)(void *), void *cbarg) 214 { 215 struct sun6idma_softc *sc = device_private(dev); 216 struct sun6idma_channel *ch = NULL; 217 uint32_t irqen; 218 uint8_t index; 219 220 if (len != 4) 221 return NULL; 222 223 const u_int portid = be32dec(data); 224 if (portid > __SHIFTOUT_MASK(DMA_CFG_SRC_DRQ_TYPE)) 225 return NULL; 226 227 mutex_enter(&sc->sc_lock); 228 229 for (index = 0; index < sc->sc_nchan; index++) { 230 if (sc->sc_chan[index].ch_callback == NULL) { 231 ch = &sc->sc_chan[index]; 232 ch->ch_callback = cb; 233 ch->ch_callbackarg = cbarg; 234 ch->ch_portid = portid; 235 236 irqen = DMA_READ(sc, index < 8 ? 237 DMA_IRQ_EN_REG0_REG : 238 DMA_IRQ_EN_REG1_REG); 239 irqen |= (index < 8 ? 240 DMA_IRQ_EN_REG0_PKG_IRQ_EN(index) : 241 DMA_IRQ_EN_REG1_PKG_IRQ_EN(index)); 242 DMA_WRITE(sc, index < 8 ? 243 DMA_IRQ_EN_REG0_REG : 244 DMA_IRQ_EN_REG1_REG, irqen); 245 246 break; 247 } 248 } 249 250 mutex_exit(&sc->sc_lock); 251 252 return ch; 253 } 254 255 static void 256 sun6idma_release(device_t dev, void *priv) 257 { 258 struct sun6idma_softc *sc = device_private(dev); 259 struct sun6idma_channel *ch = priv; 260 uint32_t irqen; 261 uint8_t index = ch->ch_index; 262 263 mutex_enter(&sc->sc_lock); 264 265 irqen = DMA_READ(sc, index < 8 ? 266 DMA_IRQ_EN_REG0_REG : 267 DMA_IRQ_EN_REG1_REG); 268 irqen &= ~(index < 8 ? 269 DMA_IRQ_EN_REG0_PKG_IRQ_EN(index) : 270 DMA_IRQ_EN_REG1_PKG_IRQ_EN(index)); 271 DMA_WRITE(sc, index < 8 ? 272 DMA_IRQ_EN_REG0_REG : 273 DMA_IRQ_EN_REG1_REG, irqen); 274 275 ch->ch_callback = NULL; 276 ch->ch_callbackarg = NULL; 277 278 mutex_exit(&sc->sc_lock); 279 } 280 281 static int 282 sun6idma_transfer(device_t dev, void *priv, struct fdtbus_dma_req *req) 283 { 284 struct sun6idma_softc *sc = device_private(dev); 285 struct sun6idma_channel *ch = priv; 286 struct sun6idma_desc *desc = ch->ch_dmadesc; 287 uint32_t src, dst, len, cfg, mem_cfg, dev_cfg; 288 uint32_t mem_width, dev_width, mem_burst, dev_burst; 289 290 if (req->dreq_nsegs > sc->sc_ndesc_ch) 291 return EINVAL; 292 293 if ((sc->sc_widths & 294 IL2B(req->dreq_mem_opt.opt_bus_width/NBBY)) == 0) 295 return EINVAL; 296 if ((sc->sc_widths & 297 IL2B(req->dreq_dev_opt.opt_bus_width/NBBY)) == 0) 298 return EINVAL; 299 if ((sc->sc_bursts & 300 IL2B(req->dreq_mem_opt.opt_burst_len)) == 0) 301 return EINVAL; 302 if ((sc->sc_bursts & 303 IL2B(req->dreq_dev_opt.opt_burst_len)) == 0) 304 return EINVAL; 305 306 mem_width = DMA_CFG_DATA_WIDTH(req->dreq_mem_opt.opt_bus_width); 307 dev_width = DMA_CFG_DATA_WIDTH(req->dreq_dev_opt.opt_bus_width); 308 mem_burst = DMA_CFG_BST_LEN(req->dreq_mem_opt.opt_burst_len); 309 dev_burst = DMA_CFG_BST_LEN(req->dreq_dev_opt.opt_burst_len); 310 311 mem_cfg = __SHIFTIN(mem_width, DMA_CFG_SRC_DATA_WIDTH) | 312 __SHIFTIN(mem_burst, sc->sc_burst_mask) | 313 __SHIFTIN(DMA_CFG_ADDR_MODE_LINEAR, DMA_CFG_SRC_ADDR_MODE) | 314 __SHIFTIN(DMA_CFG_DRQ_TYPE_SDRAM, DMA_CFG_SRC_DRQ_TYPE); 315 dev_cfg = __SHIFTIN(dev_width, DMA_CFG_SRC_DATA_WIDTH) | 316 __SHIFTIN(dev_burst, sc->sc_burst_mask) | 317 __SHIFTIN(DMA_CFG_ADDR_MODE_IO, DMA_CFG_SRC_ADDR_MODE) | 318 __SHIFTIN(ch->ch_portid, DMA_CFG_SRC_DRQ_TYPE); 319 320 for (size_t j = 0; j < req->dreq_nsegs; j++) { 321 if (req->dreq_dir == FDT_DMA_READ) { 322 src = req->dreq_dev_phys; 323 dst = req->dreq_segs[j].ds_addr; 324 cfg = mem_cfg << 16 | dev_cfg; 325 } else { 326 src = req->dreq_segs[j].ds_addr; 327 dst = req->dreq_dev_phys; 328 cfg = dev_cfg << 16 | mem_cfg; 329 } 330 len = req->dreq_segs[j].ds_len; 331 332 desc[j].dma_config = htole32(cfg); 333 desc[j].dma_srcaddr = htole32(src); 334 desc[j].dma_dstaddr = htole32(dst); 335 desc[j].dma_bcnt = htole32(len); 336 desc[j].dma_para = htole32(0); 337 if (j < req->dreq_nsegs - 1) 338 desc[j].dma_next = htole32(DESC_ADDR(sc, ch, j + 1)); 339 else 340 desc[j].dma_next = htole32(DMA_NULL); 341 } 342 343 #if notyet && maybenever 344 DMA_WRITE(sc, DMA_MODE_REG(ch->ch_index), 345 DMA_MODE_DST(MODE_HANDSHAKE)|DMA_MODE_SRC(MODE_HANDSHAKE)); 346 #endif 347 348 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, DESC_OFFS(ch->ch_index, 0), 349 DESC_LEN(req->dreq_nsegs), BUS_DMASYNC_PREWRITE); 350 351 DMA_WRITE(sc, DMA_START_ADDR_REG(ch->ch_index), 352 DESC_ADDR(sc, ch, 0)); 353 DMA_WRITE(sc, DMA_EN_REG(ch->ch_index), DMA_EN_EN); 354 355 if ((DMA_READ(sc, DMA_EN_REG(ch->ch_index)) & DMA_EN_EN) == 0) { 356 aprint_error_dev(sc->sc_dev, 357 "DMA Channel %u failed to start\n", ch->ch_index); 358 return EIO; 359 } 360 361 return 0; 362 } 363 364 static void 365 sun6idma_halt(device_t dev, void *priv) 366 { 367 struct sun6idma_softc *sc = device_private(dev); 368 struct sun6idma_channel *ch = priv; 369 370 DMA_WRITE(sc, DMA_EN_REG(ch->ch_index), 0); 371 } 372 373 static const struct fdtbus_dma_controller_func sun6idma_funcs = { 374 .acquire = sun6idma_acquire, 375 .release = sun6idma_release, 376 .transfer = sun6idma_transfer, 377 .halt = sun6idma_halt 378 }; 379 380 static int 381 sun6idma_intr(void *priv) 382 { 383 struct sun6idma_softc *sc = priv; 384 uint32_t pend0, pend1, bit; 385 uint64_t pend, mask; 386 uint8_t index; 387 388 pend0 = DMA_READ(sc, DMA_IRQ_PEND_REG0_REG); 389 pend1 = DMA_READ(sc, DMA_IRQ_PEND_REG1_REG); 390 if (!pend0 && !pend1) 391 return 0; 392 393 DMA_WRITE(sc, DMA_IRQ_PEND_REG0_REG, pend0); 394 DMA_WRITE(sc, DMA_IRQ_PEND_REG1_REG, pend1); 395 396 pend = pend0 | ((uint64_t)pend1 << 32); 397 398 while ((bit = ffs64(pend & DMA_IRQ_PKG_MASK)) != 0) { 399 mask = __BIT(bit - 1); 400 pend &= ~mask; 401 index = (bit - 1) / 4; 402 403 if (sc->sc_chan[index].ch_callback == NULL) 404 continue; 405 sc->sc_chan[index].ch_callback( 406 sc->sc_chan[index].ch_callbackarg); 407 } 408 409 return 1; 410 } 411 412 static int 413 sun6idma_match(device_t parent, cfdata_t cf, void *aux) 414 { 415 struct fdt_attach_args * const faa = aux; 416 417 return of_compatible_match(faa->faa_phandle, compat_data); 418 } 419 420 static void 421 sun6idma_attach(device_t parent, device_t self, void *aux) 422 { 423 struct sun6idma_softc * const sc = device_private(self); 424 struct fdt_attach_args * const faa = aux; 425 const int phandle = faa->faa_phandle; 426 size_t desclen; 427 const struct sun6idma_config *conf; 428 struct fdtbus_reset *rst; 429 struct clk *clk; 430 char intrstr[128]; 431 bus_addr_t addr; 432 bus_size_t size; 433 int error, nsegs; 434 u_int index; 435 436 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 437 aprint_error(": couldn't get registers\n"); 438 return; 439 } 440 441 if ((clk = fdtbus_clock_get_index(phandle, 0)) == NULL || 442 clk_enable(clk) != 0) { 443 aprint_error(": couldn't enable clock\n"); 444 return; 445 } 446 if ((rst = fdtbus_reset_get_index(phandle, 0)) == NULL || 447 fdtbus_reset_deassert(rst) != 0) { 448 aprint_error(": couldn't de-assert reset\n"); 449 return; 450 } 451 452 sc->sc_dev = self; 453 sc->sc_phandle = phandle; 454 sc->sc_dmat = faa->faa_dmat; 455 sc->sc_bst = faa->faa_bst; 456 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 457 aprint_error(": couldn't map registers\n"); 458 return; 459 } 460 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SCHED); 461 462 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 463 aprint_error(": failed to decode interrupt\n"); 464 return; 465 } 466 467 conf = of_compatible_lookup(phandle, compat_data)->data; 468 469 sc->sc_burst_mask = conf->burst_mask; 470 sc->sc_nchan = conf->num_channels; 471 sc->sc_widths = conf->widths; 472 sc->sc_bursts = conf->bursts; 473 sc->sc_chan = kmem_alloc(sizeof(*sc->sc_chan) * sc->sc_nchan, KM_SLEEP); 474 desclen = DESC_OFFS(sc->sc_nchan, 0); 475 sc->sc_ndesc_ch = DESC_OFFS(1, 0) / sizeof(struct sun6idma_desc); 476 477 aprint_naive("\n"); 478 aprint_normal(": DMA controller (%u channels)\n", sc->sc_nchan); 479 480 DMA_WRITE(sc, DMA_IRQ_EN_REG0_REG, 0); 481 DMA_WRITE(sc, DMA_IRQ_EN_REG1_REG, 0); 482 DMA_WRITE(sc, DMA_IRQ_PEND_REG0_REG, ~0); 483 DMA_WRITE(sc, DMA_IRQ_PEND_REG1_REG, ~0); 484 485 error = bus_dmamem_alloc(sc->sc_dmat, desclen, 0, 0, 486 sc->sc_dmasegs, 1, &nsegs, BUS_DMA_WAITOK); 487 if (error) 488 panic("bus_dmamem_alloc failed: %d", error); 489 error = bus_dmamem_map(sc->sc_dmat, sc->sc_dmasegs, nsegs, 490 desclen, (void **)&sc->sc_dmadescs, BUS_DMA_WAITOK); 491 if (error) 492 panic("bus_dmamem_map failed: %d", error); 493 error = bus_dmamap_create(sc->sc_dmat, desclen, 1, desclen, 0, 494 BUS_DMA_WAITOK, &sc->sc_dmamap); 495 if (error) 496 panic("bus_dmamap_create failed: %d", error); 497 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 498 sc->sc_dmadescs, desclen, NULL, BUS_DMA_WAITOK); 499 if (error) 500 panic("bus_dmamap_load failed: %d", error); 501 502 for (index = 0; index < sc->sc_nchan; index++) { 503 struct sun6idma_channel *ch = &sc->sc_chan[index]; 504 ch->ch_index = index; 505 ch->ch_dmadesc = (void *)((uintptr_t)sc->sc_dmadescs + DESC_OFFS(index, 0)); 506 ch->ch_callback = NULL; 507 ch->ch_callbackarg = NULL; 508 509 DMA_WRITE(sc, DMA_EN_REG(index), 0); 510 } 511 512 if (conf->autogate) 513 DMA_WRITE(sc, conf->autogate_reg, conf->autogate_mask); 514 515 sc->sc_ih = fdtbus_intr_establish_xname(phandle, 0, IPL_SCHED, 516 FDT_INTR_MPSAFE, sun6idma_intr, sc, device_xname(sc->sc_dev)); 517 if (sc->sc_ih == NULL) { 518 aprint_error_dev(sc->sc_dev, 519 "couldn't establish interrupt on %s\n", intrstr); 520 return; 521 } 522 aprint_normal_dev(sc->sc_dev, "interrupting on %s\n", intrstr); 523 524 fdtbus_register_dma_controller(self, phandle, &sun6idma_funcs); 525 } 526 527 CFATTACH_DECL_NEW(sun6i_dma, sizeof(struct sun6idma_softc), 528 sun6idma_match, sun6idma_attach, NULL, NULL); 529 530 #ifdef DDB 531 void sun6idma_dump(void); 532 533 void 534 sun6idma_dump(void) 535 { 536 struct sun6idma_softc *sc; 537 device_t dev; 538 u_int index; 539 540 dev = device_find_by_driver_unit("sun6idma", 0); 541 if (dev == NULL) 542 return; 543 sc = device_private(dev); 544 545 device_printf(dev, "DMA_IRQ_EN_REG0_REG: %08x\n", DMA_READ(sc, DMA_IRQ_EN_REG0_REG)); 546 device_printf(dev, "DMA_IRQ_EN_REG1_REG: %08x\n", DMA_READ(sc, DMA_IRQ_EN_REG1_REG)); 547 device_printf(dev, "DMA_IRQ_PEND_REG0_REG: %08x\n", DMA_READ(sc, DMA_IRQ_PEND_REG0_REG)); 548 device_printf(dev, "DMA_IRQ_PEND_REG1_REG: %08x\n", DMA_READ(sc, DMA_IRQ_PEND_REG1_REG)); 549 device_printf(dev, "DMA_STA_REG: %08x\n", DMA_READ(sc, DMA_STA_REG)); 550 551 for (index = 0; index < sc->sc_nchan; index++) { 552 struct sun6idma_channel *ch = &sc->sc_chan[index]; 553 if (ch->ch_callback == NULL) 554 continue; 555 device_printf(dev, " %2d: DMA_EN_REG: %08x\n", index, DMA_READ(sc, DMA_EN_REG(index))); 556 device_printf(dev, " %2d: DMA_PAU_REG: %08x\n", index, DMA_READ(sc, DMA_PAU_REG(index))); 557 device_printf(dev, " %2d: DMA_START_ADDR_REG: %08x\n", index, DMA_READ(sc, DMA_START_ADDR_REG(index))); 558 device_printf(dev, " %2d: DMA_CFG_REG: %08x\n", index, DMA_READ(sc, DMA_CFG_REG(index))); 559 device_printf(dev, " %2d: DMA_CUR_SRC_REG: %08x\n", index, DMA_READ(sc, DMA_CUR_SRC_REG(index))); 560 device_printf(dev, " %2d: DMA_CUR_DEST_REG: %08x\n", index, DMA_READ(sc, DMA_CUR_DEST_REG(index))); 561 device_printf(dev, " %2d: DMA_BCNT_LEFT_REG: %08x\n", index, DMA_READ(sc, DMA_BCNT_LEFT_REG(index))); 562 device_printf(dev, " %2d: DMA_PARA_REG: %08x\n", index, DMA_READ(sc, DMA_PARA_REG(index))); 563 device_printf(dev, " %2d: DMA_MODE_REG: %08x\n", index, DMA_READ(sc, DMA_MODE_REG(index))); 564 device_printf(dev, " %2d: DMA_FDESC_ADDR_REG: %08x\n", index, DMA_READ(sc, DMA_FDESC_ADDR_REG(index))); 565 device_printf(dev, " %2d: DMA_PKG_NUM_REG: %08x\n", index, DMA_READ(sc, DMA_PKG_NUM_REG(index))); 566 } 567 } 568 #endif 569
Indexes created Thu Oct 02 14:10:14 GMT 2025