sun6i_dma.c revision 1.2
1 /* $NetBSD: sun6i_dma.c,v 1.2 2017/08/06 17:13:15 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2014-2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_ddb.h" 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: sun6i_dma.c,v 1.2 2017/08/06 17:13:15 jmcneill Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/intr.h> 38 #include <sys/systm.h> 39 #include <sys/mutex.h> 40 #include <sys/bitops.h> 41 #include <sys/kmem.h> 42 43 #include <dev/fdt/fdtvar.h> 44 45 #define DMA_IRQ_EN_REG0_REG 0x0000 46 #define DMA_IRQ_EN_REG1_REG 0x0004 47 #define DMA_IRQ_EN_REG0_QUEUE_IRQ_EN(n) __BIT(n * 4 + 2) 48 #define DMA_IRQ_EN_REG0_PKG_IRQ_EN(n) __BIT(n * 4 + 1) 49 #define DMA_IRQ_EN_REG0_HLAF_IRQ_EN(n) __BIT(n * 4 + 0) 50 #define DMA_IRQ_EN_REG1_QUEUE_IRQ_EN(n) __BIT((n - 8) * 4 + 2) 51 #define DMA_IRQ_EN_REG1_PKG_IRQ_EN(n) __BIT((n - 8) * 4 + 1) 52 #define DMA_IRQ_EN_REG1_HLAF_IRQ_EN(n) __BIT((n - 8) * 4 + 0) 53 #define DMA_IRQ_PEND_REG0_REG 0x0010 54 #define DMA_IRQ_PEND_REG1_REG 0x0014 55 #define DMA_IRQ_QUEUE_MASK 0x4444444444444444ULL 56 #define DMA_IRQ_PKG_MASK 0x2222222222222222ULL 57 #define DMA_IRQ_HF_MASK 0x1111111111111111ULL 58 #define DMA_STA_REG 0x0030 59 #define DMA_EN_REG(n) (0x0100 + (n) * 0x40 + 0x00) 60 #define DMA_EN_EN __BIT(0) 61 #define DMA_PAU_REG(n) (0x0100 + (n) * 0x40 + 0x04) 62 #define DMA_PAU_PAUSE __BIT(0) 63 #define DMA_START_ADDR_REG(n) (0x0100 + (n) * 0x40 + 0x08) 64 #define DMA_CFG_REG(n) (0x0100 + (n) * 0x40 + 0x0C) 65 #define DMA_CFG_DEST_DATA_WIDTH __BITS(26,25) 66 #define DMA_CFG_DATA_WIDTH(n) ((n) >> 4) 67 #define DMA_CFG_DEST_BST_LEN __BITS(24,23) 68 #define DMA_CFG_BST_LEN(n) ((n) == 1 ? 0 : (((n) >> 3) + 1)) 69 #define DMA_CFG_DEST_ADDR_MODE __BITS(22,21) 70 #define DMA_CFG_ADDR_MODE_LINEAR 0 71 #define DMA_CFG_ADDR_MODE_IO 1 72 #define DMA_CFG_DEST_DRQ_TYPE __BITS(20,16) 73 #define DMA_CFG_DRQ_TYPE_SDRAM 1 74 #define DMA_CFG_SRC_DATA_WIDTH __BITS(10,9) 75 #define DMA_CFG_SRC_BST_LEN __BITS(8,7) 76 #define DMA_CFG_SRC_ADDR_MODE __BITS(6,5) 77 #define DMA_CFG_SRC_DRQ_TYPE __BITS(4,0) 78 #define DMA_CUR_SRC_REG(n) (0x0100 + (n) * 0x40 + 0x10) 79 #define DMA_CUR_DEST_REG(n) (0x0100 + (n) * 0x40 + 0x14) 80 #define DMA_BCNT_LEFT_REG(n) (0x0100 + (n) * 0x40 + 0x18) 81 #define DMA_PARA_REG(n) (0x0100 + (n) * 0x40 + 0x1C) 82 #define DMA_PARA_DATA_BLK_SIZE __BITS(15,8) 83 #define DMA_PARA_WAIT_CYC __BITS(7,0) 84 85 struct sun6idma_desc { 86 uint32_t dma_config; 87 uint32_t dma_srcaddr; 88 uint32_t dma_dstaddr; 89 uint32_t dma_bcnt; 90 uint32_t dma_para; 91 uint32_t dma_next; 92 #define DMA_NULL 0xfffff800 93 }; 94 95 static const struct of_compat_data compat_data[] = { 96 { "allwinner,sun6i-a31-dma", 16 }, 97 { "allwinner,sun8i-a83t-dma", 8 }, 98 { "allwinner,sun8i-h3-dma", 12 }, 99 { NULL } 100 }; 101 102 struct sun6idma_channel { 103 uint8_t ch_index; 104 void (*ch_callback)(void *); 105 void *ch_callbackarg; 106 u_int ch_portid; 107 108 bus_dma_segment_t ch_dmasegs[1]; 109 bus_dmamap_t ch_dmamap; 110 void *ch_dmadesc; 111 bus_size_t ch_dmadesclen; 112 }; 113 114 struct sun6idma_softc { 115 device_t sc_dev; 116 bus_space_tag_t sc_bst; 117 bus_space_handle_t sc_bsh; 118 bus_dma_tag_t sc_dmat; 119 int sc_phandle; 120 void *sc_ih; 121 122 kmutex_t sc_lock; 123 124 struct sun6idma_channel *sc_chan; 125 u_int sc_nchan; 126 }; 127 128 #define DMA_READ(sc, reg) \ 129 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 130 #define DMA_WRITE(sc, reg, val) \ 131 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 132 133 static void * 134 sun6idma_acquire(device_t dev, const void *data, size_t len, 135 void (*cb)(void *), void *cbarg) 136 { 137 struct sun6idma_softc *sc = device_private(dev); 138 struct sun6idma_channel *ch = NULL; 139 uint32_t irqen; 140 uint8_t index; 141 142 if (len != 4) 143 return NULL; 144 145 const u_int portid = be32dec(data); 146 if (portid > __SHIFTOUT_MASK(DMA_CFG_SRC_DRQ_TYPE)) 147 return NULL; 148 149 mutex_enter(&sc->sc_lock); 150 151 for (index = 0; index < sc->sc_nchan; index++) { 152 if (sc->sc_chan[index].ch_callback == NULL) { 153 ch = &sc->sc_chan[index]; 154 ch->ch_callback = cb; 155 ch->ch_callbackarg = cbarg; 156 ch->ch_portid = portid; 157 158 irqen = DMA_READ(sc, index < 8 ? 159 DMA_IRQ_EN_REG0_REG : 160 DMA_IRQ_EN_REG1_REG); 161 irqen |= (index < 8 ? 162 DMA_IRQ_EN_REG0_PKG_IRQ_EN(index) : 163 DMA_IRQ_EN_REG1_PKG_IRQ_EN(index)); 164 DMA_WRITE(sc, index < 8 ? 165 DMA_IRQ_EN_REG0_REG : 166 DMA_IRQ_EN_REG1_REG, irqen); 167 168 break; 169 } 170 } 171 172 mutex_exit(&sc->sc_lock); 173 174 return ch; 175 } 176 177 static void 178 sun6idma_release(device_t dev, void *priv) 179 { 180 struct sun6idma_softc *sc = device_private(dev); 181 struct sun6idma_channel *ch = priv; 182 uint32_t irqen; 183 uint8_t index = ch->ch_index; 184 185 mutex_enter(&sc->sc_lock); 186 187 irqen = DMA_READ(sc, index < 8 ? 188 DMA_IRQ_EN_REG0_REG : 189 DMA_IRQ_EN_REG1_REG); 190 irqen &= ~(index < 8 ? 191 DMA_IRQ_EN_REG0_PKG_IRQ_EN(index) : 192 DMA_IRQ_EN_REG1_PKG_IRQ_EN(index)); 193 DMA_WRITE(sc, index < 8 ? 194 DMA_IRQ_EN_REG0_REG : 195 DMA_IRQ_EN_REG1_REG, irqen); 196 197 ch->ch_callback = NULL; 198 ch->ch_callbackarg = NULL; 199 200 mutex_exit(&sc->sc_lock); 201 } 202 203 static int 204 sun6idma_transfer(device_t dev, void *priv, struct fdtbus_dma_req *req) 205 { 206 struct sun6idma_softc *sc = device_private(dev); 207 struct sun6idma_channel *ch = priv; 208 struct sun6idma_desc *desc = ch->ch_dmadesc; 209 uint32_t src, dst, len, cfg, mem_cfg, dev_cfg; 210 uint32_t mem_width, dev_width, mem_burst, dev_burst; 211 212 if (req->dreq_nsegs != 1) 213 return EINVAL; 214 215 mem_width = DMA_CFG_DATA_WIDTH(req->dreq_mem_opt.opt_bus_width); 216 dev_width = DMA_CFG_DATA_WIDTH(req->dreq_dev_opt.opt_bus_width); 217 mem_burst = DMA_CFG_BST_LEN(req->dreq_mem_opt.opt_burst_len); 218 dev_burst = DMA_CFG_BST_LEN(req->dreq_dev_opt.opt_burst_len); 219 220 mem_cfg = __SHIFTIN(mem_width, DMA_CFG_SRC_DATA_WIDTH) | 221 __SHIFTIN(mem_burst, DMA_CFG_SRC_BST_LEN) | 222 __SHIFTIN(DMA_CFG_ADDR_MODE_LINEAR, DMA_CFG_SRC_ADDR_MODE) | 223 __SHIFTIN(DMA_CFG_DRQ_TYPE_SDRAM, DMA_CFG_SRC_DRQ_TYPE); 224 dev_cfg = __SHIFTIN(dev_width, DMA_CFG_SRC_DATA_WIDTH) | 225 __SHIFTIN(dev_burst, DMA_CFG_SRC_BST_LEN) | 226 __SHIFTIN(DMA_CFG_ADDR_MODE_IO, DMA_CFG_SRC_ADDR_MODE) | 227 __SHIFTIN(ch->ch_portid, DMA_CFG_SRC_DRQ_TYPE); 228 229 if (req->dreq_dir == FDT_DMA_READ) { 230 src = req->dreq_dev_phys; 231 dst = req->dreq_segs[0].ds_addr; 232 cfg = mem_cfg << 16 | dev_cfg; 233 } else { 234 src = req->dreq_segs[0].ds_addr; 235 dst = req->dreq_dev_phys; 236 cfg = dev_cfg << 16 | mem_cfg; 237 } 238 len = req->dreq_segs[0].ds_len; 239 240 desc->dma_config = htole32(cfg); 241 desc->dma_srcaddr = htole32(src); 242 desc->dma_dstaddr = htole32(dst); 243 desc->dma_bcnt = htole32(len); 244 desc->dma_para = htole32(0); 245 desc->dma_next = htole32(DMA_NULL); 246 247 bus_dmamap_sync(sc->sc_dmat, ch->ch_dmamap, 0, ch->ch_dmadesclen, 248 BUS_DMASYNC_PREWRITE); 249 250 DMA_WRITE(sc, DMA_START_ADDR_REG(ch->ch_index), 251 ch->ch_dmamap->dm_segs[0].ds_addr); 252 DMA_WRITE(sc, DMA_EN_REG(ch->ch_index), DMA_EN_EN); 253 254 if ((DMA_READ(sc, DMA_EN_REG(ch->ch_index)) & DMA_EN_EN) == 0) { 255 aprint_error_dev(sc->sc_dev, 256 "DMA Channel %u failed to start\n", ch->ch_index); 257 return EIO; 258 } 259 260 return 0; 261 } 262 263 static void 264 sun6idma_halt(device_t dev, void *priv) 265 { 266 struct sun6idma_softc *sc = device_private(dev); 267 struct sun6idma_channel *ch = priv; 268 269 DMA_WRITE(sc, DMA_EN_REG(ch->ch_index), 0); 270 } 271 272 static const struct fdtbus_dma_controller_func sun6idma_funcs = { 273 .acquire = sun6idma_acquire, 274 .release = sun6idma_release, 275 .transfer = sun6idma_transfer, 276 .halt = sun6idma_halt 277 }; 278 279 static int 280 sun6idma_intr(void *priv) 281 { 282 struct sun6idma_softc *sc = priv; 283 uint32_t pend0, pend1, bit; 284 uint64_t pend, mask; 285 uint8_t index; 286 287 pend0 = DMA_READ(sc, DMA_IRQ_PEND_REG0_REG); 288 pend1 = DMA_READ(sc, DMA_IRQ_PEND_REG1_REG); 289 if (!pend0 && !pend1) 290 return 0; 291 292 DMA_WRITE(sc, DMA_IRQ_PEND_REG0_REG, pend0); 293 DMA_WRITE(sc, DMA_IRQ_PEND_REG1_REG, pend1); 294 295 pend = pend0 | ((uint64_t)pend1 << 32); 296 297 while ((bit = ffs64(pend & DMA_IRQ_PKG_MASK)) != 0) { 298 mask = __BIT(bit - 1); 299 pend &= ~mask; 300 index = (bit - 1) / 4; 301 302 if (sc->sc_chan[index].ch_callback == NULL) 303 continue; 304 sc->sc_chan[index].ch_callback( 305 sc->sc_chan[index].ch_callbackarg); 306 } 307 308 return 1; 309 } 310 311 static int 312 sun6idma_match(device_t parent, cfdata_t cf, void *aux) 313 { 314 struct fdt_attach_args * const faa = aux; 315 316 return of_match_compat_data(faa->faa_phandle, compat_data); 317 } 318 319 static void 320 sun6idma_attach(device_t parent, device_t self, void *aux) 321 { 322 struct sun6idma_softc * const sc = device_private(self); 323 struct fdt_attach_args * const faa = aux; 324 const int phandle = faa->faa_phandle; 325 const size_t desclen = sizeof(struct sun6idma_desc); 326 struct fdtbus_reset *rst; 327 struct clk *clk; 328 char intrstr[128]; 329 bus_addr_t addr; 330 bus_size_t size; 331 int error, nsegs; 332 u_int index; 333 334 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 335 aprint_error(": couldn't get registers\n"); 336 return; 337 } 338 339 if ((clk = fdtbus_clock_get_index(phandle, 0)) == NULL || 340 clk_enable(clk) != 0) { 341 aprint_error(": couldn't enable clock\n"); 342 return; 343 } 344 if ((rst = fdtbus_reset_get_index(phandle, 0)) == NULL || 345 fdtbus_reset_deassert(rst) != 0) { 346 aprint_error(": couldn't de-assert reset\n"); 347 return; 348 } 349 350 sc->sc_dev = self; 351 sc->sc_phandle = phandle; 352 sc->sc_dmat = faa->faa_dmat; 353 sc->sc_bst = faa->faa_bst; 354 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 355 aprint_error(": couldn't map registers\n"); 356 return; 357 } 358 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SCHED); 359 360 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 361 aprint_error(": failed to decode interrupt\n"); 362 return; 363 } 364 365 sc->sc_nchan = of_search_compatible(phandle, compat_data)->data; 366 sc->sc_chan = kmem_alloc(sizeof(*sc->sc_chan) * sc->sc_nchan, KM_SLEEP); 367 368 aprint_naive("\n"); 369 aprint_normal(": DMA controller (%u channels)\n", sc->sc_nchan); 370 371 DMA_WRITE(sc, DMA_IRQ_EN_REG0_REG, 0); 372 DMA_WRITE(sc, DMA_IRQ_EN_REG1_REG, 0); 373 DMA_WRITE(sc, DMA_IRQ_PEND_REG0_REG, ~0); 374 DMA_WRITE(sc, DMA_IRQ_PEND_REG1_REG, ~0); 375 376 for (index = 0; index < sc->sc_nchan; index++) { 377 struct sun6idma_channel *ch = &sc->sc_chan[index]; 378 ch->ch_index = index; 379 ch->ch_callback = NULL; 380 ch->ch_callbackarg = NULL; 381 ch->ch_dmadesclen = desclen; 382 383 error = bus_dmamem_alloc(sc->sc_dmat, desclen, 0, 0, 384 ch->ch_dmasegs, 1, &nsegs, BUS_DMA_WAITOK); 385 if (error) 386 panic("bus_dmamem_alloc failed: %d", error); 387 error = bus_dmamem_map(sc->sc_dmat, ch->ch_dmasegs, nsegs, 388 desclen, &ch->ch_dmadesc, BUS_DMA_WAITOK); 389 if (error) 390 panic("bus_dmamem_map failed: %d", error); 391 error = bus_dmamap_create(sc->sc_dmat, desclen, 1, desclen, 0, 392 BUS_DMA_WAITOK, &ch->ch_dmamap); 393 if (error) 394 panic("bus_dmamap_create failed: %d", error); 395 error = bus_dmamap_load(sc->sc_dmat, ch->ch_dmamap, 396 ch->ch_dmadesc, desclen, NULL, BUS_DMA_WAITOK); 397 if (error) 398 panic("bus_dmamap_load failed: %d", error); 399 400 DMA_WRITE(sc, DMA_EN_REG(index), 0); 401 } 402 403 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_SCHED, FDT_INTR_MPSAFE, 404 sun6idma_intr, sc); 405 if (sc->sc_ih == NULL) { 406 aprint_error_dev(sc->sc_dev, 407 "couldn't establish interrupt on %s\n", intrstr); 408 return; 409 } 410 aprint_normal_dev(sc->sc_dev, "interrupting on %s\n", intrstr); 411 412 fdtbus_register_dma_controller(self, phandle, &sun6idma_funcs); 413 } 414 415 CFATTACH_DECL_NEW(sun6i_dma, sizeof(struct sun6idma_softc), 416 sun6idma_match, sun6idma_attach, NULL, NULL); 417 418 #ifdef DDB 419 void sun6idma_dump(void); 420 421 void 422 sun6idma_dump(void) 423 { 424 struct sun6idma_softc *sc; 425 device_t dev; 426 u_int index; 427 428 dev = device_find_by_driver_unit("sun6idma", 0); 429 if (dev == NULL) 430 return; 431 sc = device_private(dev); 432 433 device_printf(dev, "DMA_IRQ_EN_REG0_REG: %08x\n", DMA_READ(sc, DMA_IRQ_EN_REG0_REG)); 434 device_printf(dev, "DMA_IRQ_EN_REG1_REG: %08x\n", DMA_READ(sc, DMA_IRQ_EN_REG1_REG)); 435 device_printf(dev, "DMA_IRQ_PEND_REG0_REG: %08x\n", DMA_READ(sc, DMA_IRQ_PEND_REG0_REG)); 436 device_printf(dev, "DMA_IRQ_PEND_REG1_REG: %08x\n", DMA_READ(sc, DMA_IRQ_PEND_REG1_REG)); 437 device_printf(dev, "DMA_STA_REG: %08x\n", DMA_READ(sc, DMA_STA_REG)); 438 439 for (index = 0; index < sc->sc_nchan; index++) { 440 struct sun6idma_channel *ch = &sc->sc_chan[index]; 441 if (ch->ch_callback == NULL) 442 continue; 443 device_printf(dev, " %2d: DMA_EN_REG: %08x\n", index, DMA_READ(sc, DMA_EN_REG(index))); 444 device_printf(dev, " %2d: DMA_PAU_REG: %08x\n", index, DMA_READ(sc, DMA_PAU_REG(index))); 445 device_printf(dev, " %2d: DMA_START_ADDR_REG: %08x\n", index, DMA_READ(sc, DMA_START_ADDR_REG(index))); 446 device_printf(dev, " %2d: DMA_CFG_REG: %08x\n", index, DMA_READ(sc, DMA_CFG_REG(index))); 447 device_printf(dev, " %2d: DMA_CUR_SRC_REG: %08x\n", index, DMA_READ(sc, DMA_CUR_SRC_REG(index))); 448 device_printf(dev, " %2d: DMA_CUR_DEST_REG: %08x\n", index, DMA_READ(sc, DMA_CUR_DEST_REG(index))); 449 device_printf(dev, " %2d: DMA_BCNT_LEFT_REG: %08x\n", index, DMA_READ(sc, DMA_BCNT_LEFT_REG(index))); 450 device_printf(dev, " %2d: DMA_PARA_REG: %08x\n", index, DMA_READ(sc, DMA_PARA_REG(index))); 451 } 452 } 453 #endif 454
Indexes created Fri Oct 03 02:09:57 GMT 2025