sun6i_dma.c revision 1.8
1 /* $NetBSD: sun6i_dma.c,v 1.8 2019/03/02 16:55:13 jakllsch Exp $ */ 2 3 /*- 4 * Copyright (c) 2014-2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_ddb.h" 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: sun6i_dma.c,v 1.8 2019/03/02 16:55:13 jakllsch Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/intr.h> 38 #include <sys/systm.h> 39 #include <sys/mutex.h> 40 #include <sys/bitops.h> 41 #include <sys/kmem.h> 42 43 #include <dev/fdt/fdtvar.h> 44 45 #define DMA_IRQ_EN_REG0_REG 0x0000 46 #define DMA_IRQ_EN_REG1_REG 0x0004 47 #define DMA_IRQ_EN_REG0_QUEUE_IRQ_EN(n) __BIT(n * 4 + 2) 48 #define DMA_IRQ_EN_REG0_PKG_IRQ_EN(n) __BIT(n * 4 + 1) 49 #define DMA_IRQ_EN_REG0_HLAF_IRQ_EN(n) __BIT(n * 4 + 0) 50 #define DMA_IRQ_EN_REG1_QUEUE_IRQ_EN(n) __BIT((n - 8) * 4 + 2) 51 #define DMA_IRQ_EN_REG1_PKG_IRQ_EN(n) __BIT((n - 8) * 4 + 1) 52 #define DMA_IRQ_EN_REG1_HLAF_IRQ_EN(n) __BIT((n - 8) * 4 + 0) 53 #define DMA_IRQ_PEND_REG0_REG 0x0010 54 #define DMA_IRQ_PEND_REG1_REG 0x0014 55 #define DMA_IRQ_QUEUE_MASK 0x4444444444444444ULL 56 #define DMA_IRQ_PKG_MASK 0x2222222222222222ULL 57 #define DMA_IRQ_HF_MASK 0x1111111111111111ULL 58 #define DMA_STA_REG 0x0030 59 #define DMA_EN_REG(n) (0x0100 + (n) * 0x40 + 0x00) 60 #define DMA_EN_EN __BIT(0) 61 #define DMA_PAU_REG(n) (0x0100 + (n) * 0x40 + 0x04) 62 #define DMA_PAU_PAUSE __BIT(0) 63 #define DMA_START_ADDR_REG(n) (0x0100 + (n) * 0x40 + 0x08) 64 #define DMA_CFG_REG(n) (0x0100 + (n) * 0x40 + 0x0C) 65 #define DMA_CFG_DEST_DATA_WIDTH __BITS(26,25) 66 #define DMA_CFG_DATA_WIDTH(n) ((n) >> 4) 67 #define DMA_CFG_BST_LEN(n) ((n) == 1 ? 0 : (((n) >> 3) + 1)) 68 #define DMA_CFG_DEST_ADDR_MODE __BITS(22,21) 69 #define DMA_CFG_ADDR_MODE_LINEAR 0 70 #define DMA_CFG_ADDR_MODE_IO 1 71 #define DMA_CFG_DEST_DRQ_TYPE __BITS(20,16) 72 #define DMA_CFG_DRQ_TYPE_SDRAM 1 73 #define DMA_CFG_SRC_DATA_WIDTH __BITS(10,9) 74 #define DMA_CFG_SRC_ADDR_MODE __BITS(6,5) 75 #define DMA_CFG_SRC_DRQ_TYPE __BITS(4,0) 76 #define DMA_CUR_SRC_REG(n) (0x0100 + (n) * 0x40 + 0x10) 77 #define DMA_CUR_DEST_REG(n) (0x0100 + (n) * 0x40 + 0x14) 78 #define DMA_BCNT_LEFT_REG(n) (0x0100 + (n) * 0x40 + 0x18) 79 #define DMA_PARA_REG(n) (0x0100 + (n) * 0x40 + 0x1C) 80 #define DMA_PARA_DATA_BLK_SIZE __BITS(15,8) 81 #define DMA_PARA_WAIT_CYC __BITS(7,0) 82 #define DMA_MODE_REG(n) (0x0100 + (n) * 0x40 + 0x28) 83 #define MODE_WAIT 0b0 84 #define MODE_HANDSHAKE 0b1 85 #define DMA_MODE_DST(m) __SHIFTIN((m), __BIT(3)) 86 #define DMA_MODE_SRC(m) __SHIFTIN((m), __BIT(2)) 87 #define DMA_FDESC_ADDR_REG(n) (0x0100 + (n) * 0x40 + 0x2C) 88 #define DMA_PKG_NUM_REG(n) (0x0100 + (n) * 0x40 + 0x30) 89 90 struct sun6idma_desc { 91 uint32_t dma_config; 92 uint32_t dma_srcaddr; 93 uint32_t dma_dstaddr; 94 uint32_t dma_bcnt; 95 uint32_t dma_para; 96 uint32_t dma_next; 97 #define DMA_NULL 0xfffff800 98 }; 99 100 struct sun6idma_config { 101 u_int num_channels; 102 bool autogate; 103 uint8_t bursts; 104 uint8_t widths; 105 bus_size_t autogate_reg; 106 uint32_t autogate_mask; 107 uint32_t burst_mask; 108 }; 109 110 #define IL2B(x) __BIT(ilog2(x)) 111 #define IL2B_RANGE(x, y) __BITS(ilog2(x), ilog2(y)) 112 #define WIDTHS_1_2_4 IL2B_RANGE(4, 1) 113 #define WIDTHS_1_2_4_8 IL2B_RANGE(8, 1) 114 #define BURSTS_1_8 (IL2B(8)|IL2B(1)) 115 #define BURSTS_1_4_8_16 (IL2B(16)|IL2B(8)|IL2B(4)|IL2B(1)) 116 117 static const struct sun6idma_config sun6i_a31_dma_config = { 118 .num_channels = 16, 119 .burst_mask = __BITS(8,7), 120 .bursts = BURSTS_1_8, 121 .widths = WIDTHS_1_2_4, 122 }; 123 124 static const struct sun6idma_config sun8i_a83t_dma_config = { 125 .num_channels = 8, 126 .autogate = true, 127 .autogate_reg = 0x20, 128 .autogate_mask = 0x4, 129 .burst_mask = __BITS(8,7), 130 .bursts = BURSTS_1_8, 131 .widths = WIDTHS_1_2_4, 132 }; 133 134 static const struct sun6idma_config sun8i_h3_dma_config = { 135 .num_channels = 12, 136 .autogate = true, 137 .autogate_reg = 0x28, 138 .autogate_mask = 0x4, 139 .burst_mask = __BITS(7,6), 140 .bursts = BURSTS_1_4_8_16, 141 .widths = WIDTHS_1_2_4_8, 142 }; 143 144 static const struct sun6idma_config sun50i_a64_dma_config = { 145 .num_channels = 8, 146 .autogate = true, 147 .autogate_reg = 0x28, 148 .autogate_mask = 0x4, 149 .burst_mask = __BITS(7,6), 150 .bursts = BURSTS_1_4_8_16, 151 .widths = WIDTHS_1_2_4_8, 152 }; 153 154 static const struct of_compat_data compat_data[] = { 155 { "allwinner,sun6i-a31-dma", (uintptr_t)&sun6i_a31_dma_config }, 156 { "allwinner,sun8i-a83t-dma", (uintptr_t)&sun8i_a83t_dma_config }, 157 { "allwinner,sun8i-h3-dma", (uintptr_t)&sun8i_h3_dma_config }, 158 { "allwinner,sun50i-a64-dma", (uintptr_t)&sun50i_a64_dma_config }, 159 { NULL } 160 }; 161 162 struct sun6idma_channel { 163 uint8_t ch_index; 164 void (*ch_callback)(void *); 165 void *ch_callbackarg; 166 u_int ch_portid; 167 void *ch_dmadesc; 168 }; 169 170 struct sun6idma_softc { 171 device_t sc_dev; 172 bus_space_tag_t sc_bst; 173 bus_space_handle_t sc_bsh; 174 bus_dma_tag_t sc_dmat; 175 int sc_phandle; 176 void *sc_ih; 177 178 uint32_t sc_burst_mask; 179 180 kmutex_t sc_lock; 181 182 struct sun6idma_channel *sc_chan; 183 u_int sc_nchan; 184 u_int sc_ndesc_ch; 185 uint8_t sc_widths; 186 uint8_t sc_bursts; 187 188 bus_dma_segment_t sc_dmasegs[1]; 189 bus_dmamap_t sc_dmamap; 190 void *sc_dmadescs; 191 }; 192 193 #define DMA_READ(sc, reg) \ 194 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 195 #define DMA_WRITE(sc, reg, val) \ 196 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 197 198 #define DESC_NUM ((MAXPHYS / MIN_PAGE_SIZE + 1) + 1) 199 #define DESC_LEN(n) \ 200 (sizeof(struct sun6idma_desc) * (n)) 201 #define DESC_OFFS(ch, n) \ 202 ((ch) * roundup2(DESC_LEN(DESC_NUM), COHERENCY_UNIT) + DESC_LEN(n)) 203 #define DESC_ADDR(sc, chp, n) \ 204 ((sc)->sc_dmamap->dm_segs[0].ds_addr + DESC_OFFS((chp)->ch_index, (n))) 205 206 static void * 207 sun6idma_acquire(device_t dev, const void *data, size_t len, 208 void (*cb)(void *), void *cbarg) 209 { 210 struct sun6idma_softc *sc = device_private(dev); 211 struct sun6idma_channel *ch = NULL; 212 uint32_t irqen; 213 uint8_t index; 214 215 if (len != 4) 216 return NULL; 217 218 const u_int portid = be32dec(data); 219 if (portid > __SHIFTOUT_MASK(DMA_CFG_SRC_DRQ_TYPE)) 220 return NULL; 221 222 mutex_enter(&sc->sc_lock); 223 224 for (index = 0; index < sc->sc_nchan; index++) { 225 if (sc->sc_chan[index].ch_callback == NULL) { 226 ch = &sc->sc_chan[index]; 227 ch->ch_callback = cb; 228 ch->ch_callbackarg = cbarg; 229 ch->ch_portid = portid; 230 231 irqen = DMA_READ(sc, index < 8 ? 232 DMA_IRQ_EN_REG0_REG : 233 DMA_IRQ_EN_REG1_REG); 234 irqen |= (index < 8 ? 235 DMA_IRQ_EN_REG0_PKG_IRQ_EN(index) : 236 DMA_IRQ_EN_REG1_PKG_IRQ_EN(index)); 237 DMA_WRITE(sc, index < 8 ? 238 DMA_IRQ_EN_REG0_REG : 239 DMA_IRQ_EN_REG1_REG, irqen); 240 241 break; 242 } 243 } 244 245 mutex_exit(&sc->sc_lock); 246 247 return ch; 248 } 249 250 static void 251 sun6idma_release(device_t dev, void *priv) 252 { 253 struct sun6idma_softc *sc = device_private(dev); 254 struct sun6idma_channel *ch = priv; 255 uint32_t irqen; 256 uint8_t index = ch->ch_index; 257 258 mutex_enter(&sc->sc_lock); 259 260 irqen = DMA_READ(sc, index < 8 ? 261 DMA_IRQ_EN_REG0_REG : 262 DMA_IRQ_EN_REG1_REG); 263 irqen &= ~(index < 8 ? 264 DMA_IRQ_EN_REG0_PKG_IRQ_EN(index) : 265 DMA_IRQ_EN_REG1_PKG_IRQ_EN(index)); 266 DMA_WRITE(sc, index < 8 ? 267 DMA_IRQ_EN_REG0_REG : 268 DMA_IRQ_EN_REG1_REG, irqen); 269 270 ch->ch_callback = NULL; 271 ch->ch_callbackarg = NULL; 272 273 mutex_exit(&sc->sc_lock); 274 } 275 276 static int 277 sun6idma_transfer(device_t dev, void *priv, struct fdtbus_dma_req *req) 278 { 279 struct sun6idma_softc *sc = device_private(dev); 280 struct sun6idma_channel *ch = priv; 281 struct sun6idma_desc *desc = ch->ch_dmadesc; 282 uint32_t src, dst, len, cfg, mem_cfg, dev_cfg; 283 uint32_t mem_width, dev_width, mem_burst, dev_burst; 284 285 if (req->dreq_nsegs > sc->sc_ndesc_ch) 286 return EINVAL; 287 288 if ((sc->sc_widths & 289 IL2B(req->dreq_mem_opt.opt_bus_width/NBBY)) == 0) 290 return EINVAL; 291 if ((sc->sc_widths & 292 IL2B(req->dreq_dev_opt.opt_bus_width/NBBY)) == 0) 293 return EINVAL; 294 if ((sc->sc_bursts & 295 IL2B(req->dreq_mem_opt.opt_burst_len)) == 0) 296 return EINVAL; 297 if ((sc->sc_bursts & 298 IL2B(req->dreq_dev_opt.opt_burst_len)) == 0) 299 return EINVAL; 300 301 mem_width = DMA_CFG_DATA_WIDTH(req->dreq_mem_opt.opt_bus_width); 302 dev_width = DMA_CFG_DATA_WIDTH(req->dreq_dev_opt.opt_bus_width); 303 mem_burst = DMA_CFG_BST_LEN(req->dreq_mem_opt.opt_burst_len); 304 dev_burst = DMA_CFG_BST_LEN(req->dreq_dev_opt.opt_burst_len); 305 306 mem_cfg = __SHIFTIN(mem_width, DMA_CFG_SRC_DATA_WIDTH) | 307 __SHIFTIN(mem_burst, sc->sc_burst_mask) | 308 __SHIFTIN(DMA_CFG_ADDR_MODE_LINEAR, DMA_CFG_SRC_ADDR_MODE) | 309 __SHIFTIN(DMA_CFG_DRQ_TYPE_SDRAM, DMA_CFG_SRC_DRQ_TYPE); 310 dev_cfg = __SHIFTIN(dev_width, DMA_CFG_SRC_DATA_WIDTH) | 311 __SHIFTIN(dev_burst, sc->sc_burst_mask) | 312 __SHIFTIN(DMA_CFG_ADDR_MODE_IO, DMA_CFG_SRC_ADDR_MODE) | 313 __SHIFTIN(ch->ch_portid, DMA_CFG_SRC_DRQ_TYPE); 314 315 for (size_t j = 0; j < req->dreq_nsegs; j++) { 316 if (req->dreq_dir == FDT_DMA_READ) { 317 src = req->dreq_dev_phys; 318 dst = req->dreq_segs[j].ds_addr; 319 cfg = mem_cfg << 16 | dev_cfg; 320 } else { 321 src = req->dreq_segs[j].ds_addr; 322 dst = req->dreq_dev_phys; 323 cfg = dev_cfg << 16 | mem_cfg; 324 } 325 len = req->dreq_segs[j].ds_len; 326 327 desc[j].dma_config = htole32(cfg); 328 desc[j].dma_srcaddr = htole32(src); 329 desc[j].dma_dstaddr = htole32(dst); 330 desc[j].dma_bcnt = htole32(len); 331 desc[j].dma_para = htole32(0); 332 if (j < req->dreq_nsegs - 1) 333 desc[j].dma_next = htole32(DESC_ADDR(sc, ch, j + 1)); 334 else 335 desc[j].dma_next = htole32(DMA_NULL); 336 } 337 338 #if maybenever 339 DMA_WRITE(sc, DMA_MODE_REG(ch->ch_index), 340 DMA_MODE_DST(MODE_HANDSHAKE)|DMA_MODE_SRC(MODE_HANDSHAKE)); 341 #endif 342 343 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, DESC_OFFS(ch->ch_index, 0), 344 DESC_LEN(req->dreq_nsegs), BUS_DMASYNC_PREWRITE); 345 346 DMA_WRITE(sc, DMA_START_ADDR_REG(ch->ch_index), 347 DESC_ADDR(sc, ch, 0)); 348 DMA_WRITE(sc, DMA_EN_REG(ch->ch_index), DMA_EN_EN); 349 350 if ((DMA_READ(sc, DMA_EN_REG(ch->ch_index)) & DMA_EN_EN) == 0) { 351 aprint_error_dev(sc->sc_dev, 352 "DMA Channel %u failed to start\n", ch->ch_index); 353 return EIO; 354 } 355 356 return 0; 357 } 358 359 static void 360 sun6idma_halt(device_t dev, void *priv) 361 { 362 struct sun6idma_softc *sc = device_private(dev); 363 struct sun6idma_channel *ch = priv; 364 365 DMA_WRITE(sc, DMA_EN_REG(ch->ch_index), 0); 366 } 367 368 static const struct fdtbus_dma_controller_func sun6idma_funcs = { 369 .acquire = sun6idma_acquire, 370 .release = sun6idma_release, 371 .transfer = sun6idma_transfer, 372 .halt = sun6idma_halt 373 }; 374 375 static int 376 sun6idma_intr(void *priv) 377 { 378 struct sun6idma_softc *sc = priv; 379 uint32_t pend0, pend1, bit; 380 uint64_t pend, mask; 381 uint8_t index; 382 383 pend0 = DMA_READ(sc, DMA_IRQ_PEND_REG0_REG); 384 pend1 = DMA_READ(sc, DMA_IRQ_PEND_REG1_REG); 385 if (!pend0 && !pend1) 386 return 0; 387 388 DMA_WRITE(sc, DMA_IRQ_PEND_REG0_REG, pend0); 389 DMA_WRITE(sc, DMA_IRQ_PEND_REG1_REG, pend1); 390 391 pend = pend0 | ((uint64_t)pend1 << 32); 392 393 while ((bit = ffs64(pend & DMA_IRQ_PKG_MASK)) != 0) { 394 mask = __BIT(bit - 1); 395 pend &= ~mask; 396 index = (bit - 1) / 4; 397 398 if (sc->sc_chan[index].ch_callback == NULL) 399 continue; 400 sc->sc_chan[index].ch_callback( 401 sc->sc_chan[index].ch_callbackarg); 402 } 403 404 return 1; 405 } 406 407 static int 408 sun6idma_match(device_t parent, cfdata_t cf, void *aux) 409 { 410 struct fdt_attach_args * const faa = aux; 411 412 return of_match_compat_data(faa->faa_phandle, compat_data); 413 } 414 415 static void 416 sun6idma_attach(device_t parent, device_t self, void *aux) 417 { 418 struct sun6idma_softc * const sc = device_private(self); 419 struct fdt_attach_args * const faa = aux; 420 const int phandle = faa->faa_phandle; 421 size_t desclen; 422 const struct sun6idma_config *conf; 423 struct fdtbus_reset *rst; 424 struct clk *clk; 425 char intrstr[128]; 426 bus_addr_t addr; 427 bus_size_t size; 428 int error, nsegs; 429 u_int index; 430 431 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 432 aprint_error(": couldn't get registers\n"); 433 return; 434 } 435 436 if ((clk = fdtbus_clock_get_index(phandle, 0)) == NULL || 437 clk_enable(clk) != 0) { 438 aprint_error(": couldn't enable clock\n"); 439 return; 440 } 441 if ((rst = fdtbus_reset_get_index(phandle, 0)) == NULL || 442 fdtbus_reset_deassert(rst) != 0) { 443 aprint_error(": couldn't de-assert reset\n"); 444 return; 445 } 446 447 sc->sc_dev = self; 448 sc->sc_phandle = phandle; 449 sc->sc_dmat = faa->faa_dmat; 450 sc->sc_bst = faa->faa_bst; 451 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 452 aprint_error(": couldn't map registers\n"); 453 return; 454 } 455 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SCHED); 456 457 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 458 aprint_error(": failed to decode interrupt\n"); 459 return; 460 } 461 462 conf = (void *)of_search_compatible(phandle, compat_data)->data; 463 464 sc->sc_burst_mask = conf->burst_mask; 465 sc->sc_nchan = conf->num_channels; 466 sc->sc_widths = conf->widths; 467 sc->sc_bursts = conf->bursts; 468 sc->sc_chan = kmem_alloc(sizeof(*sc->sc_chan) * sc->sc_nchan, KM_SLEEP); 469 desclen = DESC_OFFS(sc->sc_nchan, 0); 470 sc->sc_ndesc_ch = DESC_OFFS(1, 0) / sizeof(struct sun6idma_desc); 471 472 aprint_naive("\n"); 473 aprint_normal(": DMA controller (%u channels)\n", sc->sc_nchan); 474 475 DMA_WRITE(sc, DMA_IRQ_EN_REG0_REG, 0); 476 DMA_WRITE(sc, DMA_IRQ_EN_REG1_REG, 0); 477 DMA_WRITE(sc, DMA_IRQ_PEND_REG0_REG, ~0); 478 DMA_WRITE(sc, DMA_IRQ_PEND_REG1_REG, ~0); 479 480 error = bus_dmamem_alloc(sc->sc_dmat, desclen, 0, 0, 481 sc->sc_dmasegs, 1, &nsegs, BUS_DMA_WAITOK); 482 if (error) 483 panic("bus_dmamem_alloc failed: %d", error); 484 error = bus_dmamem_map(sc->sc_dmat, sc->sc_dmasegs, nsegs, 485 desclen, (void **)&sc->sc_dmadescs, BUS_DMA_WAITOK); 486 if (error) 487 panic("bus_dmamem_map failed: %d", error); 488 error = bus_dmamap_create(sc->sc_dmat, desclen, 1, desclen, 0, 489 BUS_DMA_WAITOK, &sc->sc_dmamap); 490 if (error) 491 panic("bus_dmamap_create failed: %d", error); 492 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 493 sc->sc_dmadescs, desclen, NULL, BUS_DMA_WAITOK); 494 if (error) 495 panic("bus_dmamap_load failed: %d", error); 496 497 for (index = 0; index < sc->sc_nchan; index++) { 498 struct sun6idma_channel *ch = &sc->sc_chan[index]; 499 ch->ch_index = index; 500 ch->ch_dmadesc = (void *)((uintptr_t)sc->sc_dmadescs + DESC_OFFS(index, 0)); 501 ch->ch_callback = NULL; 502 ch->ch_callbackarg = NULL; 503 504 DMA_WRITE(sc, DMA_EN_REG(index), 0); 505 } 506 507 if (conf->autogate) 508 DMA_WRITE(sc, conf->autogate_reg, conf->autogate_mask); 509 510 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_SCHED, FDT_INTR_MPSAFE, 511 sun6idma_intr, sc); 512 if (sc->sc_ih == NULL) { 513 aprint_error_dev(sc->sc_dev, 514 "couldn't establish interrupt on %s\n", intrstr); 515 return; 516 } 517 aprint_normal_dev(sc->sc_dev, "interrupting on %s\n", intrstr); 518 519 fdtbus_register_dma_controller(self, phandle, &sun6idma_funcs); 520 } 521 522 CFATTACH_DECL_NEW(sun6i_dma, sizeof(struct sun6idma_softc), 523 sun6idma_match, sun6idma_attach, NULL, NULL); 524 525 #ifdef DDB 526 void sun6idma_dump(void); 527 528 void 529 sun6idma_dump(void) 530 { 531 struct sun6idma_softc *sc; 532 device_t dev; 533 u_int index; 534 535 dev = device_find_by_driver_unit("sun6idma", 0); 536 if (dev == NULL) 537 return; 538 sc = device_private(dev); 539 540 device_printf(dev, "DMA_IRQ_EN_REG0_REG: %08x\n", DMA_READ(sc, DMA_IRQ_EN_REG0_REG)); 541 device_printf(dev, "DMA_IRQ_EN_REG1_REG: %08x\n", DMA_READ(sc, DMA_IRQ_EN_REG1_REG)); 542 device_printf(dev, "DMA_IRQ_PEND_REG0_REG: %08x\n", DMA_READ(sc, DMA_IRQ_PEND_REG0_REG)); 543 device_printf(dev, "DMA_IRQ_PEND_REG1_REG: %08x\n", DMA_READ(sc, DMA_IRQ_PEND_REG1_REG)); 544 device_printf(dev, "DMA_STA_REG: %08x\n", DMA_READ(sc, DMA_STA_REG)); 545 546 for (index = 0; index < sc->sc_nchan; index++) { 547 struct sun6idma_channel *ch = &sc->sc_chan[index]; 548 if (ch->ch_callback == NULL) 549 continue; 550 device_printf(dev, " %2d: DMA_EN_REG: %08x\n", index, DMA_READ(sc, DMA_EN_REG(index))); 551 device_printf(dev, " %2d: DMA_PAU_REG: %08x\n", index, DMA_READ(sc, DMA_PAU_REG(index))); 552 device_printf(dev, " %2d: DMA_START_ADDR_REG: %08x\n", index, DMA_READ(sc, DMA_START_ADDR_REG(index))); 553 device_printf(dev, " %2d: DMA_CFG_REG: %08x\n", index, DMA_READ(sc, DMA_CFG_REG(index))); 554 device_printf(dev, " %2d: DMA_CUR_SRC_REG: %08x\n", index, DMA_READ(sc, DMA_CUR_SRC_REG(index))); 555 device_printf(dev, " %2d: DMA_CUR_DEST_REG: %08x\n", index, DMA_READ(sc, DMA_CUR_DEST_REG(index))); 556 device_printf(dev, " %2d: DMA_BCNT_LEFT_REG: %08x\n", index, DMA_READ(sc, DMA_BCNT_LEFT_REG(index))); 557 device_printf(dev, " %2d: DMA_PARA_REG: %08x\n", index, DMA_READ(sc, DMA_PARA_REG(index))); 558 device_printf(dev, " %2d: DMA_MODE_REG: %08x\n", index, DMA_READ(sc, DMA_MODE_REG(index))); 559 device_printf(dev, " %2d: DMA_FDESC_ADDR_REG: %08x\n", index, DMA_READ(sc, DMA_FDESC_ADDR_REG(index))); 560 device_printf(dev, " %2d: DMA_PKG_NUM_REG: %08x\n", index, DMA_READ(sc, DMA_PKG_NUM_REG(index))); 561 } 562 } 563 #endif 564
Indexes created Thu Oct 02 14:10:14 GMT 2025