sun6i_spi.c revision 1.1
1 /* $NetBSD: sun6i_spi.c,v 1.1 2018/01/31 16:24:11 jakllsch Exp $ */ 2 3 /* 4 * Copyright (c) 2018 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: sun6i_spi.c,v 1.1 2018/01/31 16:24:11 jakllsch Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/device.h> 34 #include <sys/systm.h> 35 #include <sys/mutex.h> 36 #include <sys/bus.h> 37 #include <sys/intr.h> 38 #include <sys/kernel.h> 39 40 #include <sys/bitops.h> 41 #include <dev/spi/spivar.h> 42 43 #include <arm/sunxi/sun6i_spireg.h> 44 45 #include <dev/fdt/fdtvar.h> 46 47 #include <arm/fdt/arm_fdtvar.h> 48 49 #define SPI_IER_DEFAULT (SPI_IER_TC_INT_EN | SPI_IER_TF_UDR_INT_EN | \ 50 SPI_IER_TF_OVF_INT_EN | SPI_IER_RF_UDR_INT_EN | SPI_IER_RF_OVF_INT_EN) 51 52 struct sun6ispi_softc { 53 device_t sc_dev; 54 bus_space_tag_t sc_iot; 55 bus_space_handle_t sc_ioh; 56 void *sc_intrh; 57 struct spi_controller sc_spi; 58 SIMPLEQ_HEAD(,spi_transfer) sc_q; 59 struct spi_transfer *sc_transfer; 60 struct spi_chunk *sc_wchunk; 61 struct spi_chunk *sc_rchunk; 62 uint32_t sc_TCR; 63 u_int sc_modclkrate; 64 volatile bool sc_running; 65 }; 66 67 static int sun6ispi_match(device_t, cfdata_t, void *); 68 static void sun6ispi_attach(device_t, device_t, void *); 69 70 static int sun6ispi_configure(void *, int, int, int); 71 static int sun6ispi_transfer(void *, struct spi_transfer *); 72 73 static void sun6ispi_start(struct sun6ispi_softc * const); 74 static int sun6ispi_intr(void *); 75 76 static void sun6ispi_send(struct sun6ispi_softc * const); 77 static void sun6ispi_recv(struct sun6ispi_softc * const); 78 79 CFATTACH_DECL_NEW(sun6i_spi, sizeof(struct sun6ispi_softc), 80 sun6ispi_match, sun6ispi_attach, NULL, NULL); 81 82 static int 83 sun6ispi_match(device_t parent, cfdata_t cf, void *aux) 84 { 85 const char * const compatible[] = { 86 "allwinner,sun8i-h3-spi", 87 NULL 88 }; 89 struct fdt_attach_args * const faa = aux; 90 91 return of_match_compatible(faa->faa_phandle, compatible); 92 } 93 94 static void 95 sun6ispi_attach(device_t parent, device_t self, void *aux) 96 { 97 struct sun6ispi_softc * const sc = device_private(self); 98 struct fdt_attach_args * const faa = aux; 99 struct spibus_attach_args sba; 100 struct fdtbus_reset *rst; 101 struct clk *clk, *modclk; 102 uint32_t gcr, isr; 103 char intrstr[128]; 104 105 aprint_naive("\n"); 106 aprint_normal(": SPI\n"); 107 108 sc->sc_dev = self; 109 sc->sc_iot = faa->faa_bst; 110 SIMPLEQ_INIT(&sc->sc_q); 111 112 const int phandle = faa->faa_phandle; 113 bus_addr_t addr; 114 bus_size_t size; 115 116 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 117 aprint_error_dev(sc->sc_dev, "missing 'reg' property\n"); 118 return; 119 } 120 121 if (bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh) != 0) { 122 aprint_error_dev(sc->sc_dev, "unable to map device\n"); 123 return; 124 } 125 126 if ((clk = fdtbus_clock_get_index(phandle, 0)) != NULL) { 127 if (clk_enable(clk) != 0) { 128 aprint_error_dev(sc->sc_dev, "couldn't enable clock\n"); 129 return; 130 } 131 device_printf(self, "%s ahb @ %uHz\n", __func__, clk_get_rate(clk)); 132 } 133 134 if ((modclk = fdtbus_clock_get(phandle, "mod")) != NULL) { 135 /* 200MHz max on H3,H5 */ 136 if (clk_set_rate(modclk, 200000000) != 0) { 137 aprint_error_dev(sc->sc_dev, "couldn't configure module clock\n"); 138 return; 139 } 140 if (clk_enable(modclk) != 0) { 141 aprint_error_dev(sc->sc_dev, "couldn't enable module clock\n"); 142 return; 143 } 144 sc->sc_modclkrate = clk_get_rate(modclk); 145 device_printf(self, "%s %uHz\n", __func__, sc->sc_modclkrate); 146 } 147 148 if ((rst = fdtbus_reset_get_index(phandle, 0)) != NULL) 149 if (fdtbus_reset_deassert(rst) != 0) { 150 aprint_error(": couldn't de-assert reset\n"); 151 return; 152 } 153 154 isr = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SPI_INT_STA); 155 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SPI_INT_STA, isr); 156 157 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 158 aprint_error(": failed to decode interrupt\n"); 159 return; 160 } 161 162 sc->sc_intrh = fdtbus_intr_establish(phandle, 0, IPL_VM, 0, 163 sun6ispi_intr, sc); 164 if (sc->sc_intrh == NULL) { 165 aprint_error_dev(sc->sc_dev, "unable to establish interrupt\n"); 166 return; 167 } 168 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 169 170 gcr = SPI_GCR_SRST; 171 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SPI_GCR, gcr); 172 do { 173 } while ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, SPI_GCR) & SPI_GCR_SRST) != 0); 174 gcr = SPI_GCR_TP_EN | SPI_GCR_MODE | SPI_GCR_EN; 175 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SPI_GCR, gcr); 176 177 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SPI_IER, SPI_IER_DEFAULT); 178 179 sc->sc_spi.sct_cookie = sc; 180 sc->sc_spi.sct_configure = sun6ispi_configure; 181 sc->sc_spi.sct_transfer = sun6ispi_transfer; 182 sc->sc_spi.sct_nslaves = 4; 183 184 sba.sba_controller = &sc->sc_spi; 185 186 (void) config_found_ia(self, "spibus", &sba, spibus_print); 187 } 188 189 static int 190 sun6ispi_configure(void *cookie, int slave, int mode, int speed) 191 { 192 struct sun6ispi_softc * const sc = cookie; 193 uint32_t tcr, cctl; 194 195 #if 0 196 device_printf(sc->sc_dev, "%s slave %d mode %d speed %d\n", __func__, slave, mode, speed); 197 198 if (speed > 200000) 199 speed = 200000; 200 #endif 201 202 tcr = SPI_TCR_SS_LEVEL | SPI_TCR_SPOL; 203 204 if (slave > 3) 205 return EINVAL; 206 207 if (speed <= 0) 208 return EINVAL; 209 210 switch (mode) { 211 case SPI_MODE_0: 212 tcr |= 0; 213 break; 214 case SPI_MODE_1: 215 tcr |= SPI_TCR_CPHA; 216 break; 217 case SPI_MODE_2: 218 tcr |= SPI_TCR_CPOL; 219 break; 220 case SPI_MODE_3: 221 tcr |= SPI_TCR_CPHA|SPI_TCR_CPOL; 222 break; 223 default: 224 return EINVAL; 225 } 226 227 sc->sc_TCR = tcr; 228 229 if (speed < 3000 || speed > 200000000) 230 return EINVAL; 231 232 if (speed > sc->sc_modclkrate / 2 || speed < sc->sc_modclkrate / 512) { 233 for (cctl = 0; cctl <= __SHIFTOUT_MASK(SPI_CCTL_CDR1); cctl++) { 234 if ((sc->sc_modclkrate / (1<<cctl)) <= speed) 235 goto cdr1_found; 236 } 237 return EINVAL; 238 cdr1_found: 239 cctl = __SHIFTIN(cctl, SPI_CCTL_CDR1); 240 } else { 241 cctl = howmany(sc->sc_modclkrate, 2 * speed) - 1; 242 cctl = SPI_CCTL_DRS|__SHIFTIN(cctl, SPI_CCTL_CDR2); 243 } 244 245 device_printf(sc->sc_dev, "%s CCTL 0x%08x\n", __func__, cctl); 246 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SPI_CCTL, cctl); 247 248 return 0; 249 } 250 251 static int 252 sun6ispi_transfer(void *cookie, struct spi_transfer *st) 253 { 254 struct sun6ispi_softc * const sc = cookie; 255 int s; 256 257 s = splbio(); 258 spi_transq_enqueue(&sc->sc_q, st); 259 if (sc->sc_running == false) { 260 sun6ispi_start(sc); 261 } 262 splx(s); 263 return 0; 264 } 265 266 static size_t 267 chunks_total_count(struct spi_transfer * st) 268 { 269 struct spi_chunk *chunk = st->st_chunks; 270 size_t len = 0; 271 272 do { 273 len += chunk->chunk_count; 274 } while ((chunk = chunk->chunk_next) != NULL); 275 276 return len; 277 } 278 279 static void 280 sun6ispi_start(struct sun6ispi_softc * const sc) 281 { 282 struct spi_transfer *st; 283 uint32_t isr, tcr; 284 size_t ctc; 285 286 //device_printf(sc->sc_dev, "%s\n", __func__); 287 while ((st = spi_transq_first(&sc->sc_q)) != NULL) { 288 289 spi_transq_dequeue(&sc->sc_q); 290 291 KASSERT(sc->sc_transfer == NULL); 292 sc->sc_transfer = st; 293 sc->sc_rchunk = sc->sc_wchunk = st->st_chunks; 294 sc->sc_running = true; 295 296 isr = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SPI_INT_STA); 297 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SPI_INT_STA, isr); 298 299 //printf("%s fcr 0x%08x\n", __func__, bus_space_read_4(sc->sc_iot, sc->sc_ioh, SPI_FCR)); 300 301 ctc = chunks_total_count(st); 302 //printf("%s total count %zu\n", __func__, ctc); 303 304 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SPI_BC, __SHIFTIN(ctc, SPI_BC_MBC)); 305 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SPI_TC, __SHIFTIN(ctc, SPI_TC_MWTC)); 306 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SPI_BCC, __SHIFTIN(ctc, SPI_BCC_STC)); 307 308 KASSERT(st->st_slave <= 3); 309 tcr = sc->sc_TCR | __SHIFTIN(st->st_slave, SPI_TCR_SS_SEL); 310 311 //device_printf(sc->sc_dev, "%s before TCR write\n", __func__); 312 //bus_space_write_4(sc->sc_iot, sc->sc_ioh, SPI_TCR, tcr); 313 314 sun6ispi_send(sc); 315 316 const uint32_t ier = SPI_IER_DEFAULT | SPI_IER_RF_RDY_INT_EN | SPI_IER_TX_ERQ_INT_EN; 317 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SPI_IER, ier); 318 319 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SPI_TCR, tcr|SPI_TCR_XCH); 320 //device_printf(sc->sc_dev, "%s after TCR write\n", __func__); 321 322 if (!cold) 323 return; 324 325 //device_printf(sc->sc_dev, "%s cold\n", __func__); 326 327 int s = splbio(); 328 for (;;) { 329 sun6ispi_intr(sc); 330 if (ISSET(st->st_flags, SPI_F_DONE)) 331 break; 332 } 333 splx(s); 334 } 335 336 sc->sc_running = false; 337 // device_printf(sc->sc_dev, "%s finishes\n", __func__); 338 } 339 340 static void 341 sun6ispi_send(struct sun6ispi_softc * const sc) 342 { 343 uint8_t fd; 344 uint32_t fsr; 345 struct spi_chunk *chunk; 346 347 //device_printf(sc->sc_dev, "%s\n", __func__); 348 349 while ((chunk = sc->sc_wchunk) != NULL) { 350 while (chunk->chunk_wresid) { 351 fsr = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SPI_FSR); 352 if (__SHIFTOUT(fsr, SPI_FSR_TF_CNT) >= 64) { 353 //printf("%s fsr 0x%08x\n", __func__, fsr); 354 return; 355 } 356 if (chunk->chunk_wptr) { 357 fd = *chunk->chunk_wptr++; 358 } else { 359 fd = '\0'; 360 } 361 //printf("%s fd %02x\n", __func__, fd); 362 bus_space_write_1(sc->sc_iot, sc->sc_ioh, SPI_TXD, fd); 363 chunk->chunk_wresid--; 364 } 365 sc->sc_wchunk = sc->sc_wchunk->chunk_next; 366 } 367 } 368 369 static void 370 sun6ispi_recv(struct sun6ispi_softc * const sc) 371 { 372 uint8_t fd; 373 uint32_t fsr; 374 struct spi_chunk *chunk; 375 376 //device_printf(sc->sc_dev, "%s\n", __func__); 377 378 while ((chunk = sc->sc_rchunk) != NULL) { 379 while (chunk->chunk_rresid) { 380 fsr = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SPI_FSR); 381 if (__SHIFTOUT(fsr, SPI_FSR_RF_CNT) == 0) { 382 //printf("%s fsr 0x%08x\n", __func__, fsr); 383 return; 384 } 385 fd = bus_space_read_1(sc->sc_iot, sc->sc_ioh, SPI_RXD); 386 //printf("%s fd %02x\n", __func__, fd); 387 if (chunk->chunk_rptr) { 388 *chunk->chunk_rptr++ = fd; 389 } 390 chunk->chunk_rresid--; 391 } 392 sc->sc_rchunk = sc->sc_rchunk->chunk_next; 393 } 394 } 395 396 static int 397 sun6ispi_intr(void *cookie) 398 { 399 struct sun6ispi_softc * const sc = cookie; 400 struct spi_transfer *st; 401 uint32_t isr; 402 403 isr = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SPI_INT_STA); 404 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SPI_INT_STA, isr); 405 //device_printf(sc->sc_dev, "%s ISR 0x%08x\n", __func__, isr); 406 407 if (ISSET(isr, SPI_ISR_RX_RDY)) { 408 sun6ispi_recv(sc); 409 sun6ispi_send(sc); 410 } 411 412 if (ISSET(isr, SPI_ISR_TC)) { 413 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SPI_IER, SPI_IER_DEFAULT); 414 415 sc->sc_rchunk = sc->sc_wchunk = NULL; 416 st = sc->sc_transfer; 417 sc->sc_transfer = NULL; 418 KASSERT(st != NULL); 419 spi_done(st, 0); 420 sc->sc_running = false; 421 } 422 423 return isr; 424 } 425
Indexes created Tue Sep 23 02:09:52 GMT 2025