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sun6i_spi.c revision 1.2 
      1 /*	$NetBSD: sun6i_spi.c,v 1.2 2018/02/01 14:50:36 jakllsch Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 2018 Jonathan A. Kollasch
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
     17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     18  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     19  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
     20  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
     21  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
     22  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
     23  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
     24  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
     25  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
     26  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     27  */
     28 
     29 #include <sys/cdefs.h>
     30 __KERNEL_RCSID(0, "$NetBSD: sun6i_spi.c,v 1.2 2018/02/01 14:50:36 jakllsch Exp $");
     31 
     32 #include <sys/param.h>
     33 #include <sys/device.h>
     34 #include <sys/systm.h>
     35 #include <sys/mutex.h>
     36 #include <sys/bus.h>
     37 #include <sys/intr.h>
     38 #include <sys/kernel.h>
     39 
     40 #include <sys/bitops.h>
     41 #include <dev/spi/spivar.h>
     42 
     43 #include <arm/sunxi/sun6i_spireg.h>
     44 
     45 #include <dev/fdt/fdtvar.h>
     46 
     47 #include <arm/fdt/arm_fdtvar.h>
     48 
     49 #define SPI_IER_DEFAULT (SPI_IER_TC_INT_EN | SPI_IER_TF_UDR_INT_EN | \
     50 	SPI_IER_TF_OVF_INT_EN | SPI_IER_RF_UDR_INT_EN | SPI_IER_RF_OVF_INT_EN)
     51 
     52 struct sun6ispi_softc {
     53 	device_t		sc_dev;
     54 	bus_space_tag_t		sc_iot;
     55 	bus_space_handle_t	sc_ioh;
     56 	void			*sc_intrh;
     57 	struct spi_controller	sc_spi;
     58 	SIMPLEQ_HEAD(,spi_transfer) sc_q;
     59 	struct spi_transfer	*sc_transfer;
     60 	struct spi_chunk	*sc_wchunk;
     61 	struct spi_chunk	*sc_rchunk;
     62 	uint32_t		sc_TCR;
     63 	u_int			sc_modclkrate;
     64 	volatile bool		sc_running;
     65 };
     66 
     67 static int sun6ispi_match(device_t, cfdata_t, void *);
     68 static void sun6ispi_attach(device_t, device_t, void *);
     69 
     70 static int sun6ispi_configure(void *, int, int, int);
     71 static int sun6ispi_transfer(void *, struct spi_transfer *);
     72 
     73 static void sun6ispi_start(struct sun6ispi_softc * const);
     74 static int sun6ispi_intr(void *);
     75 
     76 static void sun6ispi_send(struct sun6ispi_softc * const);
     77 static void sun6ispi_recv(struct sun6ispi_softc * const);
     78 
     79 CFATTACH_DECL_NEW(sun6i_spi, sizeof(struct sun6ispi_softc),
     80     sun6ispi_match, sun6ispi_attach, NULL, NULL);
     81 
     82 static int
     83 sun6ispi_match(device_t parent, cfdata_t cf, void *aux)
     84 {
     85 	const char * const compatible[] = {
     86 		"allwinner,sun8i-h3-spi",
     87 		NULL
     88 	};
     89 	struct fdt_attach_args * const faa = aux;
     90 
     91 	return of_match_compatible(faa->faa_phandle, compatible);
     92 }
     93 
     94 static void
     95 sun6ispi_attach(device_t parent, device_t self, void *aux)
     96 {
     97 	struct sun6ispi_softc * const sc = device_private(self);
     98 	struct fdt_attach_args * const faa = aux;
     99 	struct spibus_attach_args sba;
    100 	struct fdtbus_reset *rst;
    101 	struct clk *clk, *modclk;
    102 	uint32_t gcr, isr;
    103 	char intrstr[128];
    104 
    105 	aprint_naive("\n");
    106 	aprint_normal(": SPI\n");
    107 
    108 	sc->sc_dev = self;
    109 	sc->sc_iot = faa->faa_bst;
    110 	SIMPLEQ_INIT(&sc->sc_q);
    111 
    112 	const int phandle = faa->faa_phandle;
    113 	bus_addr_t addr;
    114 	bus_size_t size;
    115 
    116 	if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
    117 		aprint_error_dev(sc->sc_dev, "missing 'reg' property\n");
    118 		return;
    119 	}
    120 
    121 	if (bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh) != 0) {
    122 		aprint_error_dev(sc->sc_dev, "unable to map device\n");
    123 		return;
    124 	}
    125 
    126 	if ((clk = fdtbus_clock_get_index(phandle, 0)) != NULL) {
    127 		if (clk_enable(clk) != 0) {
    128 			aprint_error_dev(sc->sc_dev, "couldn't enable clock\n");
    129 			return;
    130 		}
    131 		device_printf(self, "%s ahb @ %uHz\n", __func__, clk_get_rate(clk));
    132 	}
    133 
    134 	if ((modclk = fdtbus_clock_get(phandle, "mod")) != NULL) {
    135 		/* 200MHz max on H3,H5 */
    136 		if (clk_set_rate(modclk, 200000000) != 0) {
    137 			aprint_error_dev(sc->sc_dev, "couldn't configure module clock\n");
    138 			return;
    139 		}
    140 		if (clk_enable(modclk) != 0) {
    141 			aprint_error_dev(sc->sc_dev, "couldn't enable module clock\n");
    142 			return;
    143 		}
    144 		sc->sc_modclkrate = clk_get_rate(modclk);
    145 		device_printf(self, "%s %uHz\n", __func__, sc->sc_modclkrate);
    146 	}
    147 
    148 	if ((rst = fdtbus_reset_get_index(phandle, 0)) != NULL)
    149 		if (fdtbus_reset_deassert(rst) != 0) {
    150 			aprint_error(": couldn't de-assert reset\n");
    151 			return;
    152 		}
    153 
    154 	isr = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SPI_INT_STA);
    155 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SPI_INT_STA, isr);
    156 
    157 	if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) {
    158 		aprint_error(": failed to decode interrupt\n");
    159 		return;
    160 	}
    161 
    162 	sc->sc_intrh = fdtbus_intr_establish(phandle, 0, IPL_VM, 0,
    163 	    sun6ispi_intr, sc);
    164 	if (sc->sc_intrh == NULL) {
    165 		aprint_error_dev(sc->sc_dev, "unable to establish interrupt\n");
    166 		return;
    167 	}
    168 	aprint_normal_dev(self, "interrupting on %s\n", intrstr);
    169 
    170 	gcr = SPI_GCR_SRST;
    171 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SPI_GCR, gcr);
    172 	for (u_int i = 0; ; i++) {
    173 		if (i >= 1000000) {
    174 			aprint_error_dev(self, "reset timeout\n");
    175 			return;
    176 		}
    177 		gcr = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SPI_GCR);
    178 		if ((gcr & SPI_GCR_SRST) == 0)
    179 			break;
    180 		else
    181 			DELAY(1);
    182 	}
    183 	gcr = SPI_GCR_TP_EN | SPI_GCR_MODE | SPI_GCR_EN;
    184 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SPI_GCR, gcr);
    185 
    186 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SPI_IER, SPI_IER_DEFAULT);
    187 
    188 	sc->sc_spi.sct_cookie = sc;
    189 	sc->sc_spi.sct_configure = sun6ispi_configure;
    190 	sc->sc_spi.sct_transfer = sun6ispi_transfer;
    191 	sc->sc_spi.sct_nslaves = 4;
    192 
    193 	sba.sba_controller = &sc->sc_spi;
    194 
    195 	(void) config_found_ia(self, "spibus", &sba, spibus_print);
    196 }
    197 
    198 static int
    199 sun6ispi_configure(void *cookie, int slave, int mode, int speed)
    200 {
    201 	struct sun6ispi_softc * const sc = cookie;
    202 	uint32_t tcr, cctl;
    203 
    204 #if 0
    205 	device_printf(sc->sc_dev, "%s slave %d mode %d speed %d\n", __func__, slave, mode, speed);
    206 
    207 	if (speed > 200000)
    208 		speed = 200000;
    209 #endif
    210 
    211 	tcr = SPI_TCR_SS_LEVEL | SPI_TCR_SPOL;
    212 
    213 	if (slave > 3)
    214 		return EINVAL;
    215 
    216 	if (speed <= 0)
    217 		return EINVAL;
    218 
    219 	switch (mode) {
    220 	case SPI_MODE_0:
    221 		tcr |= 0;
    222 		break;
    223 	case SPI_MODE_1:
    224 		tcr |= SPI_TCR_CPHA;
    225 		break;
    226 	case SPI_MODE_2:
    227 		tcr |= SPI_TCR_CPOL;
    228 		break;
    229 	case SPI_MODE_3:
    230 		tcr |= SPI_TCR_CPHA|SPI_TCR_CPOL;
    231 		break;
    232 	default:
    233 		return EINVAL;
    234 	}
    235 
    236 	sc->sc_TCR = tcr;
    237 
    238 	if (speed < 3000 || speed > 200000000)
    239 		return EINVAL;
    240 
    241 	if (speed > sc->sc_modclkrate / 2 || speed < sc->sc_modclkrate / 512) {
    242 		for (cctl = 0; cctl <= __SHIFTOUT_MASK(SPI_CCTL_CDR1); cctl++) {
    243 			if ((sc->sc_modclkrate / (1<<cctl)) <= speed)
    244 				goto cdr1_found;
    245 		}
    246 		return EINVAL;
    247 cdr1_found:
    248 		cctl = __SHIFTIN(cctl, SPI_CCTL_CDR1);
    249 	} else {
    250 		cctl = howmany(sc->sc_modclkrate, 2 * speed) - 1;
    251 		cctl = SPI_CCTL_DRS|__SHIFTIN(cctl, SPI_CCTL_CDR2);
    252 	}
    253 
    254 	device_printf(sc->sc_dev, "%s CCTL 0x%08x\n", __func__, cctl);
    255 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SPI_CCTL, cctl);
    256 
    257 	return 0;
    258 }
    259 
    260 static int
    261 sun6ispi_transfer(void *cookie, struct spi_transfer *st)
    262 {
    263 	struct sun6ispi_softc * const sc = cookie;
    264 	int s;
    265 
    266 	s = splbio();
    267 	spi_transq_enqueue(&sc->sc_q, st);
    268 	if (sc->sc_running == false) {
    269 		sun6ispi_start(sc);
    270 	}
    271 	splx(s);
    272 	return 0;
    273 }
    274 
    275 static size_t
    276 chunks_total_count(struct spi_transfer * st)
    277 {
    278 	struct spi_chunk *chunk = st->st_chunks;
    279 	size_t len = 0;
    280 
    281 	do {
    282 		len += chunk->chunk_count;
    283 	} while ((chunk = chunk->chunk_next) != NULL);
    284 
    285 	return len;
    286 }
    287 
    288 static void
    289 sun6ispi_start(struct sun6ispi_softc * const sc)
    290 {
    291 	struct spi_transfer *st;
    292 	uint32_t isr, tcr;
    293 	size_t ctc;
    294 
    295 	//device_printf(sc->sc_dev, "%s\n", __func__);
    296 	while ((st = spi_transq_first(&sc->sc_q)) != NULL) {
    297 
    298 		spi_transq_dequeue(&sc->sc_q);
    299 
    300 		KASSERT(sc->sc_transfer == NULL);
    301 		sc->sc_transfer = st;
    302 		sc->sc_rchunk = sc->sc_wchunk = st->st_chunks;
    303 		sc->sc_running = true;
    304 
    305 		isr = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SPI_INT_STA);
    306 		bus_space_write_4(sc->sc_iot, sc->sc_ioh, SPI_INT_STA, isr);
    307 
    308 		//printf("%s fcr 0x%08x\n", __func__, bus_space_read_4(sc->sc_iot, sc->sc_ioh, SPI_FCR));
    309 
    310 		ctc = chunks_total_count(st);
    311 		//printf("%s total count %zu\n", __func__, ctc);
    312 
    313 		bus_space_write_4(sc->sc_iot, sc->sc_ioh, SPI_BC, __SHIFTIN(ctc, SPI_BC_MBC));
    314 		bus_space_write_4(sc->sc_iot, sc->sc_ioh, SPI_TC, __SHIFTIN(ctc, SPI_TC_MWTC));
    315 		bus_space_write_4(sc->sc_iot, sc->sc_ioh, SPI_BCC, __SHIFTIN(ctc, SPI_BCC_STC));
    316 
    317 		KASSERT(st->st_slave <= 3);
    318 		tcr = sc->sc_TCR | __SHIFTIN(st->st_slave, SPI_TCR_SS_SEL);
    319 
    320 		//device_printf(sc->sc_dev, "%s before TCR write\n", __func__);
    321 		//bus_space_write_4(sc->sc_iot, sc->sc_ioh, SPI_TCR, tcr);
    322 
    323 		sun6ispi_send(sc);
    324 
    325 		const uint32_t ier = SPI_IER_DEFAULT | SPI_IER_RF_RDY_INT_EN | SPI_IER_TX_ERQ_INT_EN;
    326 		bus_space_write_4(sc->sc_iot, sc->sc_ioh, SPI_IER, ier);
    327 
    328 		bus_space_write_4(sc->sc_iot, sc->sc_ioh, SPI_TCR, tcr|SPI_TCR_XCH);
    329 		//device_printf(sc->sc_dev, "%s after TCR write\n", __func__);
    330 
    331 		if (!cold)
    332 			return;
    333 
    334 		//device_printf(sc->sc_dev, "%s cold\n", __func__);
    335 
    336 		int s = splbio();
    337 		for (;;) {
    338 			sun6ispi_intr(sc);
    339 			if (ISSET(st->st_flags, SPI_F_DONE))
    340 				break;
    341 		}
    342 		splx(s);
    343 	}
    344 
    345 	sc->sc_running = false;
    346 //	device_printf(sc->sc_dev, "%s finishes\n", __func__);
    347 }
    348 
    349 static void
    350 sun6ispi_send(struct sun6ispi_softc * const sc)
    351 {
    352 	uint8_t fd;
    353 	uint32_t fsr;
    354 	struct spi_chunk *chunk;
    355 
    356 	//device_printf(sc->sc_dev, "%s\n", __func__);
    357 
    358 	while ((chunk = sc->sc_wchunk) != NULL) {
    359 		while (chunk->chunk_wresid) {
    360 			fsr = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SPI_FSR);
    361 			if (__SHIFTOUT(fsr, SPI_FSR_TF_CNT) >= 64) {
    362 				//printf("%s fsr 0x%08x\n", __func__, fsr);
    363 				return;
    364 			}
    365 			if (chunk->chunk_wptr) {
    366 				fd = *chunk->chunk_wptr++;
    367 			} else {
    368 				fd = '\0';
    369 			}
    370 			//printf("%s fd %02x\n", __func__, fd);
    371 			bus_space_write_1(sc->sc_iot, sc->sc_ioh, SPI_TXD, fd);
    372 			chunk->chunk_wresid--;
    373 		}
    374 		sc->sc_wchunk = sc->sc_wchunk->chunk_next;
    375 	}
    376 }
    377 
    378 static void
    379 sun6ispi_recv(struct sun6ispi_softc * const sc)
    380 {
    381 	uint8_t fd;
    382 	uint32_t fsr;
    383 	struct spi_chunk *chunk;
    384 
    385 	//device_printf(sc->sc_dev, "%s\n", __func__);
    386 
    387 	while ((chunk = sc->sc_rchunk) != NULL) {
    388 		while (chunk->chunk_rresid) {
    389 			fsr = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SPI_FSR);
    390 			if (__SHIFTOUT(fsr, SPI_FSR_RF_CNT) == 0) {
    391 				//printf("%s fsr 0x%08x\n", __func__, fsr);
    392 				return;
    393 			}
    394 			fd = bus_space_read_1(sc->sc_iot, sc->sc_ioh, SPI_RXD);
    395 			//printf("%s fd %02x\n", __func__, fd);
    396 			if (chunk->chunk_rptr) {
    397 				*chunk->chunk_rptr++ = fd;
    398 			}
    399 			chunk->chunk_rresid--;
    400 		}
    401 		sc->sc_rchunk = sc->sc_rchunk->chunk_next;
    402 	}
    403 }
    404 
    405 static int
    406 sun6ispi_intr(void *cookie)
    407 {
    408 	struct sun6ispi_softc * const sc = cookie;
    409 	struct spi_transfer *st;
    410 	uint32_t isr;
    411 
    412 	isr = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SPI_INT_STA);
    413 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SPI_INT_STA, isr);
    414 	//device_printf(sc->sc_dev, "%s ISR 0x%08x\n", __func__, isr);
    415 
    416 	if (ISSET(isr, SPI_ISR_RX_RDY)) {
    417 		sun6ispi_recv(sc);
    418 		sun6ispi_send(sc);
    419 	}
    420 
    421 	if (ISSET(isr, SPI_ISR_TC)) {
    422 		bus_space_write_4(sc->sc_iot, sc->sc_ioh, SPI_IER, SPI_IER_DEFAULT);
    423 
    424 		sc->sc_rchunk = sc->sc_wchunk = NULL;
    425 		st = sc->sc_transfer;
    426 		sc->sc_transfer = NULL;
    427 		KASSERT(st != NULL);
    428 		spi_done(st, 0);
    429 		sc->sc_running = false;
    430 	}
    431 
    432 	return isr;
    433 }
    434