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sun6i_spi.c revision 1.3 
      1 /*	$NetBSD: sun6i_spi.c,v 1.3 2019/08/03 14:42:24 tnn Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 2019 Tobias Nygren
      5  * Copyright (c) 2018 Jonathan A. Kollasch
      6  * All rights reserved.
      7  *
      8  * Redistribution and use in source and binary forms, with or without
      9  * modification, are permitted provided that the following conditions
     10  * are met:
     11  * 1. Redistributions of source code must retain the above copyright
     12  *    notice, this list of conditions and the following disclaimer.
     13  * 2. Redistributions in binary form must reproduce the above copyright
     14  *    notice, this list of conditions and the following disclaimer in the
     15  *    documentation and/or other materials provided with the distribution.
     16  *
     17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
     18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     19  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     20  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
     21  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
     22  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
     23  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
     24  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
     25  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
     26  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
     27  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     28  */
     29 
     30 #include <sys/cdefs.h>
     31 __KERNEL_RCSID(0, "$NetBSD: sun6i_spi.c,v 1.3 2019/08/03 14:42:24 tnn Exp $");
     32 
     33 #include <sys/param.h>
     34 #include <sys/device.h>
     35 #include <sys/systm.h>
     36 #include <sys/bus.h>
     37 #include <sys/intr.h>
     38 #include <sys/kernel.h>
     39 
     40 #include <sys/bitops.h>
     41 #include <dev/spi/spivar.h>
     42 
     43 #include <arm/sunxi/sun6i_spireg.h>
     44 
     45 #include <dev/fdt/fdtvar.h>
     46 
     47 #include <arm/fdt/arm_fdtvar.h>
     48 
     49 #define SPI_IER_DEFAULT (SPI_IER_TC_INT_EN | SPI_IER_TF_UDR_INT_EN | \
     50 	SPI_IER_TF_OVF_INT_EN | SPI_IER_RF_UDR_INT_EN | SPI_IER_RF_OVF_INT_EN)
     51 
     52 struct sun6ispi_softc {
     53 	device_t		sc_dev;
     54 	bus_space_tag_t		sc_iot;
     55 	bus_space_handle_t	sc_ioh;
     56 	void			*sc_intrh;
     57 	struct spi_controller	sc_spi;
     58 	SIMPLEQ_HEAD(,spi_transfer) sc_q;
     59 	struct spi_transfer	*sc_transfer;
     60 	struct spi_chunk	*sc_wchunk;
     61 	struct spi_chunk	*sc_rchunk;
     62 	uint32_t		sc_TCR;
     63 	u_int			sc_modclkrate;
     64 	volatile bool		sc_running;
     65 };
     66 
     67 #define SPIREG_READ(sc, reg) \
     68     bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))
     69 #define SPIREG_WRITE(sc, reg, val) \
     70     bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
     71 
     72 static int sun6ispi_match(device_t, cfdata_t, void *);
     73 static void sun6ispi_attach(device_t, device_t, void *);
     74 
     75 static int sun6ispi_configure(void *, int, int, int);
     76 static int sun6ispi_transfer(void *, struct spi_transfer *);
     77 
     78 static void sun6ispi_start(struct sun6ispi_softc * const);
     79 static int sun6ispi_intr(void *);
     80 
     81 static void sun6ispi_send(struct sun6ispi_softc * const);
     82 static void sun6ispi_recv(struct sun6ispi_softc * const);
     83 
     84 CFATTACH_DECL_NEW(sun6i_spi, sizeof(struct sun6ispi_softc),
     85     sun6ispi_match, sun6ispi_attach, NULL, NULL);
     86 
     87 static int
     88 sun6ispi_match(device_t parent, cfdata_t cf, void *aux)
     89 {
     90 	const char * const compatible[] = {
     91 		"allwinner,sun8i-h3-spi",
     92 		NULL
     93 	};
     94 	struct fdt_attach_args * const faa = aux;
     95 
     96 	return of_match_compatible(faa->faa_phandle, compatible);
     97 }
     98 
     99 static void
    100 sun6ispi_attach(device_t parent, device_t self, void *aux)
    101 {
    102 	struct sun6ispi_softc * const sc = device_private(self);
    103 	struct fdt_attach_args * const faa = aux;
    104 	struct spibus_attach_args sba;
    105 	const int phandle = faa->faa_phandle;
    106 	bus_addr_t addr;
    107 	bus_size_t size;
    108 	struct fdtbus_reset *rst;
    109 	struct clk *clk, *modclk;
    110 	uint32_t gcr, isr;
    111 	char intrstr[128];
    112 
    113 	sc->sc_dev = self;
    114 	sc->sc_iot = faa->faa_bst;
    115 	SIMPLEQ_INIT(&sc->sc_q);
    116 
    117 	if ((clk = fdtbus_clock_get_index(phandle, 0)) == NULL
    118 	    || clk_enable(clk) != 0) {
    119 		aprint_error(": couldn't enable clock\n");
    120 		return;
    121 	}
    122 
    123 	/* 200MHz max on H3,H5 */
    124 	if ((modclk = fdtbus_clock_get(phandle, "mod")) == NULL
    125 	    || clk_set_rate(modclk, 200000000) != 0
    126 	    || clk_enable(modclk) != 0) {
    127 		aprint_error(": couldn't enable module clock\n");
    128 		return;
    129 	}
    130 	sc->sc_modclkrate = clk_get_rate(modclk);
    131 
    132 	if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0
    133 	    || bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh) != 0) {
    134 		aprint_error(": couldn't map registers\n");
    135 		return;
    136 	}
    137 
    138 	if ((rst = fdtbus_reset_get_index(phandle, 0)) != NULL)
    139 		if (fdtbus_reset_deassert(rst) != 0) {
    140 			aprint_error(": couldn't de-assert reset\n");
    141 			return;
    142 		}
    143 
    144 	isr = SPIREG_READ(sc, SPI_INT_STA);
    145 	SPIREG_WRITE(sc, SPI_INT_STA, isr);
    146 
    147 	if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) {
    148 		aprint_error(": failed to decode interrupt\n");
    149 		return;
    150 	}
    151 
    152 	sc->sc_intrh = fdtbus_intr_establish(phandle, 0, IPL_VM, 0,
    153 	    sun6ispi_intr, sc);
    154 	if (sc->sc_intrh == NULL) {
    155 		aprint_error(": unable to establish interrupt\n");
    156 		return;
    157 	}
    158 
    159 	aprint_naive("\n");
    160 	aprint_normal(": SPI\n");
    161 
    162 	aprint_normal_dev(self, "interrupting on %s\n", intrstr);
    163 
    164 	gcr = SPI_GCR_SRST;
    165 	SPIREG_WRITE(sc, SPI_GCR, gcr);
    166 	for (u_int i = 0; ; i++) {
    167 		if (i >= 1000000) {
    168 			aprint_error_dev(self, "reset timeout\n");
    169 			return;
    170 		}
    171 		gcr = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SPI_GCR);
    172 		if ((gcr & SPI_GCR_SRST) == 0)
    173 			break;
    174 		else
    175 			DELAY(1);
    176 	}
    177 	gcr = SPI_GCR_TP_EN | SPI_GCR_MODE | SPI_GCR_EN;
    178 	SPIREG_WRITE(sc, SPI_GCR, gcr);
    179 
    180 	SPIREG_WRITE(sc, SPI_IER, SPI_IER_DEFAULT);
    181 
    182 	sc->sc_spi.sct_cookie = sc;
    183 	sc->sc_spi.sct_configure = sun6ispi_configure;
    184 	sc->sc_spi.sct_transfer = sun6ispi_transfer;
    185 	sc->sc_spi.sct_nslaves = 4;
    186 
    187 	sba.sba_controller = &sc->sc_spi;
    188 
    189 	(void) config_found_ia(self, "spibus", &sba, spibus_print);
    190 }
    191 
    192 static int
    193 sun6ispi_configure(void *cookie, int slave, int mode, int speed)
    194 {
    195 	struct sun6ispi_softc * const sc = cookie;
    196 	uint32_t tcr, cctl;
    197 	uint32_t minfreq, maxfreq;
    198 
    199 	minfreq = sc->sc_modclkrate >> 16;
    200 	maxfreq = sc->sc_modclkrate >> 1;
    201 
    202 	if (speed <= 0 || speed < minfreq || speed > maxfreq)
    203 		return EINVAL;
    204 
    205 	if (slave >= sc->sc_spi.sct_nslaves)
    206 		return EINVAL;
    207 
    208 	tcr = SPI_TCR_SS_LEVEL | SPI_TCR_SPOL;
    209 
    210 	switch (mode) {
    211 	case SPI_MODE_0:
    212 		tcr |= 0;
    213 		break;
    214 	case SPI_MODE_1:
    215 		tcr |= SPI_TCR_CPHA;
    216 		break;
    217 	case SPI_MODE_2:
    218 		tcr |= SPI_TCR_CPOL;
    219 		break;
    220 	case SPI_MODE_3:
    221 		tcr |= SPI_TCR_CPHA|SPI_TCR_CPOL;
    222 		break;
    223 	default:
    224 		return EINVAL;
    225 	}
    226 
    227 	sc->sc_TCR = tcr;
    228 
    229 	if (speed < sc->sc_modclkrate / 512) {
    230 		for (cctl = 0; cctl <= __SHIFTOUT_MASK(SPI_CCTL_CDR1); cctl++) {
    231 			if ((sc->sc_modclkrate / (1<<cctl)) <= speed)
    232 				goto cdr1_found;
    233 		}
    234 		return EINVAL;
    235 cdr1_found:
    236 		cctl = __SHIFTIN(cctl, SPI_CCTL_CDR1);
    237 	} else {
    238 		cctl = howmany(sc->sc_modclkrate, 2 * speed) - 1;
    239 		cctl = SPI_CCTL_DRS|__SHIFTIN(cctl, SPI_CCTL_CDR2);
    240 	}
    241 
    242 	device_printf(sc->sc_dev, "tcr 0x%x, cctl 0x%x, CLK %uHz, SCLK %uHz\n",
    243 	    tcr, cctl, sc->sc_modclkrate,
    244 	    (cctl & SPI_CCTL_DRS)
    245 	    ? (sc->sc_modclkrate / (u_int)(2 * (__SHIFTOUT(cctl, SPI_CCTL_CDR2) + 1)))
    246 	    : (sc->sc_modclkrate >> (__SHIFTOUT(cctl, SPI_CCTL_CDR1) + 1))
    247 	);
    248 
    249 	SPIREG_WRITE(sc, SPI_CCTL, cctl);
    250 
    251 	return 0;
    252 }
    253 
    254 static int
    255 sun6ispi_transfer(void *cookie, struct spi_transfer *st)
    256 {
    257 	struct sun6ispi_softc * const sc = cookie;
    258 	int s;
    259 
    260 	s = splbio();
    261 	spi_transq_enqueue(&sc->sc_q, st);
    262 	if (sc->sc_running == false) {
    263 		sun6ispi_start(sc);
    264 	}
    265 	splx(s);
    266 	return 0;
    267 }
    268 
    269 static void
    270 sun6ispi_start(struct sun6ispi_softc * const sc)
    271 {
    272 	struct spi_transfer *st;
    273 	uint32_t isr, tcr;
    274 	struct spi_chunk *chunk;
    275 	size_t burstcount;
    276 
    277 	while ((st = spi_transq_first(&sc->sc_q)) != NULL) {
    278 
    279 		spi_transq_dequeue(&sc->sc_q);
    280 
    281 		KASSERT(sc->sc_transfer == NULL);
    282 		sc->sc_transfer = st;
    283 		sc->sc_rchunk = sc->sc_wchunk = st->st_chunks;
    284 		sc->sc_running = true;
    285 
    286 		isr = SPIREG_READ(sc, SPI_INT_STA);
    287 		SPIREG_WRITE(sc, SPI_INT_STA, isr);
    288 
    289 		burstcount = 0;
    290 		for (chunk = st->st_chunks; chunk; chunk = chunk->chunk_next) {
    291 			burstcount += chunk->chunk_count;
    292 		}
    293 		KASSERT(burstcount <= SPI_BC_MBC);
    294 		SPIREG_WRITE(sc, SPI_BC, __SHIFTIN(burstcount, SPI_BC_MBC));
    295 		SPIREG_WRITE(sc, SPI_TC, __SHIFTIN(burstcount, SPI_TC_MWTC));
    296 		SPIREG_WRITE(sc, SPI_BCC, __SHIFTIN(burstcount, SPI_BCC_STC));
    297 
    298 		KASSERT(st->st_slave <= 3);
    299 		tcr = sc->sc_TCR | __SHIFTIN(st->st_slave, SPI_TCR_SS_SEL);
    300 
    301 		sun6ispi_send(sc);
    302 
    303 		const uint32_t ier = SPI_IER_DEFAULT | SPI_IER_RF_RDY_INT_EN | SPI_IER_TX_ERQ_INT_EN;
    304 		SPIREG_WRITE(sc, SPI_IER, ier);
    305 
    306 		SPIREG_WRITE(sc, SPI_TCR, tcr|SPI_TCR_XCH);
    307 
    308 		if (!cold)
    309 			return;
    310 
    311 		int s = splbio();
    312 		for (;;) {
    313 			sun6ispi_intr(sc);
    314 			if (ISSET(st->st_flags, SPI_F_DONE))
    315 				break;
    316 		}
    317 		splx(s);
    318 	}
    319 
    320 	sc->sc_running = false;
    321 }
    322 
    323 static void
    324 sun6ispi_send(struct sun6ispi_softc * const sc)
    325 {
    326 	uint8_t fd;
    327 	uint32_t fsr;
    328 	struct spi_chunk *chunk;
    329 
    330 	while ((chunk = sc->sc_wchunk) != NULL) {
    331 		while (chunk->chunk_wresid) {
    332 			fsr = SPIREG_READ(sc, SPI_FSR);
    333 			if (__SHIFTOUT(fsr, SPI_FSR_TF_CNT) >= 64) {
    334 				return;
    335 			}
    336 			if (chunk->chunk_wptr) {
    337 				fd = *chunk->chunk_wptr++;
    338 			} else {
    339 				fd = '\0';
    340 			}
    341 			bus_space_write_1(sc->sc_iot, sc->sc_ioh, SPI_TXD, fd);
    342 			chunk->chunk_wresid--;
    343 		}
    344 		sc->sc_wchunk = sc->sc_wchunk->chunk_next;
    345 	}
    346 }
    347 
    348 static void
    349 sun6ispi_recv(struct sun6ispi_softc * const sc)
    350 {
    351 	uint8_t fd;
    352 	uint32_t fsr;
    353 	struct spi_chunk *chunk;
    354 
    355 	while ((chunk = sc->sc_rchunk) != NULL) {
    356 		while (chunk->chunk_rresid) {
    357 			fsr = SPIREG_READ(sc, SPI_FSR);
    358 			if (__SHIFTOUT(fsr, SPI_FSR_RF_CNT) == 0) {
    359 				return;
    360 			}
    361 			fd = bus_space_read_1(sc->sc_iot, sc->sc_ioh, SPI_RXD);
    362 			if (chunk->chunk_rptr) {
    363 				*chunk->chunk_rptr++ = fd;
    364 			}
    365 			chunk->chunk_rresid--;
    366 		}
    367 		sc->sc_rchunk = sc->sc_rchunk->chunk_next;
    368 	}
    369 }
    370 
    371 static int
    372 sun6ispi_intr(void *cookie)
    373 {
    374 	struct sun6ispi_softc * const sc = cookie;
    375 	struct spi_transfer *st;
    376 	uint32_t isr;
    377 
    378 	isr = SPIREG_READ(sc, SPI_INT_STA);
    379 	SPIREG_WRITE(sc, SPI_INT_STA, isr);
    380 
    381 	if (ISSET(isr, SPI_ISR_RX_RDY)) {
    382 		sun6ispi_recv(sc);
    383 		sun6ispi_send(sc);
    384 	}
    385 
    386 	if (ISSET(isr, SPI_ISR_TC)) {
    387 		SPIREG_WRITE(sc, SPI_IER, SPI_IER_DEFAULT);
    388 
    389 		sc->sc_rchunk = sc->sc_wchunk = NULL;
    390 		st = sc->sc_transfer;
    391 		sc->sc_transfer = NULL;
    392 		KASSERT(st != NULL);
    393 		spi_done(st, 0);
    394 		sc->sc_running = false;
    395 	}
    396 
    397 	return isr;
    398 }
    399