sun8i_codec.c revision 1.1
1 /* $NetBSD: sun8i_codec.c,v 1.1 2018/05/10 00:00:21 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: sun8i_codec.c,v 1.1 2018/05/10 00:00:21 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/cpu.h> 35 #include <sys/device.h> 36 #include <sys/kmem.h> 37 #include <sys/bitops.h> 38 #include <sys/gpio.h> 39 40 #include <dev/audio_dai.h> 41 42 #include <dev/fdt/fdtvar.h> 43 44 #define SYSCLK_CTL 0x00c 45 #define AIF1CLK_ENA __BIT(11) 46 #define AIF1CLK_SRC __BITS(9,8) 47 #define AIF1CLK_SRC_PLL 2 48 #define SYSCLK_ENA __BIT(3) 49 #define SYSCLK_SRC __BIT(0) 50 51 #define MOD_CLK_ENA 0x010 52 #define MOD_RST_CTL 0x014 53 #define MOD_AIF1 __BIT(15) 54 #define MOD_ADC __BIT(3) 55 #define MOD_DAC __BIT(2) 56 57 #define SYS_SR_CTRL 0x018 58 #define AIF1_FS __BITS(15,12) 59 #define AIF_FS_48KHZ 8 60 61 #define AIF1CLK_CTRL 0x040 62 #define AIF1_MSTR_MOD __BIT(15) 63 #define AIF1_BCLK_INV __BIT(14) 64 #define AIF1_LRCK_INV __BIT(13) 65 #define AIF1_BCLK_DIV __BITS(12,9) 66 #define AIF1_BCLK_DIV_16 6 67 #define AIF1_LRCK_DIV __BITS(8,6) 68 #define AIF1_LRCK_DIV_16 0 69 #define AIF1_LRCK_DIV_64 2 70 #define AIF1_WORD_SIZ __BITS(5,4) 71 #define AIF1_WORD_SIZ_16 1 72 #define AIF1_DATA_FMT __BITS(3,2) 73 #define AIF1_DATA_FMT_I2S 0 74 #define AIF1_DATA_FMT_LJ 1 75 #define AIF1_DATA_FMT_RJ 2 76 #define AIF1_DATA_FMT_DSP 3 77 78 #define AIF1_DACDAT_CTRL 0x048 79 #define AIF1_DAC0L_ENA __BIT(15) 80 #define AIF1_DAC0R_ENA __BIT(14) 81 82 #define ADC_DIG_CTRL 0x100 83 #define ADC_DIG_CTRL_ENAD __BIT(15) 84 85 #define DAC_DIG_CTRL 0x120 86 #define DAC_DIG_CTRL_ENDA __BIT(15) 87 88 #define DAC_MXR_SRC 0x130 89 #define DACL_MXR_SRC __BITS(15,12) 90 #define DACL_MXR_SRC_AIF1_DAC0L 0x8 91 #define DACR_MXR_SRC __BITS(11,8) 92 #define DACR_MXR_SRC_AIF1_DAC0R 0x8 93 94 struct sun8i_codec_softc { 95 device_t sc_dev; 96 bus_space_tag_t sc_bst; 97 bus_space_handle_t sc_bsh; 98 int sc_phandle; 99 100 struct audio_dai_device sc_dai; 101 102 struct fdtbus_gpio_pin *sc_pin_pa; 103 104 struct clk *sc_clk_gate; 105 struct clk *sc_clk_mod; 106 }; 107 108 #define RD4(sc, reg) \ 109 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 110 #define WR4(sc, reg, val) \ 111 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 112 113 static int 114 sun8i_codec_set_params(void *priv, int setmode, int usemode, 115 audio_params_t *play, audio_params_t *rec, 116 stream_filter_list_t *pfil, stream_filter_list_t *rfil) 117 { 118 if (play && (setmode & AUMODE_PLAY)) 119 if (play->sample_rate != 48000) 120 return EINVAL; 121 122 if (rec && (setmode & AUMODE_RECORD)) 123 if (rec->sample_rate != 48000) 124 return EINVAL; 125 126 return 0; 127 } 128 129 static const struct audio_hw_if sun8i_codec_hw_if = { 130 .set_params = sun8i_codec_set_params, 131 }; 132 133 static audio_dai_tag_t 134 sun8i_codec_dai_get_tag(device_t dev, const void *data, size_t len) 135 { 136 struct sun8i_codec_softc * const sc = device_private(dev); 137 138 if (len != 4) 139 return NULL; 140 141 return &sc->sc_dai; 142 } 143 144 static struct fdtbus_dai_controller_func sun8i_codec_dai_funcs = { 145 .get_tag = sun8i_codec_dai_get_tag 146 }; 147 148 static int 149 sun8i_codec_dai_set_format(audio_dai_tag_t dai, u_int format) 150 { 151 struct sun8i_codec_softc * const sc = audio_dai_private(dai); 152 uint32_t val; 153 154 const u_int fmt = __SHIFTOUT(format, AUDIO_DAI_FORMAT_MASK); 155 const u_int pol = __SHIFTOUT(format, AUDIO_DAI_POLARITY_MASK); 156 const u_int clk = __SHIFTOUT(format, AUDIO_DAI_CLOCK_MASK); 157 158 val = RD4(sc, AIF1CLK_CTRL); 159 160 val &= ~AIF1_DATA_FMT; 161 switch (fmt) { 162 case AUDIO_DAI_FORMAT_I2S: 163 val |= __SHIFTIN(AIF1_DATA_FMT_I2S, AIF1_DATA_FMT); 164 break; 165 case AUDIO_DAI_FORMAT_RJ: 166 val |= __SHIFTIN(AIF1_DATA_FMT_RJ, AIF1_DATA_FMT); 167 break; 168 case AUDIO_DAI_FORMAT_LJ: 169 val |= __SHIFTIN(AIF1_DATA_FMT_LJ, AIF1_DATA_FMT); 170 break; 171 case AUDIO_DAI_FORMAT_DSPA: 172 case AUDIO_DAI_FORMAT_DSPB: 173 val |= __SHIFTIN(AIF1_DATA_FMT_DSP, AIF1_DATA_FMT); 174 break; 175 default: 176 return EINVAL; 177 } 178 179 val &= ~(AIF1_BCLK_INV|AIF1_LRCK_INV); 180 /* Codec LRCK polarity is inverted (datasheet is wrong) */ 181 if (!AUDIO_DAI_POLARITY_F(pol)) 182 val |= AIF1_LRCK_INV; 183 if (AUDIO_DAI_POLARITY_B(pol)) 184 val |= AIF1_BCLK_INV; 185 186 switch (clk) { 187 case AUDIO_DAI_CLOCK_CBM_CFM: 188 val &= ~AIF1_MSTR_MOD; /* codec is master */ 189 break; 190 case AUDIO_DAI_CLOCK_CBS_CFS: 191 val |= AIF1_MSTR_MOD; /* codec is slave */ 192 break; 193 default: 194 return EINVAL; 195 } 196 197 val &= ~AIF1_LRCK_DIV; 198 val |= __SHIFTIN(AIF1_LRCK_DIV_64, AIF1_LRCK_DIV); 199 200 val &= ~AIF1_BCLK_DIV; 201 val |= __SHIFTIN(AIF1_BCLK_DIV_16, AIF1_BCLK_DIV); 202 203 WR4(sc, AIF1CLK_CTRL, val); 204 205 return 0; 206 } 207 208 static const char * compatible[] = { 209 "allwinner,sun50i-a64-codec", 210 NULL 211 }; 212 213 static int 214 sun8i_codec_match(device_t parent, cfdata_t cf, void *aux) 215 { 216 struct fdt_attach_args * const faa = aux; 217 218 return of_match_compatible(faa->faa_phandle, compatible); 219 } 220 221 static void 222 sun8i_codec_attach(device_t parent, device_t self, void *aux) 223 { 224 struct sun8i_codec_softc * const sc = device_private(self); 225 struct fdt_attach_args * const faa = aux; 226 const int phandle = faa->faa_phandle; 227 bus_addr_t addr; 228 bus_size_t size; 229 uint32_t val; 230 231 sc->sc_dev = self; 232 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 233 aprint_error(": couldn't get registers\n"); 234 return; 235 } 236 sc->sc_bst = faa->faa_bst; 237 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 238 aprint_error(": couldn't map registers\n"); 239 return; 240 } 241 242 sc->sc_clk_gate = fdtbus_clock_get(phandle, "bus"); 243 sc->sc_clk_mod = fdtbus_clock_get(phandle, "mod"); 244 if (!sc->sc_clk_gate || !sc->sc_clk_mod) { 245 aprint_error(": couldn't get clocks\n"); 246 return; 247 } 248 if (clk_enable(sc->sc_clk_gate) != 0) { 249 aprint_error(": couldn't enable bus clock\n"); 250 return; 251 } 252 253 sc->sc_phandle = phandle; 254 255 aprint_naive("\n"); 256 aprint_normal(": Audio Codec\n"); 257 258 /* Enable clocks */ 259 val = RD4(sc, SYSCLK_CTL); 260 val |= AIF1CLK_ENA; 261 val &= ~AIF1CLK_SRC; 262 val |= __SHIFTIN(AIF1CLK_SRC_PLL, AIF1CLK_SRC); 263 val |= SYSCLK_ENA; 264 val &= ~SYSCLK_SRC; 265 WR4(sc, SYSCLK_CTL, val); 266 WR4(sc, MOD_CLK_ENA, MOD_AIF1 | MOD_ADC | MOD_DAC); 267 WR4(sc, MOD_RST_CTL, MOD_AIF1 | MOD_ADC | MOD_DAC); 268 269 /* Enable digital parts */ 270 WR4(sc, DAC_DIG_CTRL, DAC_DIG_CTRL_ENDA); 271 WR4(sc, ADC_DIG_CTRL, ADC_DIG_CTRL_ENAD); 272 273 /* Set AIF1 to 48 kHz */ 274 val = RD4(sc, SYS_SR_CTRL); 275 val &= ~AIF1_FS; 276 val |= __SHIFTIN(AIF_FS_48KHZ, AIF1_FS); 277 WR4(sc, SYS_SR_CTRL, val); 278 279 /* Set AIF1 to 16-bit */ 280 val = RD4(sc, AIF1CLK_CTRL); 281 val &= ~AIF1_WORD_SIZ; 282 val |= __SHIFTIN(AIF1_WORD_SIZ_16, AIF1_WORD_SIZ); 283 WR4(sc, AIF1CLK_CTRL, val); 284 285 /* Enable AIF1 DAC timelot 0 */ 286 val = RD4(sc, AIF1_DACDAT_CTRL); 287 val |= AIF1_DAC0L_ENA; 288 val |= AIF1_DAC0R_ENA; 289 WR4(sc, AIF1_DACDAT_CTRL, val); 290 291 /* DAC mixer source select */ 292 val = RD4(sc, DAC_MXR_SRC); 293 val &= ~DACL_MXR_SRC; 294 val |= __SHIFTIN(DACL_MXR_SRC_AIF1_DAC0L, DACL_MXR_SRC); 295 val &= ~DACR_MXR_SRC; 296 val |= __SHIFTIN(DACR_MXR_SRC_AIF1_DAC0R, DACR_MXR_SRC); 297 WR4(sc, DAC_MXR_SRC, val); 298 299 /* Enable PA power */ 300 sc->sc_pin_pa = fdtbus_gpio_acquire(phandle, "allwinner,pa-gpios", GPIO_PIN_OUTPUT); 301 if (sc->sc_pin_pa) 302 fdtbus_gpio_write(sc->sc_pin_pa, 1); 303 304 sc->sc_dai.dai_set_format = sun8i_codec_dai_set_format; 305 sc->sc_dai.dai_hw_if = &sun8i_codec_hw_if; 306 sc->sc_dai.dai_dev = self; 307 sc->sc_dai.dai_priv = sc; 308 fdtbus_register_dai_controller(self, phandle, &sun8i_codec_dai_funcs); 309 } 310 311 CFATTACH_DECL_NEW(sun8i_codec, sizeof(struct sun8i_codec_softc), 312 sun8i_codec_match, sun8i_codec_attach, NULL, NULL); 313
Indexes created Tue Sep 23 14:10:03 GMT 2025