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sun8i_codec.c revision 1.2 
      1 /* $NetBSD: sun8i_codec.c,v 1.2 2018/05/11 22:51:12 jmcneill Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2018 Jared McNeill <jmcneill (at) invisible.ca>
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
     21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
     23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     26  * SUCH DAMAGE.
     27  */
     28 
     29 #include <sys/cdefs.h>
     30 __KERNEL_RCSID(0, "$NetBSD: sun8i_codec.c,v 1.2 2018/05/11 22:51:12 jmcneill Exp $");
     31 
     32 #include <sys/param.h>
     33 #include <sys/bus.h>
     34 #include <sys/cpu.h>
     35 #include <sys/device.h>
     36 #include <sys/kmem.h>
     37 #include <sys/bitops.h>
     38 #include <sys/gpio.h>
     39 #include <sys/workqueue.h>
     40 
     41 #include <dev/audio_dai.h>
     42 
     43 #include <dev/fdt/fdtvar.h>
     44 
     45 #define	SYSCLK_CTL		0x00c
     46 #define	 AIF1CLK_ENA		__BIT(11)
     47 #define	 AIF1CLK_SRC		__BITS(9,8)
     48 #define	  AIF1CLK_SRC_PLL	2
     49 #define	 SYSCLK_ENA		__BIT(3)
     50 #define	 SYSCLK_SRC		__BIT(0)
     51 
     52 #define	MOD_CLK_ENA		0x010
     53 #define	MOD_RST_CTL		0x014
     54 #define	 MOD_AIF1		__BIT(15)
     55 #define	 MOD_ADC		__BIT(3)
     56 #define	 MOD_DAC		__BIT(2)
     57 
     58 #define	SYS_SR_CTRL		0x018
     59 #define	 AIF1_FS		__BITS(15,12)
     60 #define	  AIF_FS_48KHZ		8
     61 
     62 #define	AIF1CLK_CTRL		0x040
     63 #define	 AIF1_MSTR_MOD		__BIT(15)
     64 #define	 AIF1_BCLK_INV		__BIT(14)
     65 #define	 AIF1_LRCK_INV		__BIT(13)
     66 #define	 AIF1_BCLK_DIV		__BITS(12,9)
     67 #define	  AIF1_BCLK_DIV_16	6
     68 #define	 AIF1_LRCK_DIV		__BITS(8,6)
     69 #define	  AIF1_LRCK_DIV_16	0
     70 #define	  AIF1_LRCK_DIV_64	2
     71 #define	 AIF1_WORD_SIZ		__BITS(5,4)
     72 #define	  AIF1_WORD_SIZ_16	1
     73 #define	 AIF1_DATA_FMT		__BITS(3,2)
     74 #define	  AIF1_DATA_FMT_I2S	0
     75 #define	  AIF1_DATA_FMT_LJ	1
     76 #define	  AIF1_DATA_FMT_RJ	2
     77 #define	  AIF1_DATA_FMT_DSP	3
     78 
     79 #define	AIF1_DACDAT_CTRL	0x048
     80 #define	 AIF1_DAC0L_ENA		__BIT(15)
     81 #define	 AIF1_DAC0R_ENA		__BIT(14)
     82 
     83 #define	ADC_DIG_CTRL		0x100
     84 #define	 ADC_DIG_CTRL_ENAD	__BIT(15)
     85 
     86 #define	HMIC_CTRL1		0x110
     87 #define	 HMIC_CTRL1_N		__BITS(11,8)
     88 #define	 HMIC_CTRL1_JACK_IN_IRQ_EN __BIT(4)
     89 #define	 HMIC_CTRL1_JACK_OUT_IRQ_EN __BIT(3)
     90 #define	 HMIC_CTRL1_MIC_DET_IRQ_EN __BIT(0)
     91 
     92 #define	HMIC_CTRL2		0x114
     93 #define	 HMIC_CTRL2_MDATA_THRES	__BITS(12,8)
     94 
     95 #define	HMIC_STS		0x118
     96 #define	 HMIC_STS_MIC_PRESENT	__BIT(6)
     97 #define	 HMIC_STS_JACK_DET_OIRQ	__BIT(4)
     98 #define	 HMIC_STS_JACK_DET_IIRQ	__BIT(3)
     99 #define	 HMIC_STS_MIC_DET_ST	__BIT(0)
    100 
    101 #define	DAC_DIG_CTRL		0x120
    102 #define	 DAC_DIG_CTRL_ENDA	__BIT(15)
    103 
    104 #define	DAC_MXR_SRC		0x130
    105 #define	 DACL_MXR_SRC		__BITS(15,12)
    106 #define	  DACL_MXR_SRC_AIF1_DAC0L 0x8
    107 #define	 DACR_MXR_SRC		__BITS(11,8)
    108 #define	  DACR_MXR_SRC_AIF1_DAC0R 0x8
    109 
    110 struct sun8i_codec_softc {
    111 	device_t		sc_dev;
    112 	bus_space_tag_t		sc_bst;
    113 	bus_space_handle_t	sc_bsh;
    114 	int			sc_phandle;
    115 
    116 	struct workqueue	*sc_workq;
    117 	struct work		sc_work;
    118 
    119 	struct audio_dai_device	sc_dai;
    120 	audio_dai_tag_t		sc_codec_analog;
    121 	uint32_t		sc_jackdet;
    122 	int			sc_jackdet_pol;
    123 
    124 	struct fdtbus_gpio_pin	*sc_pin_pa;
    125 
    126 	struct clk		*sc_clk_gate;
    127 	struct clk		*sc_clk_mod;
    128 };
    129 
    130 #define	RD4(sc, reg)			\
    131 	bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
    132 #define	WR4(sc, reg, val)		\
    133 	bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
    134 
    135 static int
    136 sun8i_codec_set_params(void *priv, int setmode, int usemode,
    137     audio_params_t *play, audio_params_t *rec,
    138     stream_filter_list_t *pfil, stream_filter_list_t *rfil)
    139 {
    140 	if (play && (setmode & AUMODE_PLAY))
    141 		if (play->sample_rate != 48000)
    142 			return EINVAL;
    143 
    144 	if (rec && (setmode & AUMODE_RECORD))
    145 		if (rec->sample_rate != 48000)
    146 			return EINVAL;
    147 
    148 	return 0;
    149 }
    150 
    151 static const struct audio_hw_if sun8i_codec_hw_if = {
    152 	.set_params = sun8i_codec_set_params,
    153 };
    154 
    155 static audio_dai_tag_t
    156 sun8i_codec_dai_get_tag(device_t dev, const void *data, size_t len)
    157 {
    158 	struct sun8i_codec_softc * const sc = device_private(dev);
    159 
    160 	if (len != 4)
    161 		return NULL;
    162 
    163 	return &sc->sc_dai;
    164 }
    165 
    166 static struct fdtbus_dai_controller_func sun8i_codec_dai_funcs = {
    167 	.get_tag = sun8i_codec_dai_get_tag
    168 };
    169 
    170 static int
    171 sun8i_codec_dai_set_format(audio_dai_tag_t dai, u_int format)
    172 {
    173 	struct sun8i_codec_softc * const sc = audio_dai_private(dai);
    174 	uint32_t val;
    175 
    176         const u_int fmt = __SHIFTOUT(format, AUDIO_DAI_FORMAT_MASK);
    177         const u_int pol = __SHIFTOUT(format, AUDIO_DAI_POLARITY_MASK);
    178         const u_int clk = __SHIFTOUT(format, AUDIO_DAI_CLOCK_MASK);
    179 
    180 	val = RD4(sc, AIF1CLK_CTRL);
    181 
    182 	val &= ~AIF1_DATA_FMT;
    183 	switch (fmt) {
    184 	case AUDIO_DAI_FORMAT_I2S:
    185 		val |= __SHIFTIN(AIF1_DATA_FMT_I2S, AIF1_DATA_FMT);
    186 		break;
    187 	case AUDIO_DAI_FORMAT_RJ:
    188 		val |= __SHIFTIN(AIF1_DATA_FMT_RJ, AIF1_DATA_FMT);
    189 		break;
    190 	case AUDIO_DAI_FORMAT_LJ:
    191 		val |= __SHIFTIN(AIF1_DATA_FMT_LJ, AIF1_DATA_FMT);
    192 		break;
    193 	case AUDIO_DAI_FORMAT_DSPA:
    194 	case AUDIO_DAI_FORMAT_DSPB:
    195 		val |= __SHIFTIN(AIF1_DATA_FMT_DSP, AIF1_DATA_FMT);
    196 		break;
    197 	default:
    198 		return EINVAL;
    199 	}
    200 
    201 	val &= ~(AIF1_BCLK_INV|AIF1_LRCK_INV);
    202 	/* Codec LRCK polarity is inverted (datasheet is wrong) */
    203 	if (!AUDIO_DAI_POLARITY_F(pol))
    204 		val |= AIF1_LRCK_INV;
    205 	if (AUDIO_DAI_POLARITY_B(pol))
    206 		val |= AIF1_BCLK_INV;
    207 
    208 	switch (clk) {
    209 	case AUDIO_DAI_CLOCK_CBM_CFM:
    210 		val &= ~AIF1_MSTR_MOD;	/* codec is master */
    211 		break;
    212 	case AUDIO_DAI_CLOCK_CBS_CFS:
    213 		val |= AIF1_MSTR_MOD;	/* codec is slave */
    214 		break;
    215 	default:
    216 		return EINVAL;
    217 	}
    218 
    219 	val &= ~AIF1_LRCK_DIV;
    220 	val |= __SHIFTIN(AIF1_LRCK_DIV_64, AIF1_LRCK_DIV);
    221 
    222 	val &= ~AIF1_BCLK_DIV;
    223 	val |= __SHIFTIN(AIF1_BCLK_DIV_16, AIF1_BCLK_DIV);
    224 
    225 	WR4(sc, AIF1CLK_CTRL, val);
    226 
    227 	return 0;
    228 }
    229 
    230 static int
    231 sun8i_codec_dai_add_device(audio_dai_tag_t dai, audio_dai_tag_t aux)
    232 {
    233 	struct sun8i_codec_softc * const sc = audio_dai_private(dai);
    234 
    235 	if (sc->sc_codec_analog != NULL)
    236 		return 0;
    237 
    238 	sc->sc_codec_analog = aux;
    239 
    240 	return 0;
    241 }
    242 
    243 static void
    244 sun8i_codec_set_jackdet(struct sun8i_codec_softc *sc, bool enable)
    245 {
    246 	const uint32_t mask =
    247 	    HMIC_CTRL1_JACK_IN_IRQ_EN |
    248 	    HMIC_CTRL1_JACK_OUT_IRQ_EN |
    249 	    HMIC_CTRL1_MIC_DET_IRQ_EN;
    250 	uint32_t val;
    251 
    252 	val = RD4(sc, HMIC_CTRL1);
    253 	if (enable)
    254 		val |= mask;
    255 	else
    256 		val &= ~mask;
    257 	WR4(sc, HMIC_CTRL1, val);
    258 }
    259 
    260 static int
    261 sun8i_codec_intr(void *priv)
    262 {
    263 	struct sun8i_codec_softc * const sc = priv;
    264 	const uint32_t mask =
    265 	    HMIC_STS_JACK_DET_OIRQ |
    266 	    HMIC_STS_JACK_DET_IIRQ |
    267 	    HMIC_STS_MIC_DET_ST;
    268 
    269 	sc->sc_jackdet = RD4(sc, HMIC_STS);
    270 
    271 	if (sc->sc_jackdet & mask) {
    272 		/* Disable jack detect IRQ until work is complete */
    273 		sun8i_codec_set_jackdet(sc, false);
    274 
    275 		/* Schedule pending jack detect task */
    276 		workqueue_enqueue(sc->sc_workq, &sc->sc_work, NULL);
    277 	}
    278 
    279 	WR4(sc, HMIC_STS, sc->sc_jackdet);
    280 
    281 	return 1;
    282 }
    283 
    284 
    285 static void
    286 sun8i_codec_thread(struct work *wk, void *priv)
    287 {
    288 	struct sun8i_codec_softc * const sc = priv;
    289 	const uint32_t sts = sc->sc_jackdet;
    290 	int hpdet = -1, micdet = -1;
    291 
    292 	if (sc->sc_codec_analog) {
    293 		if (sts & HMIC_STS_JACK_DET_OIRQ)
    294 			hpdet = 0 ^ sc->sc_jackdet_pol;
    295 		else if (sts & HMIC_STS_JACK_DET_IIRQ)
    296 			hpdet = 1 ^ sc->sc_jackdet_pol;
    297 
    298 		if (sts & HMIC_STS_MIC_DET_ST)
    299 			micdet = !!(sts & HMIC_STS_MIC_PRESENT);
    300 
    301 		if (hpdet != -1) {
    302 			audio_dai_jack_detect(sc->sc_codec_analog,
    303 			    AUDIO_DAI_JACK_HP, hpdet);
    304 		}
    305 		if (micdet != -1) {
    306 			audio_dai_jack_detect(sc->sc_codec_analog,
    307 			    AUDIO_DAI_JACK_MIC, micdet);
    308 		}
    309 	}
    310 
    311 	/* Re-enable jack detect IRQ */
    312 	sun8i_codec_set_jackdet(sc, true);
    313 }
    314 
    315 static const char * compatible[] = {
    316 	"allwinner,sun50i-a64-codec",
    317 	NULL
    318 };
    319 
    320 static int
    321 sun8i_codec_match(device_t parent, cfdata_t cf, void *aux)
    322 {
    323 	struct fdt_attach_args * const faa = aux;
    324 
    325 	return of_match_compatible(faa->faa_phandle, compatible);
    326 }
    327 
    328 static void
    329 sun8i_codec_attach(device_t parent, device_t self, void *aux)
    330 {
    331 	struct sun8i_codec_softc * const sc = device_private(self);
    332 	struct fdt_attach_args * const faa = aux;
    333 	const int phandle = faa->faa_phandle;
    334 	char intrstr[128];
    335 	bus_addr_t addr;
    336 	bus_size_t size;
    337 	uint32_t val;
    338 	void *ih;
    339 
    340 	if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
    341 		aprint_error(": couldn't get registers\n");
    342 		return;
    343 	}
    344 
    345 	if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) {
    346 		aprint_error(": couldn't decode interrupt\n");
    347 		return;
    348 	}
    349 
    350 	sc->sc_dev = self;
    351 	sc->sc_bst = faa->faa_bst;
    352 	if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
    353 		aprint_error(": couldn't map registers\n");
    354 		return;
    355 	}
    356 	sc->sc_jackdet_pol = 1;
    357 
    358 	sc->sc_clk_gate = fdtbus_clock_get(phandle, "bus");
    359 	sc->sc_clk_mod = fdtbus_clock_get(phandle, "mod");
    360 	if (!sc->sc_clk_gate || !sc->sc_clk_mod) {
    361 		aprint_error(": couldn't get clocks\n");
    362 		return;
    363 	}
    364 	if (clk_enable(sc->sc_clk_gate) != 0) {
    365 		aprint_error(": couldn't enable bus clock\n");
    366 		return;
    367 	}
    368 
    369 	sc->sc_phandle = phandle;
    370 
    371 	aprint_naive("\n");
    372 	aprint_normal(": Audio Codec\n");
    373 
    374 	if (workqueue_create(&sc->sc_workq, "jackdet", sun8i_codec_thread,
    375 	    sc, PRI_NONE, IPL_VM, 0) != 0) {
    376 		aprint_error_dev(self, "couldn't create jackdet workqueue\n");
    377 		return;
    378 	}
    379 
    380 	/* Enable clocks */
    381 	val = RD4(sc, SYSCLK_CTL);
    382 	val |= AIF1CLK_ENA;
    383 	val &= ~AIF1CLK_SRC;
    384 	val |= __SHIFTIN(AIF1CLK_SRC_PLL, AIF1CLK_SRC);
    385 	val |= SYSCLK_ENA;
    386 	val &= ~SYSCLK_SRC;
    387 	WR4(sc, SYSCLK_CTL, val);
    388 	WR4(sc, MOD_CLK_ENA, MOD_AIF1 | MOD_ADC | MOD_DAC);
    389 	WR4(sc, MOD_RST_CTL, MOD_AIF1 | MOD_ADC | MOD_DAC);
    390 
    391 	/* Enable digital parts */
    392 	WR4(sc, DAC_DIG_CTRL, DAC_DIG_CTRL_ENDA);
    393 	WR4(sc, ADC_DIG_CTRL, ADC_DIG_CTRL_ENAD);
    394 
    395 	/* Set AIF1 to 48 kHz */
    396 	val = RD4(sc, SYS_SR_CTRL);
    397 	val &= ~AIF1_FS;
    398 	val |= __SHIFTIN(AIF_FS_48KHZ, AIF1_FS);
    399 	WR4(sc, SYS_SR_CTRL, val);
    400 
    401 	/* Set AIF1 to 16-bit */
    402 	val = RD4(sc, AIF1CLK_CTRL);
    403 	val &= ~AIF1_WORD_SIZ;
    404 	val |= __SHIFTIN(AIF1_WORD_SIZ_16, AIF1_WORD_SIZ);
    405 	WR4(sc, AIF1CLK_CTRL, val);
    406 
    407 	/* Enable AIF1 DAC timelot 0 */
    408 	val = RD4(sc, AIF1_DACDAT_CTRL);
    409 	val |= AIF1_DAC0L_ENA;
    410 	val |= AIF1_DAC0R_ENA;
    411 	WR4(sc, AIF1_DACDAT_CTRL, val);
    412 
    413 	/* DAC mixer source select */
    414 	val = RD4(sc, DAC_MXR_SRC);
    415 	val &= ~DACL_MXR_SRC;
    416 	val |= __SHIFTIN(DACL_MXR_SRC_AIF1_DAC0L, DACL_MXR_SRC);
    417 	val &= ~DACR_MXR_SRC;
    418 	val |= __SHIFTIN(DACR_MXR_SRC_AIF1_DAC0R, DACR_MXR_SRC);
    419 	WR4(sc, DAC_MXR_SRC, val);
    420 
    421 	/* Enable PA power */
    422 	sc->sc_pin_pa = fdtbus_gpio_acquire(phandle, "allwinner,pa-gpios", GPIO_PIN_OUTPUT);
    423 	if (sc->sc_pin_pa)
    424 		fdtbus_gpio_write(sc->sc_pin_pa, 1);
    425 
    426 	/* Enable jack detect */
    427 	val = RD4(sc, HMIC_CTRL1);
    428 	val |= __SHIFTIN(0xff, HMIC_CTRL1_N);
    429 	WR4(sc, HMIC_CTRL1, val);
    430 
    431 	val = RD4(sc, HMIC_CTRL2);
    432 	val &= ~HMIC_CTRL2_MDATA_THRES;
    433 	val |= __SHIFTIN(0x17, HMIC_CTRL2_MDATA_THRES);
    434 	WR4(sc, HMIC_CTRL2, val);
    435 
    436 	/* Schedule initial jack detect task */
    437 	workqueue_enqueue(sc->sc_workq, &sc->sc_work, NULL);
    438 
    439 	ih = fdtbus_intr_establish(phandle, 0, IPL_VM, FDT_INTR_MPSAFE,
    440 	    sun8i_codec_intr, sc);
    441 	if (ih == NULL) {
    442 		aprint_error_dev(self, "couldn't establish interrupt on %s\n",
    443 		    intrstr);
    444 		return;
    445 	}
    446 	aprint_normal_dev(self, "interrupting on %s\n", intrstr);
    447 
    448 	sc->sc_dai.dai_set_format = sun8i_codec_dai_set_format;
    449 	sc->sc_dai.dai_add_device = sun8i_codec_dai_add_device;
    450 	sc->sc_dai.dai_hw_if = &sun8i_codec_hw_if;
    451 	sc->sc_dai.dai_dev = self;
    452 	sc->sc_dai.dai_priv = sc;
    453 	fdtbus_register_dai_controller(self, phandle, &sun8i_codec_dai_funcs);
    454 }
    455 
    456 CFATTACH_DECL_NEW(sun8i_codec, sizeof(struct sun8i_codec_softc),
    457     sun8i_codec_match, sun8i_codec_attach, NULL, NULL);
    458