sun8i_codec.c revision 1.3
1 /* $NetBSD: sun8i_codec.c,v 1.3 2018/05/11 23:05:41 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: sun8i_codec.c,v 1.3 2018/05/11 23:05:41 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/cpu.h> 35 #include <sys/device.h> 36 #include <sys/kmem.h> 37 #include <sys/bitops.h> 38 #include <sys/gpio.h> 39 #include <sys/workqueue.h> 40 41 #include <dev/audio_dai.h> 42 43 #include <dev/fdt/fdtvar.h> 44 45 #define SYSCLK_CTL 0x00c 46 #define AIF1CLK_ENA __BIT(11) 47 #define AIF1CLK_SRC __BITS(9,8) 48 #define AIF1CLK_SRC_PLL 2 49 #define SYSCLK_ENA __BIT(3) 50 #define SYSCLK_SRC __BIT(0) 51 52 #define MOD_CLK_ENA 0x010 53 #define MOD_RST_CTL 0x014 54 #define MOD_AIF1 __BIT(15) 55 #define MOD_ADC __BIT(3) 56 #define MOD_DAC __BIT(2) 57 58 #define SYS_SR_CTRL 0x018 59 #define AIF1_FS __BITS(15,12) 60 #define AIF_FS_48KHZ 8 61 62 #define AIF1CLK_CTRL 0x040 63 #define AIF1_MSTR_MOD __BIT(15) 64 #define AIF1_BCLK_INV __BIT(14) 65 #define AIF1_LRCK_INV __BIT(13) 66 #define AIF1_BCLK_DIV __BITS(12,9) 67 #define AIF1_BCLK_DIV_16 6 68 #define AIF1_LRCK_DIV __BITS(8,6) 69 #define AIF1_LRCK_DIV_16 0 70 #define AIF1_LRCK_DIV_64 2 71 #define AIF1_WORD_SIZ __BITS(5,4) 72 #define AIF1_WORD_SIZ_16 1 73 #define AIF1_DATA_FMT __BITS(3,2) 74 #define AIF1_DATA_FMT_I2S 0 75 #define AIF1_DATA_FMT_LJ 1 76 #define AIF1_DATA_FMT_RJ 2 77 #define AIF1_DATA_FMT_DSP 3 78 79 #define AIF1_DACDAT_CTRL 0x048 80 #define AIF1_DAC0L_ENA __BIT(15) 81 #define AIF1_DAC0R_ENA __BIT(14) 82 83 #define ADC_DIG_CTRL 0x100 84 #define ADC_DIG_CTRL_ENAD __BIT(15) 85 86 #define HMIC_CTRL1 0x110 87 #define HMIC_CTRL1_N __BITS(11,8) 88 #define HMIC_CTRL1_JACK_IN_IRQ_EN __BIT(4) 89 #define HMIC_CTRL1_JACK_OUT_IRQ_EN __BIT(3) 90 #define HMIC_CTRL1_MIC_DET_IRQ_EN __BIT(0) 91 92 #define HMIC_CTRL2 0x114 93 #define HMIC_CTRL2_MDATA_THRES __BITS(12,8) 94 95 #define HMIC_STS 0x118 96 #define HMIC_STS_MIC_PRESENT __BIT(6) 97 #define HMIC_STS_JACK_DET_OIRQ __BIT(4) 98 #define HMIC_STS_JACK_DET_IIRQ __BIT(3) 99 #define HMIC_STS_MIC_DET_ST __BIT(0) 100 101 #define DAC_DIG_CTRL 0x120 102 #define DAC_DIG_CTRL_ENDA __BIT(15) 103 104 #define DAC_MXR_SRC 0x130 105 #define DACL_MXR_SRC __BITS(15,12) 106 #define DACL_MXR_SRC_AIF1_DAC0L 0x8 107 #define DACR_MXR_SRC __BITS(11,8) 108 #define DACR_MXR_SRC_AIF1_DAC0R 0x8 109 110 struct sun8i_codec_softc { 111 device_t sc_dev; 112 bus_space_tag_t sc_bst; 113 bus_space_handle_t sc_bsh; 114 int sc_phandle; 115 116 struct workqueue *sc_workq; 117 struct work sc_work; 118 119 struct audio_dai_device sc_dai; 120 audio_dai_tag_t sc_codec_analog; 121 int sc_jackdet_pol; 122 123 struct fdtbus_gpio_pin *sc_pin_pa; 124 125 struct clk *sc_clk_gate; 126 struct clk *sc_clk_mod; 127 }; 128 129 #define RD4(sc, reg) \ 130 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 131 #define WR4(sc, reg, val) \ 132 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 133 134 static int 135 sun8i_codec_set_params(void *priv, int setmode, int usemode, 136 audio_params_t *play, audio_params_t *rec, 137 stream_filter_list_t *pfil, stream_filter_list_t *rfil) 138 { 139 if (play && (setmode & AUMODE_PLAY)) 140 if (play->sample_rate != 48000) 141 return EINVAL; 142 143 if (rec && (setmode & AUMODE_RECORD)) 144 if (rec->sample_rate != 48000) 145 return EINVAL; 146 147 return 0; 148 } 149 150 static const struct audio_hw_if sun8i_codec_hw_if = { 151 .set_params = sun8i_codec_set_params, 152 }; 153 154 static audio_dai_tag_t 155 sun8i_codec_dai_get_tag(device_t dev, const void *data, size_t len) 156 { 157 struct sun8i_codec_softc * const sc = device_private(dev); 158 159 if (len != 4) 160 return NULL; 161 162 return &sc->sc_dai; 163 } 164 165 static struct fdtbus_dai_controller_func sun8i_codec_dai_funcs = { 166 .get_tag = sun8i_codec_dai_get_tag 167 }; 168 169 static int 170 sun8i_codec_dai_set_format(audio_dai_tag_t dai, u_int format) 171 { 172 struct sun8i_codec_softc * const sc = audio_dai_private(dai); 173 uint32_t val; 174 175 const u_int fmt = __SHIFTOUT(format, AUDIO_DAI_FORMAT_MASK); 176 const u_int pol = __SHIFTOUT(format, AUDIO_DAI_POLARITY_MASK); 177 const u_int clk = __SHIFTOUT(format, AUDIO_DAI_CLOCK_MASK); 178 179 val = RD4(sc, AIF1CLK_CTRL); 180 181 val &= ~AIF1_DATA_FMT; 182 switch (fmt) { 183 case AUDIO_DAI_FORMAT_I2S: 184 val |= __SHIFTIN(AIF1_DATA_FMT_I2S, AIF1_DATA_FMT); 185 break; 186 case AUDIO_DAI_FORMAT_RJ: 187 val |= __SHIFTIN(AIF1_DATA_FMT_RJ, AIF1_DATA_FMT); 188 break; 189 case AUDIO_DAI_FORMAT_LJ: 190 val |= __SHIFTIN(AIF1_DATA_FMT_LJ, AIF1_DATA_FMT); 191 break; 192 case AUDIO_DAI_FORMAT_DSPA: 193 case AUDIO_DAI_FORMAT_DSPB: 194 val |= __SHIFTIN(AIF1_DATA_FMT_DSP, AIF1_DATA_FMT); 195 break; 196 default: 197 return EINVAL; 198 } 199 200 val &= ~(AIF1_BCLK_INV|AIF1_LRCK_INV); 201 /* Codec LRCK polarity is inverted (datasheet is wrong) */ 202 if (!AUDIO_DAI_POLARITY_F(pol)) 203 val |= AIF1_LRCK_INV; 204 if (AUDIO_DAI_POLARITY_B(pol)) 205 val |= AIF1_BCLK_INV; 206 207 switch (clk) { 208 case AUDIO_DAI_CLOCK_CBM_CFM: 209 val &= ~AIF1_MSTR_MOD; /* codec is master */ 210 break; 211 case AUDIO_DAI_CLOCK_CBS_CFS: 212 val |= AIF1_MSTR_MOD; /* codec is slave */ 213 break; 214 default: 215 return EINVAL; 216 } 217 218 val &= ~AIF1_LRCK_DIV; 219 val |= __SHIFTIN(AIF1_LRCK_DIV_64, AIF1_LRCK_DIV); 220 221 val &= ~AIF1_BCLK_DIV; 222 val |= __SHIFTIN(AIF1_BCLK_DIV_16, AIF1_BCLK_DIV); 223 224 WR4(sc, AIF1CLK_CTRL, val); 225 226 return 0; 227 } 228 229 static int 230 sun8i_codec_dai_add_device(audio_dai_tag_t dai, audio_dai_tag_t aux) 231 { 232 struct sun8i_codec_softc * const sc = audio_dai_private(dai); 233 234 if (sc->sc_codec_analog != NULL) 235 return 0; 236 237 sc->sc_codec_analog = aux; 238 239 return 0; 240 } 241 242 static void 243 sun8i_codec_set_jackdet(struct sun8i_codec_softc *sc, bool enable) 244 { 245 const uint32_t mask = 246 HMIC_CTRL1_JACK_IN_IRQ_EN | 247 HMIC_CTRL1_JACK_OUT_IRQ_EN | 248 HMIC_CTRL1_MIC_DET_IRQ_EN; 249 uint32_t val; 250 251 val = RD4(sc, HMIC_CTRL1); 252 if (enable) 253 val |= mask; 254 else 255 val &= ~mask; 256 WR4(sc, HMIC_CTRL1, val); 257 } 258 259 static int 260 sun8i_codec_intr(void *priv) 261 { 262 const uint32_t mask = 263 HMIC_STS_JACK_DET_OIRQ | 264 HMIC_STS_JACK_DET_IIRQ | 265 HMIC_STS_MIC_DET_ST; 266 struct sun8i_codec_softc * const sc = priv; 267 uint32_t val; 268 269 val = RD4(sc, HMIC_STS); 270 if (val & mask) { 271 /* Disable jack detect IRQ until work is complete */ 272 sun8i_codec_set_jackdet(sc, false); 273 274 /* Schedule pending jack detect task */ 275 workqueue_enqueue(sc->sc_workq, &sc->sc_work, NULL); 276 } 277 278 return 1; 279 } 280 281 282 static void 283 sun8i_codec_thread(struct work *wk, void *priv) 284 { 285 struct sun8i_codec_softc * const sc = priv; 286 int hpdet = -1, micdet = -1; 287 uint32_t val; 288 289 val = RD4(sc, HMIC_STS); 290 291 if (sc->sc_codec_analog) { 292 if (val & HMIC_STS_JACK_DET_OIRQ) 293 hpdet = 0 ^ sc->sc_jackdet_pol; 294 else if (val & HMIC_STS_JACK_DET_IIRQ) 295 hpdet = 1 ^ sc->sc_jackdet_pol; 296 297 if (val & HMIC_STS_MIC_DET_ST) 298 micdet = !!(val & HMIC_STS_MIC_PRESENT); 299 300 if (hpdet != -1) { 301 audio_dai_jack_detect(sc->sc_codec_analog, 302 AUDIO_DAI_JACK_HP, hpdet); 303 } 304 if (micdet != -1) { 305 audio_dai_jack_detect(sc->sc_codec_analog, 306 AUDIO_DAI_JACK_MIC, micdet); 307 } 308 } 309 310 WR4(sc, HMIC_STS, val); 311 312 /* Re-enable jack detect IRQ */ 313 sun8i_codec_set_jackdet(sc, true); 314 } 315 316 static const char * compatible[] = { 317 "allwinner,sun50i-a64-codec", 318 NULL 319 }; 320 321 static int 322 sun8i_codec_match(device_t parent, cfdata_t cf, void *aux) 323 { 324 struct fdt_attach_args * const faa = aux; 325 326 return of_match_compatible(faa->faa_phandle, compatible); 327 } 328 329 static void 330 sun8i_codec_attach(device_t parent, device_t self, void *aux) 331 { 332 struct sun8i_codec_softc * const sc = device_private(self); 333 struct fdt_attach_args * const faa = aux; 334 const int phandle = faa->faa_phandle; 335 char intrstr[128]; 336 bus_addr_t addr; 337 bus_size_t size; 338 uint32_t val; 339 void *ih; 340 341 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 342 aprint_error(": couldn't get registers\n"); 343 return; 344 } 345 346 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 347 aprint_error(": couldn't decode interrupt\n"); 348 return; 349 } 350 351 sc->sc_dev = self; 352 sc->sc_bst = faa->faa_bst; 353 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 354 aprint_error(": couldn't map registers\n"); 355 return; 356 } 357 sc->sc_jackdet_pol = 1; 358 359 sc->sc_clk_gate = fdtbus_clock_get(phandle, "bus"); 360 sc->sc_clk_mod = fdtbus_clock_get(phandle, "mod"); 361 if (!sc->sc_clk_gate || !sc->sc_clk_mod) { 362 aprint_error(": couldn't get clocks\n"); 363 return; 364 } 365 if (clk_enable(sc->sc_clk_gate) != 0) { 366 aprint_error(": couldn't enable bus clock\n"); 367 return; 368 } 369 370 sc->sc_phandle = phandle; 371 372 aprint_naive("\n"); 373 aprint_normal(": Audio Codec\n"); 374 375 if (workqueue_create(&sc->sc_workq, "jackdet", sun8i_codec_thread, 376 sc, PRI_NONE, IPL_VM, 0) != 0) { 377 aprint_error_dev(self, "couldn't create jackdet workqueue\n"); 378 return; 379 } 380 381 /* Enable clocks */ 382 val = RD4(sc, SYSCLK_CTL); 383 val |= AIF1CLK_ENA; 384 val &= ~AIF1CLK_SRC; 385 val |= __SHIFTIN(AIF1CLK_SRC_PLL, AIF1CLK_SRC); 386 val |= SYSCLK_ENA; 387 val &= ~SYSCLK_SRC; 388 WR4(sc, SYSCLK_CTL, val); 389 WR4(sc, MOD_CLK_ENA, MOD_AIF1 | MOD_ADC | MOD_DAC); 390 WR4(sc, MOD_RST_CTL, MOD_AIF1 | MOD_ADC | MOD_DAC); 391 392 /* Enable digital parts */ 393 WR4(sc, DAC_DIG_CTRL, DAC_DIG_CTRL_ENDA); 394 WR4(sc, ADC_DIG_CTRL, ADC_DIG_CTRL_ENAD); 395 396 /* Set AIF1 to 48 kHz */ 397 val = RD4(sc, SYS_SR_CTRL); 398 val &= ~AIF1_FS; 399 val |= __SHIFTIN(AIF_FS_48KHZ, AIF1_FS); 400 WR4(sc, SYS_SR_CTRL, val); 401 402 /* Set AIF1 to 16-bit */ 403 val = RD4(sc, AIF1CLK_CTRL); 404 val &= ~AIF1_WORD_SIZ; 405 val |= __SHIFTIN(AIF1_WORD_SIZ_16, AIF1_WORD_SIZ); 406 WR4(sc, AIF1CLK_CTRL, val); 407 408 /* Enable AIF1 DAC timelot 0 */ 409 val = RD4(sc, AIF1_DACDAT_CTRL); 410 val |= AIF1_DAC0L_ENA; 411 val |= AIF1_DAC0R_ENA; 412 WR4(sc, AIF1_DACDAT_CTRL, val); 413 414 /* DAC mixer source select */ 415 val = RD4(sc, DAC_MXR_SRC); 416 val &= ~DACL_MXR_SRC; 417 val |= __SHIFTIN(DACL_MXR_SRC_AIF1_DAC0L, DACL_MXR_SRC); 418 val &= ~DACR_MXR_SRC; 419 val |= __SHIFTIN(DACR_MXR_SRC_AIF1_DAC0R, DACR_MXR_SRC); 420 WR4(sc, DAC_MXR_SRC, val); 421 422 /* Enable PA power */ 423 sc->sc_pin_pa = fdtbus_gpio_acquire(phandle, "allwinner,pa-gpios", GPIO_PIN_OUTPUT); 424 if (sc->sc_pin_pa) 425 fdtbus_gpio_write(sc->sc_pin_pa, 1); 426 427 /* Enable jack detect */ 428 val = RD4(sc, HMIC_CTRL1); 429 val |= __SHIFTIN(0xff, HMIC_CTRL1_N); 430 WR4(sc, HMIC_CTRL1, val); 431 432 val = RD4(sc, HMIC_CTRL2); 433 val &= ~HMIC_CTRL2_MDATA_THRES; 434 val |= __SHIFTIN(0x17, HMIC_CTRL2_MDATA_THRES); 435 WR4(sc, HMIC_CTRL2, val); 436 437 /* Schedule initial jack detect task */ 438 workqueue_enqueue(sc->sc_workq, &sc->sc_work, NULL); 439 440 ih = fdtbus_intr_establish(phandle, 0, IPL_VM, FDT_INTR_MPSAFE, 441 sun8i_codec_intr, sc); 442 if (ih == NULL) { 443 aprint_error_dev(self, "couldn't establish interrupt on %s\n", 444 intrstr); 445 return; 446 } 447 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 448 449 sc->sc_dai.dai_set_format = sun8i_codec_dai_set_format; 450 sc->sc_dai.dai_add_device = sun8i_codec_dai_add_device; 451 sc->sc_dai.dai_hw_if = &sun8i_codec_hw_if; 452 sc->sc_dai.dai_dev = self; 453 sc->sc_dai.dai_priv = sc; 454 fdtbus_register_dai_controller(self, phandle, &sun8i_codec_dai_funcs); 455 } 456 457 CFATTACH_DECL_NEW(sun8i_codec, sizeof(struct sun8i_codec_softc), 458 sun8i_codec_match, sun8i_codec_attach, NULL, NULL); 459
Indexes created Mon Sep 22 10:09:38 GMT 2025