sun8i_h3_ccu.c revision 1.11.2.2
1 1.11.2.2 skrll /* $NetBSD: sun8i_h3_ccu.c,v 1.11.2.2 2017/08/28 17:51:32 skrll Exp $ */ 2 1.11.2.2 skrll 3 1.11.2.2 skrll /*- 4 1.11.2.2 skrll * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 1.11.2.2 skrll * Copyright (c) 2017 Emmanuel Vadot <manu (at) freebsd.org> 6 1.11.2.2 skrll * All rights reserved. 7 1.11.2.2 skrll * 8 1.11.2.2 skrll * Redistribution and use in source and binary forms, with or without 9 1.11.2.2 skrll * modification, are permitted provided that the following conditions 10 1.11.2.2 skrll * are met: 11 1.11.2.2 skrll * 1. Redistributions of source code must retain the above copyright 12 1.11.2.2 skrll * notice, this list of conditions and the following disclaimer. 13 1.11.2.2 skrll * 2. Redistributions in binary form must reproduce the above copyright 14 1.11.2.2 skrll * notice, this list of conditions and the following disclaimer in the 15 1.11.2.2 skrll * documentation and/or other materials provided with the distribution. 16 1.11.2.2 skrll * 17 1.11.2.2 skrll * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 1.11.2.2 skrll * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 1.11.2.2 skrll * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 1.11.2.2 skrll * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 1.11.2.2 skrll * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 1.11.2.2 skrll * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 1.11.2.2 skrll * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 1.11.2.2 skrll * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 1.11.2.2 skrll * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 1.11.2.2 skrll * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 1.11.2.2 skrll * SUCH DAMAGE. 28 1.11.2.2 skrll */ 29 1.11.2.2 skrll 30 1.11.2.2 skrll #include <sys/cdefs.h> 31 1.11.2.2 skrll 32 1.11.2.2 skrll __KERNEL_RCSID(1, "$NetBSD: sun8i_h3_ccu.c,v 1.11.2.2 2017/08/28 17:51:32 skrll Exp $"); 33 1.11.2.2 skrll 34 1.11.2.2 skrll #include <sys/param.h> 35 1.11.2.2 skrll #include <sys/bus.h> 36 1.11.2.2 skrll #include <sys/device.h> 37 1.11.2.2 skrll #include <sys/systm.h> 38 1.11.2.2 skrll 39 1.11.2.2 skrll #include <dev/fdt/fdtvar.h> 40 1.11.2.2 skrll 41 1.11.2.2 skrll #include <arm/sunxi/sunxi_ccu.h> 42 1.11.2.2 skrll #include <arm/sunxi/sun8i_h3_ccu.h> 43 1.11.2.2 skrll 44 1.11.2.2 skrll #define PLL_CPUX_CTRL_REG 0x000 45 1.11.2.2 skrll #define PLL_AUDIO_CTRL_REG 0x008 46 1.11.2.2 skrll #define PLL_PERIPH0_CTRL_REG 0x028 47 1.11.2.2 skrll #define AHB1_APB1_CFG_REG 0x054 48 1.11.2.2 skrll #define APB2_CFG_REG 0x058 49 1.11.2.2 skrll #define AHB2_CFG_REG 0x05c 50 1.11.2.2 skrll #define AHB2_CLK_CFG __BITS(1,0) 51 1.11.2.2 skrll #define AHB2_CLK_CFG_PLL_PERIPH0_2 1 52 1.11.2.2 skrll #define BUS_CLK_GATING_REG0 0x060 53 1.11.2.2 skrll #define BUS_CLK_GATING_REG2 0x068 54 1.11.2.2 skrll #define BUS_CLK_GATING_REG3 0x06c 55 1.11.2.2 skrll #define SDMMC0_CLK_REG 0x088 56 1.11.2.2 skrll #define SDMMC1_CLK_REG 0x08c 57 1.11.2.2 skrll #define SDMMC2_CLK_REG 0x090 58 1.11.2.2 skrll #define USBPHY_CFG_REG 0x0cc 59 1.11.2.2 skrll #define MBUS_RST_REG 0x0fc 60 1.11.2.2 skrll #define AC_DIG_CLK_REG 0x140 61 1.11.2.2 skrll #define BUS_SOFT_RST_REG0 0x2c0 62 1.11.2.2 skrll #define BUS_SOFT_RST_REG1 0x2c4 63 1.11.2.2 skrll #define BUS_SOFT_RST_REG2 0x2c8 64 1.11.2.2 skrll #define BUS_SOFT_RST_REG3 0x2d0 65 1.11.2.2 skrll #define BUS_SOFT_RST_REG4 0x2d8 66 1.11.2.2 skrll 67 1.11.2.2 skrll static int sun8i_h3_ccu_match(device_t, cfdata_t, void *); 68 1.11.2.2 skrll static void sun8i_h3_ccu_attach(device_t, device_t, void *); 69 1.11.2.2 skrll 70 1.11.2.2 skrll static const char * const compatible[] = { 71 1.11.2.2 skrll "allwinner,sun8i-h3-ccu", 72 1.11.2.2 skrll NULL 73 1.11.2.2 skrll }; 74 1.11.2.2 skrll 75 1.11.2.2 skrll CFATTACH_DECL_NEW(sunxi_h3_ccu, sizeof(struct sunxi_ccu_softc), 76 1.11.2.2 skrll sun8i_h3_ccu_match, sun8i_h3_ccu_attach, NULL, NULL); 77 1.11.2.2 skrll 78 1.11.2.2 skrll static struct sunxi_ccu_reset sun8i_h3_ccu_resets[] = { 79 1.11.2.2 skrll SUNXI_CCU_RESET(H3_RST_USB_PHY0, USBPHY_CFG_REG, 0), 80 1.11.2.2 skrll SUNXI_CCU_RESET(H3_RST_USB_PHY1, USBPHY_CFG_REG, 1), 81 1.11.2.2 skrll SUNXI_CCU_RESET(H3_RST_USB_PHY2, USBPHY_CFG_REG, 2), 82 1.11.2.2 skrll SUNXI_CCU_RESET(H3_RST_USB_PHY3, USBPHY_CFG_REG, 3), 83 1.11.2.2 skrll 84 1.11.2.2 skrll SUNXI_CCU_RESET(H3_RST_MBUS, MBUS_RST_REG, 31), 85 1.11.2.2 skrll 86 1.11.2.2 skrll SUNXI_CCU_RESET(H3_RST_BUS_CE, BUS_SOFT_RST_REG0, 5), 87 1.11.2.2 skrll SUNXI_CCU_RESET(H3_RST_BUS_DMA, BUS_SOFT_RST_REG0, 6), 88 1.11.2.2 skrll SUNXI_CCU_RESET(H3_RST_BUS_MMC0, BUS_SOFT_RST_REG0, 8), 89 1.11.2.2 skrll SUNXI_CCU_RESET(H3_RST_BUS_MMC1, BUS_SOFT_RST_REG0, 9), 90 1.11.2.2 skrll SUNXI_CCU_RESET(H3_RST_BUS_MMC2, BUS_SOFT_RST_REG0, 10), 91 1.11.2.2 skrll SUNXI_CCU_RESET(H3_RST_BUS_NAND, BUS_SOFT_RST_REG0, 13), 92 1.11.2.2 skrll SUNXI_CCU_RESET(H3_RST_BUS_DRAM, BUS_SOFT_RST_REG0, 14), 93 1.11.2.2 skrll SUNXI_CCU_RESET(H3_RST_BUS_EMAC, BUS_SOFT_RST_REG0, 17), 94 1.11.2.2 skrll SUNXI_CCU_RESET(H3_RST_BUS_TS, BUS_SOFT_RST_REG0, 18), 95 1.11.2.2 skrll SUNXI_CCU_RESET(H3_RST_BUS_HSTIMER, BUS_SOFT_RST_REG0, 19), 96 1.11.2.2 skrll SUNXI_CCU_RESET(H3_RST_BUS_SPI0, BUS_SOFT_RST_REG0, 20), 97 1.11.2.2 skrll SUNXI_CCU_RESET(H3_RST_BUS_SPI1, BUS_SOFT_RST_REG0, 21), 98 1.11.2.2 skrll SUNXI_CCU_RESET(H3_RST_BUS_OTG, BUS_SOFT_RST_REG0, 23), 99 1.11.2.2 skrll SUNXI_CCU_RESET(H3_RST_BUS_EHCI0, BUS_SOFT_RST_REG0, 24), 100 1.11.2.2 skrll SUNXI_CCU_RESET(H3_RST_BUS_EHCI1, BUS_SOFT_RST_REG0, 25), 101 1.11.2.2 skrll SUNXI_CCU_RESET(H3_RST_BUS_EHCI2, BUS_SOFT_RST_REG0, 26), 102 1.11.2.2 skrll SUNXI_CCU_RESET(H3_RST_BUS_EHCI3, BUS_SOFT_RST_REG0, 27), 103 1.11.2.2 skrll SUNXI_CCU_RESET(H3_RST_BUS_OHCI0, BUS_SOFT_RST_REG0, 28), 104 1.11.2.2 skrll SUNXI_CCU_RESET(H3_RST_BUS_OHCI1, BUS_SOFT_RST_REG0, 29), 105 1.11.2.2 skrll SUNXI_CCU_RESET(H3_RST_BUS_OHCI2, BUS_SOFT_RST_REG0, 30), 106 1.11.2.2 skrll SUNXI_CCU_RESET(H3_RST_BUS_OHCI3, BUS_SOFT_RST_REG0, 31), 107 1.11.2.2 skrll 108 1.11.2.2 skrll SUNXI_CCU_RESET(H3_RST_BUS_VE, BUS_SOFT_RST_REG1, 0), 109 1.11.2.2 skrll SUNXI_CCU_RESET(H3_RST_BUS_TCON0, BUS_SOFT_RST_REG1, 3), 110 1.11.2.2 skrll SUNXI_CCU_RESET(H3_RST_BUS_TCON1, BUS_SOFT_RST_REG1, 4), 111 1.11.2.2 skrll SUNXI_CCU_RESET(H3_RST_BUS_DEINTERLACE, BUS_SOFT_RST_REG1, 5), 112 1.11.2.2 skrll SUNXI_CCU_RESET(H3_RST_BUS_CSI, BUS_SOFT_RST_REG1, 8), 113 1.11.2.2 skrll SUNXI_CCU_RESET(H3_RST_BUS_TVE, BUS_SOFT_RST_REG1, 9), 114 1.11.2.2 skrll SUNXI_CCU_RESET(H3_RST_BUS_HDMI0, BUS_SOFT_RST_REG1, 10), 115 1.11.2.2 skrll SUNXI_CCU_RESET(H3_RST_BUS_HDMI1, BUS_SOFT_RST_REG1, 11), 116 1.11.2.2 skrll SUNXI_CCU_RESET(H3_RST_BUS_DE, BUS_SOFT_RST_REG1, 12), 117 1.11.2.2 skrll SUNXI_CCU_RESET(H3_RST_BUS_GPU, BUS_SOFT_RST_REG1, 20), 118 1.11.2.2 skrll SUNXI_CCU_RESET(H3_RST_BUS_MSGBOX, BUS_SOFT_RST_REG1, 21), 119 1.11.2.2 skrll SUNXI_CCU_RESET(H3_RST_BUS_SPINLOCK, BUS_SOFT_RST_REG1, 22), 120 1.11.2.2 skrll SUNXI_CCU_RESET(H3_RST_BUS_DBG, BUS_SOFT_RST_REG1, 31), 121 1.11.2.2 skrll 122 1.11.2.2 skrll SUNXI_CCU_RESET(H3_RST_BUS_EPHY, BUS_SOFT_RST_REG2, 2), 123 1.11.2.2 skrll 124 1.11.2.2 skrll SUNXI_CCU_RESET(H3_RST_BUS_CODEC, BUS_SOFT_RST_REG3, 0), 125 1.11.2.2 skrll SUNXI_CCU_RESET(H3_RST_BUS_SPDIF, BUS_SOFT_RST_REG3, 1), 126 1.11.2.2 skrll SUNXI_CCU_RESET(H3_RST_BUS_THS, BUS_SOFT_RST_REG3, 8), 127 1.11.2.2 skrll SUNXI_CCU_RESET(H3_RST_BUS_I2S0, BUS_SOFT_RST_REG3, 12), 128 1.11.2.2 skrll SUNXI_CCU_RESET(H3_RST_BUS_I2S1, BUS_SOFT_RST_REG3, 13), 129 1.11.2.2 skrll SUNXI_CCU_RESET(H3_RST_BUS_I2S2, BUS_SOFT_RST_REG3, 14), 130 1.11.2.2 skrll 131 1.11.2.2 skrll SUNXI_CCU_RESET(H3_RST_BUS_I2C0, BUS_SOFT_RST_REG4, 0), 132 1.11.2.2 skrll SUNXI_CCU_RESET(H3_RST_BUS_I2C1, BUS_SOFT_RST_REG4, 1), 133 1.11.2.2 skrll SUNXI_CCU_RESET(H3_RST_BUS_I2C2, BUS_SOFT_RST_REG4, 2), 134 1.11.2.2 skrll SUNXI_CCU_RESET(H3_RST_BUS_UART0, BUS_SOFT_RST_REG4, 16), 135 1.11.2.2 skrll SUNXI_CCU_RESET(H3_RST_BUS_UART1, BUS_SOFT_RST_REG4, 17), 136 1.11.2.2 skrll SUNXI_CCU_RESET(H3_RST_BUS_UART2, BUS_SOFT_RST_REG4, 18), 137 1.11.2.2 skrll SUNXI_CCU_RESET(H3_RST_BUS_UART3, BUS_SOFT_RST_REG4, 19), 138 1.11.2.2 skrll SUNXI_CCU_RESET(H3_RST_BUS_SCR, BUS_SOFT_RST_REG4, 20), 139 1.11.2.2 skrll }; 140 1.11.2.2 skrll 141 1.11.2.2 skrll static const char *ahb1_parents[] = { "losc", "hosc", "axi", "pll_periph0" }; 142 1.11.2.2 skrll static const char *ahb2_parents[] = { "ahb1", "pll_periph0" }; 143 1.11.2.2 skrll static const char *apb1_parents[] = { "ahb1" }; 144 1.11.2.2 skrll static const char *apb2_parents[] = { "losc", "hosc", "pll_periph0" }; 145 1.11.2.2 skrll static const char *mod_parents[] = { "hosc", "pll_periph0", "pll_periph1" }; 146 1.11.2.2 skrll 147 1.11.2.2 skrll static const struct sunxi_ccu_nkmp_tbl sun8i_h3_cpux_table[] = { 148 1.11.2.2 skrll { 60000000, 9, 0, 0, 2 }, 149 1.11.2.2 skrll { 66000000, 10, 0, 0, 2 }, 150 1.11.2.2 skrll { 72000000, 11, 0, 0, 2 }, 151 1.11.2.2 skrll { 78000000, 12, 0, 0, 2 }, 152 1.11.2.2 skrll { 84000000, 13, 0, 0, 2 }, 153 1.11.2.2 skrll { 90000000, 14, 0, 0, 2 }, 154 1.11.2.2 skrll { 96000000, 15, 0, 0, 2 }, 155 1.11.2.2 skrll { 102000000, 16, 0, 0, 2 }, 156 1.11.2.2 skrll { 108000000, 17, 0, 0, 2 }, 157 1.11.2.2 skrll { 114000000, 18, 0, 0, 2 }, 158 1.11.2.2 skrll { 120000000, 9, 0, 0, 1 }, 159 1.11.2.2 skrll { 132000000, 10, 0, 0, 1 }, 160 1.11.2.2 skrll { 144000000, 11, 0, 0, 1 }, 161 1.11.2.2 skrll { 156000000, 12, 0, 0, 1 }, 162 1.11.2.2 skrll { 168000000, 13, 0, 0, 1 }, 163 1.11.2.2 skrll { 180000000, 14, 0, 0, 1 }, 164 1.11.2.2 skrll { 192000000, 15, 0, 0, 1 }, 165 1.11.2.2 skrll { 204000000, 16, 0, 0, 1 }, 166 1.11.2.2 skrll { 216000000, 17, 0, 0, 1 }, 167 1.11.2.2 skrll { 228000000, 18, 0, 0, 1 }, 168 1.11.2.2 skrll { 240000000, 9, 0, 0, 0 }, 169 1.11.2.2 skrll { 264000000, 10, 0, 0, 0 }, 170 1.11.2.2 skrll { 288000000, 11, 0, 0, 0 }, 171 1.11.2.2 skrll { 312000000, 12, 0, 0, 0 }, 172 1.11.2.2 skrll { 336000000, 13, 0, 0, 0 }, 173 1.11.2.2 skrll { 360000000, 14, 0, 0, 0 }, 174 1.11.2.2 skrll { 384000000, 15, 0, 0, 0 }, 175 1.11.2.2 skrll { 408000000, 16, 0, 0, 0 }, 176 1.11.2.2 skrll { 432000000, 17, 0, 0, 0 }, 177 1.11.2.2 skrll { 456000000, 18, 0, 0, 0 }, 178 1.11.2.2 skrll { 480000000, 19, 0, 0, 0 }, 179 1.11.2.2 skrll { 504000000, 20, 0, 0, 0 }, 180 1.11.2.2 skrll { 528000000, 21, 0, 0, 0 }, 181 1.11.2.2 skrll { 552000000, 22, 0, 0, 0 }, 182 1.11.2.2 skrll { 576000000, 23, 0, 0, 0 }, 183 1.11.2.2 skrll { 600000000, 24, 0, 0, 0 }, 184 1.11.2.2 skrll { 624000000, 25, 0, 0, 0 }, 185 1.11.2.2 skrll { 648000000, 26, 0, 0, 0 }, 186 1.11.2.2 skrll { 672000000, 27, 0, 0, 0 }, 187 1.11.2.2 skrll { 696000000, 28, 0, 0, 0 }, 188 1.11.2.2 skrll { 720000000, 29, 0, 0, 0 }, 189 1.11.2.2 skrll { 768000000, 15, 1, 0, 0 }, 190 1.11.2.2 skrll { 792000000, 10, 2, 0, 0 }, 191 1.11.2.2 skrll { 816000000, 16, 1, 0, 0 }, 192 1.11.2.2 skrll { 864000000, 17, 1, 0, 0 }, 193 1.11.2.2 skrll { 912000000, 18, 1, 0, 0 }, 194 1.11.2.2 skrll { 936000000, 12, 2, 0, 0 }, 195 1.11.2.2 skrll { 960000000, 19, 1, 0, 0 }, 196 1.11.2.2 skrll { 1008000000, 20, 1, 0, 0 }, 197 1.11.2.2 skrll { 1056000000, 21, 1, 0, 0 }, 198 1.11.2.2 skrll { 1080000000, 14, 2, 0, 0 }, 199 1.11.2.2 skrll { 1104000000, 22, 1, 0, 0 }, 200 1.11.2.2 skrll { 1152000000, 23, 1, 0, 0 }, 201 1.11.2.2 skrll { 1200000000, 24, 1, 0, 0 }, 202 1.11.2.2 skrll { 1224000000, 16, 2, 0, 0 }, 203 1.11.2.2 skrll { 1248000000, 25, 1, 0, 0 }, 204 1.11.2.2 skrll { 1296000000, 26, 1, 0, 0 }, 205 1.11.2.2 skrll { 1344000000, 27, 1, 0, 0 }, 206 1.11.2.2 skrll { 1368000000, 18, 2, 0, 0 }, 207 1.11.2.2 skrll { 1392000000, 28, 1, 0, 0 }, 208 1.11.2.2 skrll { 1440000000, 29, 1, 0, 0 }, 209 1.11.2.2 skrll { 1512000000, 20, 2, 0, 0 }, 210 1.11.2.2 skrll { 1536000000, 15, 3, 0, 0 }, 211 1.11.2.2 skrll { 1584000000, 21, 2, 0, 0 }, 212 1.11.2.2 skrll { 1632000000, 16, 3, 0, 0 }, 213 1.11.2.2 skrll { 1656000000, 22, 2, 0, 0 }, 214 1.11.2.2 skrll { 1728000000, 23, 2, 0, 0 }, 215 1.11.2.2 skrll { 1800000000, 24, 2, 0, 0 }, 216 1.11.2.2 skrll { 1824000000, 18, 3, 0, 0 }, 217 1.11.2.2 skrll { 1872000000, 25, 2, 0, 0 }, 218 1.11.2.2 skrll { 0 } 219 1.11.2.2 skrll }; 220 1.11.2.2 skrll 221 1.11.2.2 skrll static const struct sunxi_ccu_nkmp_tbl sun8i_h3_ac_dig_table[] = { 222 1.11.2.2 skrll { 24576000, 13, 0, 0, 13 }, 223 1.11.2.2 skrll { 0 } 224 1.11.2.2 skrll }; 225 1.11.2.2 skrll 226 1.11.2.2 skrll static struct sunxi_ccu_clk sun8i_h3_ccu_clks[] = { 227 1.11.2.2 skrll SUNXI_CCU_NKMP_TABLE(H3_CLK_CPUX, "pll_cpux", "hosc", 228 1.11.2.2 skrll PLL_CPUX_CTRL_REG, /* reg */ 229 1.11.2.2 skrll __BITS(12,8), /* n */ 230 1.11.2.2 skrll __BITS(5,4), /* k */ 231 1.11.2.2 skrll __BITS(1,0), /* m */ 232 1.11.2.2 skrll __BITS(17,16), /* p */ 233 1.11.2.2 skrll __BIT(31), /* enable */ 234 1.11.2.2 skrll __BIT(28), /* lock */ 235 1.11.2.2 skrll sun8i_h3_cpux_table, /* table */ 236 1.11.2.2 skrll SUNXI_CCU_NKMP_SCALE_CLOCK | SUNXI_CCU_NKMP_FACTOR_P_POW2), 237 1.11.2.2 skrll 238 1.11.2.2 skrll SUNXI_CCU_NKMP(H3_CLK_PLL_PERIPH0, "pll_periph0", "hosc", 239 1.11.2.2 skrll PLL_PERIPH0_CTRL_REG, /* reg */ 240 1.11.2.2 skrll __BITS(12,8), /* n */ 241 1.11.2.2 skrll __BITS(5,4), /* k */ 242 1.11.2.2 skrll 0, /* m */ 243 1.11.2.2 skrll __BITS(17,16), /* p */ 244 1.11.2.2 skrll __BIT(31), /* enable */ 245 1.11.2.2 skrll SUNXI_CCU_NKMP_DIVIDE_BY_TWO), 246 1.11.2.2 skrll 247 1.11.2.2 skrll SUNXI_CCU_NKMP_TABLE(H3_CLK_PLL_AUDIO_BASE, "pll_audio", "hosc", 248 1.11.2.2 skrll PLL_AUDIO_CTRL_REG, /* reg */ 249 1.11.2.2 skrll __BITS(14,8), /* n */ 250 1.11.2.2 skrll 0, /* k */ 251 1.11.2.2 skrll __BITS(4,0), /* m */ 252 1.11.2.2 skrll __BITS(19,16), /* p */ 253 1.11.2.2 skrll __BIT(31), /* enable */ 254 1.11.2.2 skrll __BIT(28), /* lock */ 255 1.11.2.2 skrll sun8i_h3_ac_dig_table, /* table */ 256 1.11.2.2 skrll 0), 257 1.11.2.2 skrll 258 1.11.2.2 skrll SUNXI_CCU_PREDIV(H3_CLK_AHB1, "ahb1", ahb1_parents, 259 1.11.2.2 skrll AHB1_APB1_CFG_REG, /* reg */ 260 1.11.2.2 skrll __BITS(7,6), /* prediv */ 261 1.11.2.2 skrll __BIT(3), /* prediv_sel */ 262 1.11.2.2 skrll __BITS(5,4), /* div */ 263 1.11.2.2 skrll __BITS(13,12), /* sel */ 264 1.11.2.2 skrll SUNXI_CCU_PREDIV_POWER_OF_TWO), 265 1.11.2.2 skrll 266 1.11.2.2 skrll SUNXI_CCU_PREDIV(H3_CLK_AHB2, "ahb2", ahb2_parents, 267 1.11.2.2 skrll AHB2_CFG_REG, /* reg */ 268 1.11.2.2 skrll 0, /* prediv */ 269 1.11.2.2 skrll __BIT(1), /* prediv_sel */ 270 1.11.2.2 skrll 0, /* div */ 271 1.11.2.2 skrll __BITS(1,0), /* sel */ 272 1.11.2.2 skrll SUNXI_CCU_PREDIV_DIVIDE_BY_TWO), 273 1.11.2.2 skrll 274 1.11.2.2 skrll SUNXI_CCU_DIV(H3_CLK_APB1, "apb1", apb1_parents, 275 1.11.2.2 skrll AHB1_APB1_CFG_REG, /* reg */ 276 1.11.2.2 skrll __BITS(9,8), /* div */ 277 1.11.2.2 skrll 0, /* sel */ 278 1.11.2.2 skrll SUNXI_CCU_DIV_POWER_OF_TWO|SUNXI_CCU_DIV_ZERO_IS_ONE), 279 1.11.2.2 skrll 280 1.11.2.2 skrll SUNXI_CCU_NM(H3_CLK_APB2, "apb2", apb2_parents, 281 1.11.2.2 skrll APB2_CFG_REG, /* reg */ 282 1.11.2.2 skrll __BITS(17,16), /* n */ 283 1.11.2.2 skrll __BITS(4,0), /* m */ 284 1.11.2.2 skrll __BITS(25,24), /* sel */ 285 1.11.2.2 skrll 0, /* enable */ 286 1.11.2.2 skrll SUNXI_CCU_NM_POWER_OF_TWO), 287 1.11.2.2 skrll 288 1.11.2.2 skrll SUNXI_CCU_NM(H3_CLK_MMC0, "mmc0", mod_parents, 289 1.11.2.2 skrll SDMMC0_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31), 290 1.11.2.2 skrll SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 291 1.11.2.2 skrll SUNXI_CCU_PHASE(H3_CLK_MMC0_SAMPLE, "mmc0_sample", "mmc0", 292 1.11.2.2 skrll SDMMC0_CLK_REG, __BITS(22,20)), 293 1.11.2.2 skrll SUNXI_CCU_PHASE(H3_CLK_MMC0_OUTPUT, "mmc0_output", "mmc0", 294 1.11.2.2 skrll SDMMC0_CLK_REG, __BITS(10,8)), 295 1.11.2.2 skrll SUNXI_CCU_NM(H3_CLK_MMC1, "mmc1", mod_parents, 296 1.11.2.2 skrll SDMMC1_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31), 297 1.11.2.2 skrll SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 298 1.11.2.2 skrll SUNXI_CCU_PHASE(H3_CLK_MMC1_SAMPLE, "mmc1_sample", "mmc1", 299 1.11.2.2 skrll SDMMC1_CLK_REG, __BITS(22,20)), 300 1.11.2.2 skrll SUNXI_CCU_PHASE(H3_CLK_MMC1_OUTPUT, "mmc1_output", "mmc1", 301 1.11.2.2 skrll SDMMC1_CLK_REG, __BITS(10,8)), 302 1.11.2.2 skrll SUNXI_CCU_NM(H3_CLK_MMC2, "mmc2", mod_parents, 303 1.11.2.2 skrll SDMMC2_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31), 304 1.11.2.2 skrll SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 305 1.11.2.2 skrll SUNXI_CCU_PHASE(H3_CLK_MMC2_SAMPLE, "mmc2_sample", "mmc2", 306 1.11.2.2 skrll SDMMC2_CLK_REG, __BITS(22,20)), 307 1.11.2.2 skrll SUNXI_CCU_PHASE(H3_CLK_MMC2_OUTPUT, "mmc2_output", "mmc2", 308 1.11.2.2 skrll SDMMC2_CLK_REG, __BITS(10,8)), 309 1.11.2.2 skrll 310 1.11.2.2 skrll SUNXI_CCU_GATE(H3_CLK_AC_DIG, "ac_dig", "pll_audio", 311 1.11.2.2 skrll AC_DIG_CLK_REG, 31), 312 1.11.2.2 skrll 313 1.11.2.2 skrll SUNXI_CCU_GATE(H3_CLK_BUS_DMA, "bus-dma", "ahb1", 314 1.11.2.2 skrll BUS_CLK_GATING_REG0, 6), 315 1.11.2.2 skrll SUNXI_CCU_GATE(H3_CLK_BUS_MMC0, "bus-mmc0", "ahb1", 316 1.11.2.2 skrll BUS_CLK_GATING_REG0, 8), 317 1.11.2.2 skrll SUNXI_CCU_GATE(H3_CLK_BUS_MMC1, "bus-mmc1", "ahb1", 318 1.11.2.2 skrll BUS_CLK_GATING_REG0, 9), 319 1.11.2.2 skrll SUNXI_CCU_GATE(H3_CLK_BUS_MMC2, "bus-mmc2", "ahb1", 320 1.11.2.2 skrll BUS_CLK_GATING_REG0, 10), 321 1.11.2.2 skrll SUNXI_CCU_GATE(H3_CLK_BUS_EMAC, "bus-emac", "ahb2", 322 1.11.2.2 skrll BUS_CLK_GATING_REG0, 17), 323 1.11.2.2 skrll SUNXI_CCU_GATE(H3_CLK_BUS_OTG, "bus-otg", "ahb1", 324 1.11.2.2 skrll BUS_CLK_GATING_REG0, 23), 325 1.11.2.2 skrll SUNXI_CCU_GATE(H3_CLK_BUS_EHCI0, "bus-ehci0", "ahb1", 326 1.11.2.2 skrll BUS_CLK_GATING_REG0, 24), 327 1.11.2.2 skrll SUNXI_CCU_GATE(H3_CLK_BUS_EHCI1, "bus-ehci1", "ahb2", 328 1.11.2.2 skrll BUS_CLK_GATING_REG0, 25), 329 1.11.2.2 skrll SUNXI_CCU_GATE(H3_CLK_BUS_EHCI2, "bus-ehci2", "ahb2", 330 1.11.2.2 skrll BUS_CLK_GATING_REG0, 26), 331 1.11.2.2 skrll SUNXI_CCU_GATE(H3_CLK_BUS_EHCI3, "bus-ehci3", "ahb2", 332 1.11.2.2 skrll BUS_CLK_GATING_REG0, 27), 333 1.11.2.2 skrll SUNXI_CCU_GATE(H3_CLK_BUS_OHCI0, "bus-ohci0", "ahb1", 334 1.11.2.2 skrll BUS_CLK_GATING_REG0, 28), 335 1.11.2.2 skrll SUNXI_CCU_GATE(H3_CLK_BUS_OHCI1, "bus-ohci1", "ahb2", 336 1.11.2.2 skrll BUS_CLK_GATING_REG0, 29), 337 1.11.2.2 skrll SUNXI_CCU_GATE(H3_CLK_BUS_OHCI2, "bus-ohci2", "ahb2", 338 1.11.2.2 skrll BUS_CLK_GATING_REG0, 30), 339 1.11.2.2 skrll SUNXI_CCU_GATE(H3_CLK_BUS_OHCI3, "bus-ohci3", "ahb2", 340 1.11.2.2 skrll BUS_CLK_GATING_REG0, 31), 341 1.11.2.2 skrll 342 1.11.2.2 skrll SUNXI_CCU_GATE(H3_CLK_BUS_CODEC, "bus-codec", "apb1", 343 1.11.2.2 skrll BUS_CLK_GATING_REG2, 0), 344 1.11.2.2 skrll SUNXI_CCU_GATE(H3_CLK_BUS_PIO, "bus-pio", "apb1", 345 1.11.2.2 skrll BUS_CLK_GATING_REG2, 5), 346 1.11.2.2 skrll 347 1.11.2.2 skrll SUNXI_CCU_GATE(H3_CLK_BUS_I2C0, "bus-i2c0", "apb2", 348 1.11.2.2 skrll BUS_CLK_GATING_REG3, 0), 349 1.11.2.2 skrll SUNXI_CCU_GATE(H3_CLK_BUS_I2C1, "bus-i2c1", "apb2", 350 1.11.2.2 skrll BUS_CLK_GATING_REG3, 1), 351 1.11.2.2 skrll SUNXI_CCU_GATE(H3_CLK_BUS_I2C2, "bus-i2c2", "apb2", 352 1.11.2.2 skrll BUS_CLK_GATING_REG3, 2), 353 1.11.2.2 skrll SUNXI_CCU_GATE(H3_CLK_BUS_UART0, "bus-uart0", "apb2", 354 1.11.2.2 skrll BUS_CLK_GATING_REG3, 16), 355 1.11.2.2 skrll SUNXI_CCU_GATE(H3_CLK_BUS_UART1, "bus-uart1", "apb2", 356 1.11.2.2 skrll BUS_CLK_GATING_REG3, 17), 357 1.11.2.2 skrll SUNXI_CCU_GATE(H3_CLK_BUS_UART2, "bus-uart2", "apb2", 358 1.11.2.2 skrll BUS_CLK_GATING_REG3, 18), 359 1.11.2.2 skrll SUNXI_CCU_GATE(H3_CLK_BUS_UART3, "bus-uart3", "apb2", 360 1.11.2.2 skrll BUS_CLK_GATING_REG3, 19), 361 1.11.2.2 skrll 362 1.11.2.2 skrll SUNXI_CCU_GATE(H3_CLK_USBPHY0, "usb-phy0", "hosc", 363 1.11.2.2 skrll USBPHY_CFG_REG, 8), 364 1.11.2.2 skrll SUNXI_CCU_GATE(H3_CLK_USBPHY1, "usb-phy1", "hosc", 365 1.11.2.2 skrll USBPHY_CFG_REG, 9), 366 1.11.2.2 skrll SUNXI_CCU_GATE(H3_CLK_USBPHY2, "usb-phy2", "hosc", 367 1.11.2.2 skrll USBPHY_CFG_REG, 10), 368 1.11.2.2 skrll SUNXI_CCU_GATE(H3_CLK_USBPHY3, "usb-phy3", "hosc", 369 1.11.2.2 skrll USBPHY_CFG_REG, 11), 370 1.11.2.2 skrll SUNXI_CCU_GATE(H3_CLK_USBOHCI0, "usb-ohci0", "hosc", 371 1.11.2.2 skrll USBPHY_CFG_REG, 16), 372 1.11.2.2 skrll SUNXI_CCU_GATE(H3_CLK_USBOHCI1, "usb-ohci1", "hosc", 373 1.11.2.2 skrll USBPHY_CFG_REG, 17), 374 1.11.2.2 skrll SUNXI_CCU_GATE(H3_CLK_USBOHCI2, "usb-ohci2", "hosc", 375 1.11.2.2 skrll USBPHY_CFG_REG, 18), 376 1.11.2.2 skrll SUNXI_CCU_GATE(H3_CLK_USBOHCI3, "usb-ohci3", "hosc", 377 1.11.2.2 skrll USBPHY_CFG_REG, 19), 378 1.11.2.2 skrll }; 379 1.11.2.2 skrll 380 1.11.2.2 skrll static void 381 1.11.2.2 skrll sun8i_h3_ccu_init(struct sunxi_ccu_softc *sc) 382 1.11.2.2 skrll { 383 1.11.2.2 skrll uint32_t val; 384 1.11.2.2 skrll 385 1.11.2.2 skrll /* Set AHB2 source to PLL_PERIPH/2 */ 386 1.11.2.2 skrll val = CCU_READ(sc, AHB2_CFG_REG); 387 1.11.2.2 skrll val &= ~AHB2_CLK_CFG; 388 1.11.2.2 skrll val |= __SHIFTIN(AHB2_CLK_CFG_PLL_PERIPH0_2, AHB2_CLK_CFG); 389 1.11.2.2 skrll CCU_WRITE(sc, AHB2_CFG_REG, val); 390 1.11.2.2 skrll } 391 1.11.2.2 skrll 392 1.11.2.2 skrll static int 393 1.11.2.2 skrll sun8i_h3_ccu_match(device_t parent, cfdata_t cf, void *aux) 394 1.11.2.2 skrll { 395 1.11.2.2 skrll struct fdt_attach_args * const faa = aux; 396 1.11.2.2 skrll 397 1.11.2.2 skrll return of_match_compatible(faa->faa_phandle, compatible); 398 1.11.2.2 skrll } 399 1.11.2.2 skrll 400 1.11.2.2 skrll static void 401 1.11.2.2 skrll sun8i_h3_ccu_attach(device_t parent, device_t self, void *aux) 402 1.11.2.2 skrll { 403 1.11.2.2 skrll struct sunxi_ccu_softc * const sc = device_private(self); 404 1.11.2.2 skrll struct fdt_attach_args * const faa = aux; 405 1.11.2.2 skrll 406 1.11.2.2 skrll sc->sc_dev = self; 407 1.11.2.2 skrll sc->sc_phandle = faa->faa_phandle; 408 1.11.2.2 skrll sc->sc_bst = faa->faa_bst; 409 1.11.2.2 skrll 410 1.11.2.2 skrll sc->sc_resets = sun8i_h3_ccu_resets; 411 1.11.2.2 skrll sc->sc_nresets = __arraycount(sun8i_h3_ccu_resets); 412 1.11.2.2 skrll 413 1.11.2.2 skrll sc->sc_clks = sun8i_h3_ccu_clks; 414 1.11.2.2 skrll sc->sc_nclks = __arraycount(sun8i_h3_ccu_clks); 415 1.11.2.2 skrll 416 1.11.2.2 skrll if (sunxi_ccu_attach(sc) != 0) 417 1.11.2.2 skrll return; 418 1.11.2.2 skrll 419 1.11.2.2 skrll aprint_naive("\n"); 420 1.11.2.2 skrll aprint_normal(": H3 CCU\n"); 421 1.11.2.2 skrll 422 1.11.2.2 skrll sun8i_h3_ccu_init(sc); 423 1.11.2.2 skrll 424 1.11.2.2 skrll sunxi_ccu_print(sc); 425 1.11.2.2 skrll } 426
Indexes created Thu Oct 23 22:10:10 GMT 2025