sun8i_h3_ccu.c revision 1.10
1 /* $NetBSD: sun8i_h3_ccu.c,v 1.10 2017/08/06 17:14:37 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * Copyright (c) 2017 Emmanuel Vadot <manu (at) freebsd.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 32 __KERNEL_RCSID(1, "$NetBSD: sun8i_h3_ccu.c,v 1.10 2017/08/06 17:14:37 jmcneill Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/systm.h> 38 39 #include <dev/fdt/fdtvar.h> 40 41 #include <arm/sunxi/sunxi_ccu.h> 42 #include <arm/sunxi/sun8i_h3_ccu.h> 43 44 #define PLL_AUDIO_CTRL_REG 0x008 45 #define PLL_PERIPH0_CTRL_REG 0x028 46 #define AHB1_APB1_CFG_REG 0x054 47 #define APB2_CFG_REG 0x058 48 #define AHB2_CFG_REG 0x05c 49 #define AHB2_CLK_CFG __BITS(1,0) 50 #define AHB2_CLK_CFG_PLL_PERIPH0_2 1 51 #define BUS_CLK_GATING_REG0 0x060 52 #define BUS_CLK_GATING_REG2 0x068 53 #define BUS_CLK_GATING_REG3 0x06c 54 #define SDMMC0_CLK_REG 0x088 55 #define SDMMC1_CLK_REG 0x08c 56 #define SDMMC2_CLK_REG 0x090 57 #define USBPHY_CFG_REG 0x0cc 58 #define MBUS_RST_REG 0x0fc 59 #define AC_DIG_CLK_REG 0x140 60 #define BUS_SOFT_RST_REG0 0x2c0 61 #define BUS_SOFT_RST_REG1 0x2c4 62 #define BUS_SOFT_RST_REG2 0x2c8 63 #define BUS_SOFT_RST_REG3 0x2d0 64 #define BUS_SOFT_RST_REG4 0x2d8 65 66 static int sun8i_h3_ccu_match(device_t, cfdata_t, void *); 67 static void sun8i_h3_ccu_attach(device_t, device_t, void *); 68 69 static const char * const compatible[] = { 70 "allwinner,sun8i-h3-ccu", 71 NULL 72 }; 73 74 CFATTACH_DECL_NEW(sunxi_h3_ccu, sizeof(struct sunxi_ccu_softc), 75 sun8i_h3_ccu_match, sun8i_h3_ccu_attach, NULL, NULL); 76 77 static struct sunxi_ccu_reset sun8i_h3_ccu_resets[] = { 78 SUNXI_CCU_RESET(H3_RST_USB_PHY0, USBPHY_CFG_REG, 0), 79 SUNXI_CCU_RESET(H3_RST_USB_PHY1, USBPHY_CFG_REG, 1), 80 SUNXI_CCU_RESET(H3_RST_USB_PHY2, USBPHY_CFG_REG, 2), 81 SUNXI_CCU_RESET(H3_RST_USB_PHY3, USBPHY_CFG_REG, 3), 82 83 SUNXI_CCU_RESET(H3_RST_MBUS, MBUS_RST_REG, 31), 84 85 SUNXI_CCU_RESET(H3_RST_BUS_CE, BUS_SOFT_RST_REG0, 5), 86 SUNXI_CCU_RESET(H3_RST_BUS_DMA, BUS_SOFT_RST_REG0, 6), 87 SUNXI_CCU_RESET(H3_RST_BUS_MMC0, BUS_SOFT_RST_REG0, 8), 88 SUNXI_CCU_RESET(H3_RST_BUS_MMC1, BUS_SOFT_RST_REG0, 9), 89 SUNXI_CCU_RESET(H3_RST_BUS_MMC2, BUS_SOFT_RST_REG0, 10), 90 SUNXI_CCU_RESET(H3_RST_BUS_NAND, BUS_SOFT_RST_REG0, 13), 91 SUNXI_CCU_RESET(H3_RST_BUS_DRAM, BUS_SOFT_RST_REG0, 14), 92 SUNXI_CCU_RESET(H3_RST_BUS_EMAC, BUS_SOFT_RST_REG0, 17), 93 SUNXI_CCU_RESET(H3_RST_BUS_TS, BUS_SOFT_RST_REG0, 18), 94 SUNXI_CCU_RESET(H3_RST_BUS_HSTIMER, BUS_SOFT_RST_REG0, 19), 95 SUNXI_CCU_RESET(H3_RST_BUS_SPI0, BUS_SOFT_RST_REG0, 20), 96 SUNXI_CCU_RESET(H3_RST_BUS_SPI1, BUS_SOFT_RST_REG0, 21), 97 SUNXI_CCU_RESET(H3_RST_BUS_OTG, BUS_SOFT_RST_REG0, 23), 98 SUNXI_CCU_RESET(H3_RST_BUS_EHCI0, BUS_SOFT_RST_REG0, 24), 99 SUNXI_CCU_RESET(H3_RST_BUS_EHCI1, BUS_SOFT_RST_REG0, 25), 100 SUNXI_CCU_RESET(H3_RST_BUS_EHCI2, BUS_SOFT_RST_REG0, 26), 101 SUNXI_CCU_RESET(H3_RST_BUS_EHCI3, BUS_SOFT_RST_REG0, 27), 102 SUNXI_CCU_RESET(H3_RST_BUS_OHCI0, BUS_SOFT_RST_REG0, 28), 103 SUNXI_CCU_RESET(H3_RST_BUS_OHCI1, BUS_SOFT_RST_REG0, 29), 104 SUNXI_CCU_RESET(H3_RST_BUS_OHCI2, BUS_SOFT_RST_REG0, 30), 105 SUNXI_CCU_RESET(H3_RST_BUS_OHCI3, BUS_SOFT_RST_REG0, 31), 106 107 SUNXI_CCU_RESET(H3_RST_BUS_VE, BUS_SOFT_RST_REG1, 0), 108 SUNXI_CCU_RESET(H3_RST_BUS_TCON0, BUS_SOFT_RST_REG1, 3), 109 SUNXI_CCU_RESET(H3_RST_BUS_TCON1, BUS_SOFT_RST_REG1, 4), 110 SUNXI_CCU_RESET(H3_RST_BUS_DEINTERLACE, BUS_SOFT_RST_REG1, 5), 111 SUNXI_CCU_RESET(H3_RST_BUS_CSI, BUS_SOFT_RST_REG1, 8), 112 SUNXI_CCU_RESET(H3_RST_BUS_TVE, BUS_SOFT_RST_REG1, 9), 113 SUNXI_CCU_RESET(H3_RST_BUS_HDMI0, BUS_SOFT_RST_REG1, 10), 114 SUNXI_CCU_RESET(H3_RST_BUS_HDMI1, BUS_SOFT_RST_REG1, 11), 115 SUNXI_CCU_RESET(H3_RST_BUS_DE, BUS_SOFT_RST_REG1, 12), 116 SUNXI_CCU_RESET(H3_RST_BUS_GPU, BUS_SOFT_RST_REG1, 20), 117 SUNXI_CCU_RESET(H3_RST_BUS_MSGBOX, BUS_SOFT_RST_REG1, 21), 118 SUNXI_CCU_RESET(H3_RST_BUS_SPINLOCK, BUS_SOFT_RST_REG1, 22), 119 SUNXI_CCU_RESET(H3_RST_BUS_DBG, BUS_SOFT_RST_REG1, 31), 120 121 SUNXI_CCU_RESET(H3_RST_BUS_EPHY, BUS_SOFT_RST_REG2, 2), 122 123 SUNXI_CCU_RESET(H3_RST_BUS_CODEC, BUS_SOFT_RST_REG3, 0), 124 SUNXI_CCU_RESET(H3_RST_BUS_SPDIF, BUS_SOFT_RST_REG3, 1), 125 SUNXI_CCU_RESET(H3_RST_BUS_THS, BUS_SOFT_RST_REG3, 8), 126 SUNXI_CCU_RESET(H3_RST_BUS_I2S0, BUS_SOFT_RST_REG3, 12), 127 SUNXI_CCU_RESET(H3_RST_BUS_I2S1, BUS_SOFT_RST_REG3, 13), 128 SUNXI_CCU_RESET(H3_RST_BUS_I2S2, BUS_SOFT_RST_REG3, 14), 129 130 SUNXI_CCU_RESET(H3_RST_BUS_I2C0, BUS_SOFT_RST_REG4, 0), 131 SUNXI_CCU_RESET(H3_RST_BUS_I2C1, BUS_SOFT_RST_REG4, 1), 132 SUNXI_CCU_RESET(H3_RST_BUS_I2C2, BUS_SOFT_RST_REG4, 2), 133 SUNXI_CCU_RESET(H3_RST_BUS_UART0, BUS_SOFT_RST_REG4, 16), 134 SUNXI_CCU_RESET(H3_RST_BUS_UART1, BUS_SOFT_RST_REG4, 17), 135 SUNXI_CCU_RESET(H3_RST_BUS_UART2, BUS_SOFT_RST_REG4, 18), 136 SUNXI_CCU_RESET(H3_RST_BUS_UART3, BUS_SOFT_RST_REG4, 19), 137 SUNXI_CCU_RESET(H3_RST_BUS_SCR, BUS_SOFT_RST_REG4, 20), 138 }; 139 140 static const char *ahb1_parents[] = { "losc", "hosc", "axi", "pll_periph0" }; 141 static const char *ahb2_parents[] = { "ahb1", "pll_periph0" }; 142 static const char *apb1_parents[] = { "ahb1" }; 143 static const char *apb2_parents[] = { "losc", "hosc", "pll_periph0" }; 144 static const char *mod_parents[] = { "hosc", "pll_periph0", "pll_periph1" }; 145 146 static const struct sunxi_ccu_nkmp_tbl sunx8_h3_ac_dig_table[] = { 147 { 24576000, 13, 0, 0, 13 }, 148 { 0 } 149 }; 150 151 static struct sunxi_ccu_clk sun8i_h3_ccu_clks[] = { 152 SUNXI_CCU_NKMP(H3_CLK_PLL_PERIPH0, "pll_periph0", "hosc", 153 PLL_PERIPH0_CTRL_REG, /* reg */ 154 __BITS(12,8), /* n */ 155 __BITS(5,4), /* k */ 156 0, /* m */ 157 __BITS(17,16), /* p */ 158 __BIT(31), /* enable */ 159 SUNXI_CCU_NKMP_DIVIDE_BY_TWO), 160 161 SUNXI_CCU_NKMP_TABLE(H3_CLK_PLL_AUDIO_BASE, "pll_audio", "hosc", 162 PLL_AUDIO_CTRL_REG, /* reg */ 163 __BITS(14,8), /* n */ 164 0, /* k */ 165 __BITS(4,0), /* m */ 166 __BITS(19,16), /* p */ 167 __BIT(31), /* enable */ 168 __BIT(28), /* lock */ 169 sunx8_h3_ac_dig_table, /* table */ 170 0), 171 172 SUNXI_CCU_PREDIV(H3_CLK_AHB1, "ahb1", ahb1_parents, 173 AHB1_APB1_CFG_REG, /* reg */ 174 __BITS(7,6), /* prediv */ 175 __BIT(3), /* prediv_sel */ 176 __BITS(5,4), /* div */ 177 __BITS(13,12), /* sel */ 178 SUNXI_CCU_PREDIV_POWER_OF_TWO), 179 180 SUNXI_CCU_PREDIV(H3_CLK_AHB2, "ahb2", ahb2_parents, 181 AHB2_CFG_REG, /* reg */ 182 0, /* prediv */ 183 __BIT(1), /* prediv_sel */ 184 0, /* div */ 185 __BITS(1,0), /* sel */ 186 SUNXI_CCU_PREDIV_DIVIDE_BY_TWO), 187 188 SUNXI_CCU_DIV(H3_CLK_APB1, "apb1", apb1_parents, 189 AHB1_APB1_CFG_REG, /* reg */ 190 __BITS(9,8), /* div */ 191 0, /* sel */ 192 SUNXI_CCU_DIV_POWER_OF_TWO|SUNXI_CCU_DIV_ZERO_IS_ONE), 193 194 SUNXI_CCU_NM(H3_CLK_APB2, "apb2", apb2_parents, 195 APB2_CFG_REG, /* reg */ 196 __BITS(17,16), /* n */ 197 __BITS(4,0), /* m */ 198 __BITS(25,24), /* sel */ 199 0, /* enable */ 200 SUNXI_CCU_NM_POWER_OF_TWO), 201 202 SUNXI_CCU_NM(H3_CLK_MMC0, "mmc0", mod_parents, 203 SDMMC0_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31), 204 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 205 SUNXI_CCU_PHASE(H3_CLK_MMC0_SAMPLE, "mmc0_sample", "mmc0", 206 SDMMC0_CLK_REG, __BITS(22,20)), 207 SUNXI_CCU_PHASE(H3_CLK_MMC0_OUTPUT, "mmc0_output", "mmc0", 208 SDMMC0_CLK_REG, __BITS(10,8)), 209 SUNXI_CCU_NM(H3_CLK_MMC1, "mmc1", mod_parents, 210 SDMMC1_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31), 211 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 212 SUNXI_CCU_PHASE(H3_CLK_MMC1_SAMPLE, "mmc1_sample", "mmc1", 213 SDMMC1_CLK_REG, __BITS(22,20)), 214 SUNXI_CCU_PHASE(H3_CLK_MMC1_OUTPUT, "mmc1_output", "mmc1", 215 SDMMC1_CLK_REG, __BITS(10,8)), 216 SUNXI_CCU_NM(H3_CLK_MMC2, "mmc2", mod_parents, 217 SDMMC2_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31), 218 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 219 SUNXI_CCU_PHASE(H3_CLK_MMC2_SAMPLE, "mmc2_sample", "mmc2", 220 SDMMC2_CLK_REG, __BITS(22,20)), 221 SUNXI_CCU_PHASE(H3_CLK_MMC2_OUTPUT, "mmc2_output", "mmc2", 222 SDMMC2_CLK_REG, __BITS(10,8)), 223 224 SUNXI_CCU_GATE(H3_CLK_AC_DIG, "ac_dig", "pll_audio", 225 AC_DIG_CLK_REG, 31), 226 227 SUNXI_CCU_GATE(H3_CLK_BUS_DMA, "bus-dma", "ahb1", 228 BUS_CLK_GATING_REG0, 6), 229 SUNXI_CCU_GATE(H3_CLK_BUS_MMC0, "bus-mmc0", "ahb1", 230 BUS_CLK_GATING_REG0, 8), 231 SUNXI_CCU_GATE(H3_CLK_BUS_MMC1, "bus-mmc1", "ahb1", 232 BUS_CLK_GATING_REG0, 9), 233 SUNXI_CCU_GATE(H3_CLK_BUS_MMC2, "bus-mmc2", "ahb1", 234 BUS_CLK_GATING_REG0, 10), 235 SUNXI_CCU_GATE(H3_CLK_BUS_EMAC, "bus-emac", "ahb2", 236 BUS_CLK_GATING_REG0, 17), 237 SUNXI_CCU_GATE(H3_CLK_BUS_OTG, "bus-otg", "ahb1", 238 BUS_CLK_GATING_REG0, 23), 239 SUNXI_CCU_GATE(H3_CLK_BUS_EHCI0, "bus-ehci0", "ahb1", 240 BUS_CLK_GATING_REG0, 24), 241 SUNXI_CCU_GATE(H3_CLK_BUS_EHCI1, "bus-ehci1", "ahb2", 242 BUS_CLK_GATING_REG0, 25), 243 SUNXI_CCU_GATE(H3_CLK_BUS_EHCI2, "bus-ehci2", "ahb2", 244 BUS_CLK_GATING_REG0, 26), 245 SUNXI_CCU_GATE(H3_CLK_BUS_EHCI3, "bus-ehci3", "ahb2", 246 BUS_CLK_GATING_REG0, 27), 247 SUNXI_CCU_GATE(H3_CLK_BUS_OHCI0, "bus-ohci0", "ahb1", 248 BUS_CLK_GATING_REG0, 28), 249 SUNXI_CCU_GATE(H3_CLK_BUS_OHCI1, "bus-ohci1", "ahb2", 250 BUS_CLK_GATING_REG0, 29), 251 SUNXI_CCU_GATE(H3_CLK_BUS_OHCI2, "bus-ohci2", "ahb2", 252 BUS_CLK_GATING_REG0, 30), 253 SUNXI_CCU_GATE(H3_CLK_BUS_OHCI3, "bus-ohci3", "ahb2", 254 BUS_CLK_GATING_REG0, 31), 255 256 SUNXI_CCU_GATE(H3_CLK_BUS_CODEC, "bus-codec", "apb1", 257 BUS_CLK_GATING_REG2, 0), 258 SUNXI_CCU_GATE(H3_CLK_BUS_PIO, "bus-pio", "apb1", 259 BUS_CLK_GATING_REG2, 5), 260 261 SUNXI_CCU_GATE(H3_CLK_BUS_I2C0, "bus-i2c0", "apb2", 262 BUS_CLK_GATING_REG3, 0), 263 SUNXI_CCU_GATE(H3_CLK_BUS_I2C1, "bus-i2c1", "apb2", 264 BUS_CLK_GATING_REG3, 1), 265 SUNXI_CCU_GATE(H3_CLK_BUS_I2C2, "bus-i2c2", "apb2", 266 BUS_CLK_GATING_REG3, 2), 267 SUNXI_CCU_GATE(H3_CLK_BUS_UART0, "bus-uart0", "apb2", 268 BUS_CLK_GATING_REG3, 16), 269 SUNXI_CCU_GATE(H3_CLK_BUS_UART1, "bus-uart1", "apb2", 270 BUS_CLK_GATING_REG3, 17), 271 SUNXI_CCU_GATE(H3_CLK_BUS_UART2, "bus-uart2", "apb2", 272 BUS_CLK_GATING_REG3, 18), 273 SUNXI_CCU_GATE(H3_CLK_BUS_UART3, "bus-uart3", "apb2", 274 BUS_CLK_GATING_REG3, 19), 275 276 SUNXI_CCU_GATE(H3_CLK_USBPHY0, "usb-phy0", "hosc", 277 USBPHY_CFG_REG, 8), 278 SUNXI_CCU_GATE(H3_CLK_USBPHY1, "usb-phy1", "hosc", 279 USBPHY_CFG_REG, 9), 280 SUNXI_CCU_GATE(H3_CLK_USBPHY2, "usb-phy2", "hosc", 281 USBPHY_CFG_REG, 10), 282 SUNXI_CCU_GATE(H3_CLK_USBPHY3, "usb-phy3", "hosc", 283 USBPHY_CFG_REG, 11), 284 SUNXI_CCU_GATE(H3_CLK_USBOHCI0, "usb-ohci0", "hosc", 285 USBPHY_CFG_REG, 16), 286 SUNXI_CCU_GATE(H3_CLK_USBOHCI1, "usb-ohci1", "hosc", 287 USBPHY_CFG_REG, 17), 288 SUNXI_CCU_GATE(H3_CLK_USBOHCI2, "usb-ohci2", "hosc", 289 USBPHY_CFG_REG, 18), 290 SUNXI_CCU_GATE(H3_CLK_USBOHCI3, "usb-ohci3", "hosc", 291 USBPHY_CFG_REG, 19), 292 }; 293 294 static void 295 sun8i_h3_ccu_init(struct sunxi_ccu_softc *sc) 296 { 297 uint32_t val; 298 299 /* Set AHB2 source to PLL_PERIPH/2 */ 300 val = CCU_READ(sc, AHB2_CFG_REG); 301 val &= ~AHB2_CLK_CFG; 302 val |= __SHIFTIN(AHB2_CLK_CFG_PLL_PERIPH0_2, AHB2_CLK_CFG); 303 CCU_WRITE(sc, AHB2_CFG_REG, val); 304 } 305 306 static int 307 sun8i_h3_ccu_match(device_t parent, cfdata_t cf, void *aux) 308 { 309 struct fdt_attach_args * const faa = aux; 310 311 return of_match_compatible(faa->faa_phandle, compatible); 312 } 313 314 static void 315 sun8i_h3_ccu_attach(device_t parent, device_t self, void *aux) 316 { 317 struct sunxi_ccu_softc * const sc = device_private(self); 318 struct fdt_attach_args * const faa = aux; 319 320 sc->sc_dev = self; 321 sc->sc_phandle = faa->faa_phandle; 322 sc->sc_bst = faa->faa_bst; 323 324 sc->sc_resets = sun8i_h3_ccu_resets; 325 sc->sc_nresets = __arraycount(sun8i_h3_ccu_resets); 326 327 sc->sc_clks = sun8i_h3_ccu_clks; 328 sc->sc_nclks = __arraycount(sun8i_h3_ccu_clks); 329 330 if (sunxi_ccu_attach(sc) != 0) 331 return; 332 333 aprint_naive("\n"); 334 aprint_normal(": H3 CCU\n"); 335 336 sun8i_h3_ccu_init(sc); 337 338 sunxi_ccu_print(sc); 339 } 340
Indexes created Thu Oct 02 10:09:58 GMT 2025