sun8i_h3_ccu.c revision 1.12
1 /* $NetBSD: sun8i_h3_ccu.c,v 1.12 2017/09/16 21:47:02 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * Copyright (c) 2017 Emmanuel Vadot <manu (at) freebsd.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 32 __KERNEL_RCSID(1, "$NetBSD: sun8i_h3_ccu.c,v 1.12 2017/09/16 21:47:02 jmcneill Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/systm.h> 38 39 #include <dev/fdt/fdtvar.h> 40 41 #include <arm/sunxi/sunxi_ccu.h> 42 #include <arm/sunxi/sun8i_h3_ccu.h> 43 44 #define PLL_CPUX_CTRL_REG 0x000 45 #define PLL_AUDIO_CTRL_REG 0x008 46 #define PLL_PERIPH0_CTRL_REG 0x028 47 #define AHB1_APB1_CFG_REG 0x054 48 #define APB2_CFG_REG 0x058 49 #define AHB2_CFG_REG 0x05c 50 #define AHB2_CLK_CFG __BITS(1,0) 51 #define AHB2_CLK_CFG_PLL_PERIPH0_2 1 52 #define BUS_CLK_GATING_REG0 0x060 53 #define BUS_CLK_GATING_REG2 0x068 54 #define BUS_CLK_GATING_REG3 0x06c 55 #define BUS_CLK_GATING_REG4 0x070 56 #define SDMMC0_CLK_REG 0x088 57 #define SDMMC1_CLK_REG 0x08c 58 #define SDMMC2_CLK_REG 0x090 59 #define USBPHY_CFG_REG 0x0cc 60 #define MBUS_RST_REG 0x0fc 61 #define AC_DIG_CLK_REG 0x140 62 #define BUS_SOFT_RST_REG0 0x2c0 63 #define BUS_SOFT_RST_REG1 0x2c4 64 #define BUS_SOFT_RST_REG2 0x2c8 65 #define BUS_SOFT_RST_REG3 0x2d0 66 #define BUS_SOFT_RST_REG4 0x2d8 67 68 static int sun8i_h3_ccu_match(device_t, cfdata_t, void *); 69 static void sun8i_h3_ccu_attach(device_t, device_t, void *); 70 71 static const char * const compatible[] = { 72 "allwinner,sun8i-h3-ccu", 73 NULL 74 }; 75 76 CFATTACH_DECL_NEW(sunxi_h3_ccu, sizeof(struct sunxi_ccu_softc), 77 sun8i_h3_ccu_match, sun8i_h3_ccu_attach, NULL, NULL); 78 79 static struct sunxi_ccu_reset sun8i_h3_ccu_resets[] = { 80 SUNXI_CCU_RESET(H3_RST_USB_PHY0, USBPHY_CFG_REG, 0), 81 SUNXI_CCU_RESET(H3_RST_USB_PHY1, USBPHY_CFG_REG, 1), 82 SUNXI_CCU_RESET(H3_RST_USB_PHY2, USBPHY_CFG_REG, 2), 83 SUNXI_CCU_RESET(H3_RST_USB_PHY3, USBPHY_CFG_REG, 3), 84 85 SUNXI_CCU_RESET(H3_RST_MBUS, MBUS_RST_REG, 31), 86 87 SUNXI_CCU_RESET(H3_RST_BUS_CE, BUS_SOFT_RST_REG0, 5), 88 SUNXI_CCU_RESET(H3_RST_BUS_DMA, BUS_SOFT_RST_REG0, 6), 89 SUNXI_CCU_RESET(H3_RST_BUS_MMC0, BUS_SOFT_RST_REG0, 8), 90 SUNXI_CCU_RESET(H3_RST_BUS_MMC1, BUS_SOFT_RST_REG0, 9), 91 SUNXI_CCU_RESET(H3_RST_BUS_MMC2, BUS_SOFT_RST_REG0, 10), 92 SUNXI_CCU_RESET(H3_RST_BUS_NAND, BUS_SOFT_RST_REG0, 13), 93 SUNXI_CCU_RESET(H3_RST_BUS_DRAM, BUS_SOFT_RST_REG0, 14), 94 SUNXI_CCU_RESET(H3_RST_BUS_EMAC, BUS_SOFT_RST_REG0, 17), 95 SUNXI_CCU_RESET(H3_RST_BUS_TS, BUS_SOFT_RST_REG0, 18), 96 SUNXI_CCU_RESET(H3_RST_BUS_HSTIMER, BUS_SOFT_RST_REG0, 19), 97 SUNXI_CCU_RESET(H3_RST_BUS_SPI0, BUS_SOFT_RST_REG0, 20), 98 SUNXI_CCU_RESET(H3_RST_BUS_SPI1, BUS_SOFT_RST_REG0, 21), 99 SUNXI_CCU_RESET(H3_RST_BUS_OTG, BUS_SOFT_RST_REG0, 23), 100 SUNXI_CCU_RESET(H3_RST_BUS_EHCI0, BUS_SOFT_RST_REG0, 24), 101 SUNXI_CCU_RESET(H3_RST_BUS_EHCI1, BUS_SOFT_RST_REG0, 25), 102 SUNXI_CCU_RESET(H3_RST_BUS_EHCI2, BUS_SOFT_RST_REG0, 26), 103 SUNXI_CCU_RESET(H3_RST_BUS_EHCI3, BUS_SOFT_RST_REG0, 27), 104 SUNXI_CCU_RESET(H3_RST_BUS_OHCI0, BUS_SOFT_RST_REG0, 28), 105 SUNXI_CCU_RESET(H3_RST_BUS_OHCI1, BUS_SOFT_RST_REG0, 29), 106 SUNXI_CCU_RESET(H3_RST_BUS_OHCI2, BUS_SOFT_RST_REG0, 30), 107 SUNXI_CCU_RESET(H3_RST_BUS_OHCI3, BUS_SOFT_RST_REG0, 31), 108 109 SUNXI_CCU_RESET(H3_RST_BUS_VE, BUS_SOFT_RST_REG1, 0), 110 SUNXI_CCU_RESET(H3_RST_BUS_TCON0, BUS_SOFT_RST_REG1, 3), 111 SUNXI_CCU_RESET(H3_RST_BUS_TCON1, BUS_SOFT_RST_REG1, 4), 112 SUNXI_CCU_RESET(H3_RST_BUS_DEINTERLACE, BUS_SOFT_RST_REG1, 5), 113 SUNXI_CCU_RESET(H3_RST_BUS_CSI, BUS_SOFT_RST_REG1, 8), 114 SUNXI_CCU_RESET(H3_RST_BUS_TVE, BUS_SOFT_RST_REG1, 9), 115 SUNXI_CCU_RESET(H3_RST_BUS_HDMI0, BUS_SOFT_RST_REG1, 10), 116 SUNXI_CCU_RESET(H3_RST_BUS_HDMI1, BUS_SOFT_RST_REG1, 11), 117 SUNXI_CCU_RESET(H3_RST_BUS_DE, BUS_SOFT_RST_REG1, 12), 118 SUNXI_CCU_RESET(H3_RST_BUS_GPU, BUS_SOFT_RST_REG1, 20), 119 SUNXI_CCU_RESET(H3_RST_BUS_MSGBOX, BUS_SOFT_RST_REG1, 21), 120 SUNXI_CCU_RESET(H3_RST_BUS_SPINLOCK, BUS_SOFT_RST_REG1, 22), 121 SUNXI_CCU_RESET(H3_RST_BUS_DBG, BUS_SOFT_RST_REG1, 31), 122 123 SUNXI_CCU_RESET(H3_RST_BUS_EPHY, BUS_SOFT_RST_REG2, 2), 124 125 SUNXI_CCU_RESET(H3_RST_BUS_CODEC, BUS_SOFT_RST_REG3, 0), 126 SUNXI_CCU_RESET(H3_RST_BUS_SPDIF, BUS_SOFT_RST_REG3, 1), 127 SUNXI_CCU_RESET(H3_RST_BUS_THS, BUS_SOFT_RST_REG3, 8), 128 SUNXI_CCU_RESET(H3_RST_BUS_I2S0, BUS_SOFT_RST_REG3, 12), 129 SUNXI_CCU_RESET(H3_RST_BUS_I2S1, BUS_SOFT_RST_REG3, 13), 130 SUNXI_CCU_RESET(H3_RST_BUS_I2S2, BUS_SOFT_RST_REG3, 14), 131 132 SUNXI_CCU_RESET(H3_RST_BUS_I2C0, BUS_SOFT_RST_REG4, 0), 133 SUNXI_CCU_RESET(H3_RST_BUS_I2C1, BUS_SOFT_RST_REG4, 1), 134 SUNXI_CCU_RESET(H3_RST_BUS_I2C2, BUS_SOFT_RST_REG4, 2), 135 SUNXI_CCU_RESET(H3_RST_BUS_UART0, BUS_SOFT_RST_REG4, 16), 136 SUNXI_CCU_RESET(H3_RST_BUS_UART1, BUS_SOFT_RST_REG4, 17), 137 SUNXI_CCU_RESET(H3_RST_BUS_UART2, BUS_SOFT_RST_REG4, 18), 138 SUNXI_CCU_RESET(H3_RST_BUS_UART3, BUS_SOFT_RST_REG4, 19), 139 SUNXI_CCU_RESET(H3_RST_BUS_SCR, BUS_SOFT_RST_REG4, 20), 140 }; 141 142 static const char *ahb1_parents[] = { "losc", "hosc", "axi", "pll_periph0" }; 143 static const char *ahb2_parents[] = { "ahb1", "pll_periph0" }; 144 static const char *apb1_parents[] = { "ahb1" }; 145 static const char *apb2_parents[] = { "losc", "hosc", "pll_periph0" }; 146 static const char *mod_parents[] = { "hosc", "pll_periph0", "pll_periph1" }; 147 148 static const struct sunxi_ccu_nkmp_tbl sun8i_h3_cpux_table[] = { 149 { 60000000, 9, 0, 0, 2 }, 150 { 66000000, 10, 0, 0, 2 }, 151 { 72000000, 11, 0, 0, 2 }, 152 { 78000000, 12, 0, 0, 2 }, 153 { 84000000, 13, 0, 0, 2 }, 154 { 90000000, 14, 0, 0, 2 }, 155 { 96000000, 15, 0, 0, 2 }, 156 { 102000000, 16, 0, 0, 2 }, 157 { 108000000, 17, 0, 0, 2 }, 158 { 114000000, 18, 0, 0, 2 }, 159 { 120000000, 9, 0, 0, 1 }, 160 { 132000000, 10, 0, 0, 1 }, 161 { 144000000, 11, 0, 0, 1 }, 162 { 156000000, 12, 0, 0, 1 }, 163 { 168000000, 13, 0, 0, 1 }, 164 { 180000000, 14, 0, 0, 1 }, 165 { 192000000, 15, 0, 0, 1 }, 166 { 204000000, 16, 0, 0, 1 }, 167 { 216000000, 17, 0, 0, 1 }, 168 { 228000000, 18, 0, 0, 1 }, 169 { 240000000, 9, 0, 0, 0 }, 170 { 264000000, 10, 0, 0, 0 }, 171 { 288000000, 11, 0, 0, 0 }, 172 { 312000000, 12, 0, 0, 0 }, 173 { 336000000, 13, 0, 0, 0 }, 174 { 360000000, 14, 0, 0, 0 }, 175 { 384000000, 15, 0, 0, 0 }, 176 { 408000000, 16, 0, 0, 0 }, 177 { 432000000, 17, 0, 0, 0 }, 178 { 456000000, 18, 0, 0, 0 }, 179 { 480000000, 19, 0, 0, 0 }, 180 { 504000000, 20, 0, 0, 0 }, 181 { 528000000, 21, 0, 0, 0 }, 182 { 552000000, 22, 0, 0, 0 }, 183 { 576000000, 23, 0, 0, 0 }, 184 { 600000000, 24, 0, 0, 0 }, 185 { 624000000, 25, 0, 0, 0 }, 186 { 648000000, 26, 0, 0, 0 }, 187 { 672000000, 27, 0, 0, 0 }, 188 { 696000000, 28, 0, 0, 0 }, 189 { 720000000, 29, 0, 0, 0 }, 190 { 768000000, 15, 1, 0, 0 }, 191 { 792000000, 10, 2, 0, 0 }, 192 { 816000000, 16, 1, 0, 0 }, 193 { 864000000, 17, 1, 0, 0 }, 194 { 912000000, 18, 1, 0, 0 }, 195 { 936000000, 12, 2, 0, 0 }, 196 { 960000000, 19, 1, 0, 0 }, 197 { 1008000000, 20, 1, 0, 0 }, 198 { 1056000000, 21, 1, 0, 0 }, 199 { 1080000000, 14, 2, 0, 0 }, 200 { 1104000000, 22, 1, 0, 0 }, 201 { 1152000000, 23, 1, 0, 0 }, 202 { 1200000000, 24, 1, 0, 0 }, 203 { 1224000000, 16, 2, 0, 0 }, 204 { 1248000000, 25, 1, 0, 0 }, 205 { 1296000000, 26, 1, 0, 0 }, 206 { 1344000000, 27, 1, 0, 0 }, 207 { 1368000000, 18, 2, 0, 0 }, 208 { 1392000000, 28, 1, 0, 0 }, 209 { 1440000000, 29, 1, 0, 0 }, 210 { 1512000000, 20, 2, 0, 0 }, 211 { 1536000000, 15, 3, 0, 0 }, 212 { 1584000000, 21, 2, 0, 0 }, 213 { 1632000000, 16, 3, 0, 0 }, 214 { 1656000000, 22, 2, 0, 0 }, 215 { 1728000000, 23, 2, 0, 0 }, 216 { 1800000000, 24, 2, 0, 0 }, 217 { 1824000000, 18, 3, 0, 0 }, 218 { 1872000000, 25, 2, 0, 0 }, 219 { 0 } 220 }; 221 222 static const struct sunxi_ccu_nkmp_tbl sun8i_h3_ac_dig_table[] = { 223 { 24576000, 13, 0, 0, 13 }, 224 { 0 } 225 }; 226 227 static struct sunxi_ccu_clk sun8i_h3_ccu_clks[] = { 228 SUNXI_CCU_NKMP_TABLE(H3_CLK_CPUX, "pll_cpux", "hosc", 229 PLL_CPUX_CTRL_REG, /* reg */ 230 __BITS(12,8), /* n */ 231 __BITS(5,4), /* k */ 232 __BITS(1,0), /* m */ 233 __BITS(17,16), /* p */ 234 __BIT(31), /* enable */ 235 __BIT(28), /* lock */ 236 sun8i_h3_cpux_table, /* table */ 237 SUNXI_CCU_NKMP_SCALE_CLOCK | SUNXI_CCU_NKMP_FACTOR_P_POW2), 238 239 SUNXI_CCU_NKMP(H3_CLK_PLL_PERIPH0, "pll_periph0", "hosc", 240 PLL_PERIPH0_CTRL_REG, /* reg */ 241 __BITS(12,8), /* n */ 242 __BITS(5,4), /* k */ 243 0, /* m */ 244 __BITS(17,16), /* p */ 245 __BIT(31), /* enable */ 246 SUNXI_CCU_NKMP_DIVIDE_BY_TWO), 247 248 SUNXI_CCU_NKMP_TABLE(H3_CLK_PLL_AUDIO_BASE, "pll_audio", "hosc", 249 PLL_AUDIO_CTRL_REG, /* reg */ 250 __BITS(14,8), /* n */ 251 0, /* k */ 252 __BITS(4,0), /* m */ 253 __BITS(19,16), /* p */ 254 __BIT(31), /* enable */ 255 __BIT(28), /* lock */ 256 sun8i_h3_ac_dig_table, /* table */ 257 0), 258 259 SUNXI_CCU_PREDIV(H3_CLK_AHB1, "ahb1", ahb1_parents, 260 AHB1_APB1_CFG_REG, /* reg */ 261 __BITS(7,6), /* prediv */ 262 __BIT(3), /* prediv_sel */ 263 __BITS(5,4), /* div */ 264 __BITS(13,12), /* sel */ 265 SUNXI_CCU_PREDIV_POWER_OF_TWO), 266 267 SUNXI_CCU_PREDIV(H3_CLK_AHB2, "ahb2", ahb2_parents, 268 AHB2_CFG_REG, /* reg */ 269 0, /* prediv */ 270 __BIT(1), /* prediv_sel */ 271 0, /* div */ 272 __BITS(1,0), /* sel */ 273 SUNXI_CCU_PREDIV_DIVIDE_BY_TWO), 274 275 SUNXI_CCU_DIV(H3_CLK_APB1, "apb1", apb1_parents, 276 AHB1_APB1_CFG_REG, /* reg */ 277 __BITS(9,8), /* div */ 278 0, /* sel */ 279 SUNXI_CCU_DIV_POWER_OF_TWO|SUNXI_CCU_DIV_ZERO_IS_ONE), 280 281 SUNXI_CCU_NM(H3_CLK_APB2, "apb2", apb2_parents, 282 APB2_CFG_REG, /* reg */ 283 __BITS(17,16), /* n */ 284 __BITS(4,0), /* m */ 285 __BITS(25,24), /* sel */ 286 0, /* enable */ 287 SUNXI_CCU_NM_POWER_OF_TWO), 288 289 SUNXI_CCU_NM(H3_CLK_MMC0, "mmc0", mod_parents, 290 SDMMC0_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31), 291 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 292 SUNXI_CCU_PHASE(H3_CLK_MMC0_SAMPLE, "mmc0_sample", "mmc0", 293 SDMMC0_CLK_REG, __BITS(22,20)), 294 SUNXI_CCU_PHASE(H3_CLK_MMC0_OUTPUT, "mmc0_output", "mmc0", 295 SDMMC0_CLK_REG, __BITS(10,8)), 296 SUNXI_CCU_NM(H3_CLK_MMC1, "mmc1", mod_parents, 297 SDMMC1_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31), 298 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 299 SUNXI_CCU_PHASE(H3_CLK_MMC1_SAMPLE, "mmc1_sample", "mmc1", 300 SDMMC1_CLK_REG, __BITS(22,20)), 301 SUNXI_CCU_PHASE(H3_CLK_MMC1_OUTPUT, "mmc1_output", "mmc1", 302 SDMMC1_CLK_REG, __BITS(10,8)), 303 SUNXI_CCU_NM(H3_CLK_MMC2, "mmc2", mod_parents, 304 SDMMC2_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31), 305 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 306 SUNXI_CCU_PHASE(H3_CLK_MMC2_SAMPLE, "mmc2_sample", "mmc2", 307 SDMMC2_CLK_REG, __BITS(22,20)), 308 SUNXI_CCU_PHASE(H3_CLK_MMC2_OUTPUT, "mmc2_output", "mmc2", 309 SDMMC2_CLK_REG, __BITS(10,8)), 310 311 SUNXI_CCU_GATE(H3_CLK_AC_DIG, "ac_dig", "pll_audio", 312 AC_DIG_CLK_REG, 31), 313 314 SUNXI_CCU_GATE(H3_CLK_BUS_DMA, "bus-dma", "ahb1", 315 BUS_CLK_GATING_REG0, 6), 316 SUNXI_CCU_GATE(H3_CLK_BUS_MMC0, "bus-mmc0", "ahb1", 317 BUS_CLK_GATING_REG0, 8), 318 SUNXI_CCU_GATE(H3_CLK_BUS_MMC1, "bus-mmc1", "ahb1", 319 BUS_CLK_GATING_REG0, 9), 320 SUNXI_CCU_GATE(H3_CLK_BUS_MMC2, "bus-mmc2", "ahb1", 321 BUS_CLK_GATING_REG0, 10), 322 SUNXI_CCU_GATE(H3_CLK_BUS_EMAC, "bus-emac", "ahb2", 323 BUS_CLK_GATING_REG0, 17), 324 SUNXI_CCU_GATE(H3_CLK_BUS_OTG, "bus-otg", "ahb1", 325 BUS_CLK_GATING_REG0, 23), 326 SUNXI_CCU_GATE(H3_CLK_BUS_EHCI0, "bus-ehci0", "ahb1", 327 BUS_CLK_GATING_REG0, 24), 328 SUNXI_CCU_GATE(H3_CLK_BUS_EHCI1, "bus-ehci1", "ahb2", 329 BUS_CLK_GATING_REG0, 25), 330 SUNXI_CCU_GATE(H3_CLK_BUS_EHCI2, "bus-ehci2", "ahb2", 331 BUS_CLK_GATING_REG0, 26), 332 SUNXI_CCU_GATE(H3_CLK_BUS_EHCI3, "bus-ehci3", "ahb2", 333 BUS_CLK_GATING_REG0, 27), 334 SUNXI_CCU_GATE(H3_CLK_BUS_OHCI0, "bus-ohci0", "ahb1", 335 BUS_CLK_GATING_REG0, 28), 336 SUNXI_CCU_GATE(H3_CLK_BUS_OHCI1, "bus-ohci1", "ahb2", 337 BUS_CLK_GATING_REG0, 29), 338 SUNXI_CCU_GATE(H3_CLK_BUS_OHCI2, "bus-ohci2", "ahb2", 339 BUS_CLK_GATING_REG0, 30), 340 SUNXI_CCU_GATE(H3_CLK_BUS_OHCI3, "bus-ohci3", "ahb2", 341 BUS_CLK_GATING_REG0, 31), 342 343 SUNXI_CCU_GATE(H3_CLK_BUS_CODEC, "bus-codec", "apb1", 344 BUS_CLK_GATING_REG2, 0), 345 SUNXI_CCU_GATE(H3_CLK_BUS_PIO, "bus-pio", "apb1", 346 BUS_CLK_GATING_REG2, 5), 347 348 SUNXI_CCU_GATE(H3_CLK_BUS_I2C0, "bus-i2c0", "apb2", 349 BUS_CLK_GATING_REG3, 0), 350 SUNXI_CCU_GATE(H3_CLK_BUS_I2C1, "bus-i2c1", "apb2", 351 BUS_CLK_GATING_REG3, 1), 352 SUNXI_CCU_GATE(H3_CLK_BUS_I2C2, "bus-i2c2", "apb2", 353 BUS_CLK_GATING_REG3, 2), 354 SUNXI_CCU_GATE(H3_CLK_BUS_UART0, "bus-uart0", "apb2", 355 BUS_CLK_GATING_REG3, 16), 356 SUNXI_CCU_GATE(H3_CLK_BUS_UART1, "bus-uart1", "apb2", 357 BUS_CLK_GATING_REG3, 17), 358 SUNXI_CCU_GATE(H3_CLK_BUS_UART2, "bus-uart2", "apb2", 359 BUS_CLK_GATING_REG3, 18), 360 SUNXI_CCU_GATE(H3_CLK_BUS_UART3, "bus-uart3", "apb2", 361 BUS_CLK_GATING_REG3, 19), 362 363 SUNXI_CCU_GATE(H3_CLK_BUS_EPHY, "bus-ephy", "ahb1", 364 BUS_CLK_GATING_REG4, 0), 365 366 SUNXI_CCU_GATE(H3_CLK_USBPHY0, "usb-phy0", "hosc", 367 USBPHY_CFG_REG, 8), 368 SUNXI_CCU_GATE(H3_CLK_USBPHY1, "usb-phy1", "hosc", 369 USBPHY_CFG_REG, 9), 370 SUNXI_CCU_GATE(H3_CLK_USBPHY2, "usb-phy2", "hosc", 371 USBPHY_CFG_REG, 10), 372 SUNXI_CCU_GATE(H3_CLK_USBPHY3, "usb-phy3", "hosc", 373 USBPHY_CFG_REG, 11), 374 SUNXI_CCU_GATE(H3_CLK_USBOHCI0, "usb-ohci0", "hosc", 375 USBPHY_CFG_REG, 16), 376 SUNXI_CCU_GATE(H3_CLK_USBOHCI1, "usb-ohci1", "hosc", 377 USBPHY_CFG_REG, 17), 378 SUNXI_CCU_GATE(H3_CLK_USBOHCI2, "usb-ohci2", "hosc", 379 USBPHY_CFG_REG, 18), 380 SUNXI_CCU_GATE(H3_CLK_USBOHCI3, "usb-ohci3", "hosc", 381 USBPHY_CFG_REG, 19), 382 }; 383 384 static void 385 sun8i_h3_ccu_init(struct sunxi_ccu_softc *sc) 386 { 387 uint32_t val; 388 389 /* Set AHB2 source to PLL_PERIPH/2 */ 390 val = CCU_READ(sc, AHB2_CFG_REG); 391 val &= ~AHB2_CLK_CFG; 392 val |= __SHIFTIN(AHB2_CLK_CFG_PLL_PERIPH0_2, AHB2_CLK_CFG); 393 CCU_WRITE(sc, AHB2_CFG_REG, val); 394 } 395 396 static int 397 sun8i_h3_ccu_match(device_t parent, cfdata_t cf, void *aux) 398 { 399 struct fdt_attach_args * const faa = aux; 400 401 return of_match_compatible(faa->faa_phandle, compatible); 402 } 403 404 static void 405 sun8i_h3_ccu_attach(device_t parent, device_t self, void *aux) 406 { 407 struct sunxi_ccu_softc * const sc = device_private(self); 408 struct fdt_attach_args * const faa = aux; 409 410 sc->sc_dev = self; 411 sc->sc_phandle = faa->faa_phandle; 412 sc->sc_bst = faa->faa_bst; 413 414 sc->sc_resets = sun8i_h3_ccu_resets; 415 sc->sc_nresets = __arraycount(sun8i_h3_ccu_resets); 416 417 sc->sc_clks = sun8i_h3_ccu_clks; 418 sc->sc_nclks = __arraycount(sun8i_h3_ccu_clks); 419 420 if (sunxi_ccu_attach(sc) != 0) 421 return; 422 423 aprint_naive("\n"); 424 aprint_normal(": H3 CCU\n"); 425 426 sun8i_h3_ccu_init(sc); 427 428 sunxi_ccu_print(sc); 429 } 430
Indexes created Thu Oct 02 10:09:58 GMT 2025