sun8i_h3_ccu.c revision 1.15
1 /* $NetBSD: sun8i_h3_ccu.c,v 1.15 2018/01/12 18:22:35 jakllsch Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * Copyright (c) 2017 Emmanuel Vadot <manu (at) freebsd.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 32 __KERNEL_RCSID(1, "$NetBSD: sun8i_h3_ccu.c,v 1.15 2018/01/12 18:22:35 jakllsch Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/systm.h> 38 39 #include <dev/fdt/fdtvar.h> 40 41 #include <arm/sunxi/sunxi_ccu.h> 42 #include <arm/sunxi/sun8i_h3_ccu.h> 43 44 #define PLL_CPUX_CTRL_REG 0x000 45 #define PLL_AUDIO_CTRL_REG 0x008 46 #define PLL_PERIPH0_CTRL_REG 0x028 47 #define AHB1_APB1_CFG_REG 0x054 48 #define APB2_CFG_REG 0x058 49 #define AHB2_CFG_REG 0x05c 50 #define AHB2_CLK_CFG __BITS(1,0) 51 #define AHB2_CLK_CFG_PLL_PERIPH0_2 1 52 #define BUS_CLK_GATING_REG0 0x060 53 #define BUS_CLK_GATING_REG2 0x068 54 #define BUS_CLK_GATING_REG3 0x06c 55 #define BUS_CLK_GATING_REG4 0x070 56 #define THS_CLK_REG 0x074 57 #define SDMMC0_CLK_REG 0x088 58 #define SDMMC1_CLK_REG 0x08c 59 #define SDMMC2_CLK_REG 0x090 60 #define SPI0_CLK_REG 0x0a0 61 #define SPI1_CLK_REG 0x0a4 62 #define USBPHY_CFG_REG 0x0cc 63 #define MBUS_RST_REG 0x0fc 64 #define AC_DIG_CLK_REG 0x140 65 #define BUS_SOFT_RST_REG0 0x2c0 66 #define BUS_SOFT_RST_REG1 0x2c4 67 #define BUS_SOFT_RST_REG2 0x2c8 68 #define BUS_SOFT_RST_REG3 0x2d0 69 #define BUS_SOFT_RST_REG4 0x2d8 70 71 static int sun8i_h3_ccu_match(device_t, cfdata_t, void *); 72 static void sun8i_h3_ccu_attach(device_t, device_t, void *); 73 74 static const char * const compatible[] = { 75 "allwinner,sun8i-h3-ccu", 76 "allwinner,sun50i-h5-ccu", 77 NULL 78 }; 79 80 CFATTACH_DECL_NEW(sunxi_h3_ccu, sizeof(struct sunxi_ccu_softc), 81 sun8i_h3_ccu_match, sun8i_h3_ccu_attach, NULL, NULL); 82 83 static struct sunxi_ccu_reset sun8i_h3_ccu_resets[] = { 84 SUNXI_CCU_RESET(H3_RST_USB_PHY0, USBPHY_CFG_REG, 0), 85 SUNXI_CCU_RESET(H3_RST_USB_PHY1, USBPHY_CFG_REG, 1), 86 SUNXI_CCU_RESET(H3_RST_USB_PHY2, USBPHY_CFG_REG, 2), 87 SUNXI_CCU_RESET(H3_RST_USB_PHY3, USBPHY_CFG_REG, 3), 88 89 SUNXI_CCU_RESET(H3_RST_MBUS, MBUS_RST_REG, 31), 90 91 SUNXI_CCU_RESET(H3_RST_BUS_CE, BUS_SOFT_RST_REG0, 5), 92 SUNXI_CCU_RESET(H3_RST_BUS_DMA, BUS_SOFT_RST_REG0, 6), 93 SUNXI_CCU_RESET(H3_RST_BUS_MMC0, BUS_SOFT_RST_REG0, 8), 94 SUNXI_CCU_RESET(H3_RST_BUS_MMC1, BUS_SOFT_RST_REG0, 9), 95 SUNXI_CCU_RESET(H3_RST_BUS_MMC2, BUS_SOFT_RST_REG0, 10), 96 SUNXI_CCU_RESET(H3_RST_BUS_NAND, BUS_SOFT_RST_REG0, 13), 97 SUNXI_CCU_RESET(H3_RST_BUS_DRAM, BUS_SOFT_RST_REG0, 14), 98 SUNXI_CCU_RESET(H3_RST_BUS_EMAC, BUS_SOFT_RST_REG0, 17), 99 SUNXI_CCU_RESET(H3_RST_BUS_TS, BUS_SOFT_RST_REG0, 18), 100 SUNXI_CCU_RESET(H3_RST_BUS_HSTIMER, BUS_SOFT_RST_REG0, 19), 101 SUNXI_CCU_RESET(H3_RST_BUS_SPI0, BUS_SOFT_RST_REG0, 20), 102 SUNXI_CCU_RESET(H3_RST_BUS_SPI1, BUS_SOFT_RST_REG0, 21), 103 SUNXI_CCU_RESET(H3_RST_BUS_OTG, BUS_SOFT_RST_REG0, 23), 104 SUNXI_CCU_RESET(H3_RST_BUS_EHCI0, BUS_SOFT_RST_REG0, 24), 105 SUNXI_CCU_RESET(H3_RST_BUS_EHCI1, BUS_SOFT_RST_REG0, 25), 106 SUNXI_CCU_RESET(H3_RST_BUS_EHCI2, BUS_SOFT_RST_REG0, 26), 107 SUNXI_CCU_RESET(H3_RST_BUS_EHCI3, BUS_SOFT_RST_REG0, 27), 108 SUNXI_CCU_RESET(H3_RST_BUS_OHCI0, BUS_SOFT_RST_REG0, 28), 109 SUNXI_CCU_RESET(H3_RST_BUS_OHCI1, BUS_SOFT_RST_REG0, 29), 110 SUNXI_CCU_RESET(H3_RST_BUS_OHCI2, BUS_SOFT_RST_REG0, 30), 111 SUNXI_CCU_RESET(H3_RST_BUS_OHCI3, BUS_SOFT_RST_REG0, 31), 112 113 SUNXI_CCU_RESET(H3_RST_BUS_VE, BUS_SOFT_RST_REG1, 0), 114 SUNXI_CCU_RESET(H3_RST_BUS_TCON0, BUS_SOFT_RST_REG1, 3), 115 SUNXI_CCU_RESET(H3_RST_BUS_TCON1, BUS_SOFT_RST_REG1, 4), 116 SUNXI_CCU_RESET(H3_RST_BUS_DEINTERLACE, BUS_SOFT_RST_REG1, 5), 117 SUNXI_CCU_RESET(H3_RST_BUS_CSI, BUS_SOFT_RST_REG1, 8), 118 SUNXI_CCU_RESET(H3_RST_BUS_TVE, BUS_SOFT_RST_REG1, 9), 119 SUNXI_CCU_RESET(H3_RST_BUS_HDMI0, BUS_SOFT_RST_REG1, 10), 120 SUNXI_CCU_RESET(H3_RST_BUS_HDMI1, BUS_SOFT_RST_REG1, 11), 121 SUNXI_CCU_RESET(H3_RST_BUS_DE, BUS_SOFT_RST_REG1, 12), 122 SUNXI_CCU_RESET(H3_RST_BUS_GPU, BUS_SOFT_RST_REG1, 20), 123 SUNXI_CCU_RESET(H3_RST_BUS_MSGBOX, BUS_SOFT_RST_REG1, 21), 124 SUNXI_CCU_RESET(H3_RST_BUS_SPINLOCK, BUS_SOFT_RST_REG1, 22), 125 SUNXI_CCU_RESET(H3_RST_BUS_DBG, BUS_SOFT_RST_REG1, 31), 126 127 SUNXI_CCU_RESET(H3_RST_BUS_EPHY, BUS_SOFT_RST_REG2, 2), 128 129 SUNXI_CCU_RESET(H3_RST_BUS_CODEC, BUS_SOFT_RST_REG3, 0), 130 SUNXI_CCU_RESET(H3_RST_BUS_SPDIF, BUS_SOFT_RST_REG3, 1), 131 SUNXI_CCU_RESET(H3_RST_BUS_THS, BUS_SOFT_RST_REG3, 8), 132 SUNXI_CCU_RESET(H3_RST_BUS_I2S0, BUS_SOFT_RST_REG3, 12), 133 SUNXI_CCU_RESET(H3_RST_BUS_I2S1, BUS_SOFT_RST_REG3, 13), 134 SUNXI_CCU_RESET(H3_RST_BUS_I2S2, BUS_SOFT_RST_REG3, 14), 135 136 SUNXI_CCU_RESET(H3_RST_BUS_I2C0, BUS_SOFT_RST_REG4, 0), 137 SUNXI_CCU_RESET(H3_RST_BUS_I2C1, BUS_SOFT_RST_REG4, 1), 138 SUNXI_CCU_RESET(H3_RST_BUS_I2C2, BUS_SOFT_RST_REG4, 2), 139 SUNXI_CCU_RESET(H3_RST_BUS_UART0, BUS_SOFT_RST_REG4, 16), 140 SUNXI_CCU_RESET(H3_RST_BUS_UART1, BUS_SOFT_RST_REG4, 17), 141 SUNXI_CCU_RESET(H3_RST_BUS_UART2, BUS_SOFT_RST_REG4, 18), 142 SUNXI_CCU_RESET(H3_RST_BUS_UART3, BUS_SOFT_RST_REG4, 19), 143 SUNXI_CCU_RESET(H3_RST_BUS_SCR, BUS_SOFT_RST_REG4, 20), 144 }; 145 146 static const char *ahb1_parents[] = { "losc", "hosc", "axi", "pll_periph0" }; 147 static const char *ahb2_parents[] = { "ahb1", "pll_periph0" }; 148 static const char *apb1_parents[] = { "ahb1" }; 149 static const char *apb2_parents[] = { "losc", "hosc", "pll_periph0" }; 150 static const char *mod_parents[] = { "hosc", "pll_periph0", "pll_periph1" }; 151 static const char *ths_parents[] = { "hosc" }; 152 153 static const struct sunxi_ccu_nkmp_tbl sun8i_h3_cpux_table[] = { 154 { 60000000, 9, 0, 0, 2 }, 155 { 66000000, 10, 0, 0, 2 }, 156 { 72000000, 11, 0, 0, 2 }, 157 { 78000000, 12, 0, 0, 2 }, 158 { 84000000, 13, 0, 0, 2 }, 159 { 90000000, 14, 0, 0, 2 }, 160 { 96000000, 15, 0, 0, 2 }, 161 { 102000000, 16, 0, 0, 2 }, 162 { 108000000, 17, 0, 0, 2 }, 163 { 114000000, 18, 0, 0, 2 }, 164 { 120000000, 9, 0, 0, 1 }, 165 { 132000000, 10, 0, 0, 1 }, 166 { 144000000, 11, 0, 0, 1 }, 167 { 156000000, 12, 0, 0, 1 }, 168 { 168000000, 13, 0, 0, 1 }, 169 { 180000000, 14, 0, 0, 1 }, 170 { 192000000, 15, 0, 0, 1 }, 171 { 204000000, 16, 0, 0, 1 }, 172 { 216000000, 17, 0, 0, 1 }, 173 { 228000000, 18, 0, 0, 1 }, 174 { 240000000, 9, 0, 0, 0 }, 175 { 264000000, 10, 0, 0, 0 }, 176 { 288000000, 11, 0, 0, 0 }, 177 { 312000000, 12, 0, 0, 0 }, 178 { 336000000, 13, 0, 0, 0 }, 179 { 360000000, 14, 0, 0, 0 }, 180 { 384000000, 15, 0, 0, 0 }, 181 { 408000000, 16, 0, 0, 0 }, 182 { 432000000, 17, 0, 0, 0 }, 183 { 456000000, 18, 0, 0, 0 }, 184 { 480000000, 19, 0, 0, 0 }, 185 { 504000000, 20, 0, 0, 0 }, 186 { 528000000, 21, 0, 0, 0 }, 187 { 552000000, 22, 0, 0, 0 }, 188 { 576000000, 23, 0, 0, 0 }, 189 { 600000000, 24, 0, 0, 0 }, 190 { 624000000, 25, 0, 0, 0 }, 191 { 648000000, 26, 0, 0, 0 }, 192 { 672000000, 27, 0, 0, 0 }, 193 { 696000000, 28, 0, 0, 0 }, 194 { 720000000, 29, 0, 0, 0 }, 195 { 768000000, 15, 1, 0, 0 }, 196 { 792000000, 10, 2, 0, 0 }, 197 { 816000000, 16, 1, 0, 0 }, 198 { 864000000, 17, 1, 0, 0 }, 199 { 912000000, 18, 1, 0, 0 }, 200 { 936000000, 12, 2, 0, 0 }, 201 { 960000000, 19, 1, 0, 0 }, 202 { 1008000000, 20, 1, 0, 0 }, 203 { 1056000000, 21, 1, 0, 0 }, 204 { 1080000000, 14, 2, 0, 0 }, 205 { 1104000000, 22, 1, 0, 0 }, 206 { 1152000000, 23, 1, 0, 0 }, 207 { 1200000000, 24, 1, 0, 0 }, 208 { 1224000000, 16, 2, 0, 0 }, 209 { 1248000000, 25, 1, 0, 0 }, 210 { 1296000000, 26, 1, 0, 0 }, 211 { 1344000000, 27, 1, 0, 0 }, 212 { 1368000000, 18, 2, 0, 0 }, 213 { 1392000000, 28, 1, 0, 0 }, 214 { 1440000000, 29, 1, 0, 0 }, 215 { 1512000000, 20, 2, 0, 0 }, 216 { 1536000000, 15, 3, 0, 0 }, 217 { 1584000000, 21, 2, 0, 0 }, 218 { 1632000000, 16, 3, 0, 0 }, 219 { 1656000000, 22, 2, 0, 0 }, 220 { 1728000000, 23, 2, 0, 0 }, 221 { 1800000000, 24, 2, 0, 0 }, 222 { 1824000000, 18, 3, 0, 0 }, 223 { 1872000000, 25, 2, 0, 0 }, 224 { 0 } 225 }; 226 227 static const struct sunxi_ccu_nkmp_tbl sun8i_h3_ac_dig_table[] = { 228 { 24576000, 13, 0, 0, 13 }, 229 { 0 } 230 }; 231 232 static struct sunxi_ccu_clk sun8i_h3_ccu_clks[] = { 233 SUNXI_CCU_NKMP_TABLE(H3_CLK_CPUX, "pll_cpux", "hosc", 234 PLL_CPUX_CTRL_REG, /* reg */ 235 __BITS(12,8), /* n */ 236 __BITS(5,4), /* k */ 237 __BITS(1,0), /* m */ 238 __BITS(17,16), /* p */ 239 __BIT(31), /* enable */ 240 __BIT(28), /* lock */ 241 sun8i_h3_cpux_table, /* table */ 242 SUNXI_CCU_NKMP_SCALE_CLOCK | SUNXI_CCU_NKMP_FACTOR_P_POW2), 243 244 SUNXI_CCU_NKMP(H3_CLK_PLL_PERIPH0, "pll_periph0", "hosc", 245 PLL_PERIPH0_CTRL_REG, /* reg */ 246 __BITS(12,8), /* n */ 247 __BITS(5,4), /* k */ 248 0, /* m */ 249 __BITS(17,16), /* p */ 250 __BIT(31), /* enable */ 251 SUNXI_CCU_NKMP_DIVIDE_BY_TWO), 252 253 SUNXI_CCU_NKMP_TABLE(H3_CLK_PLL_AUDIO_BASE, "pll_audio", "hosc", 254 PLL_AUDIO_CTRL_REG, /* reg */ 255 __BITS(14,8), /* n */ 256 0, /* k */ 257 __BITS(4,0), /* m */ 258 __BITS(19,16), /* p */ 259 __BIT(31), /* enable */ 260 __BIT(28), /* lock */ 261 sun8i_h3_ac_dig_table, /* table */ 262 0), 263 264 SUNXI_CCU_PREDIV(H3_CLK_AHB1, "ahb1", ahb1_parents, 265 AHB1_APB1_CFG_REG, /* reg */ 266 __BITS(7,6), /* prediv */ 267 __BIT(3), /* prediv_sel */ 268 __BITS(5,4), /* div */ 269 __BITS(13,12), /* sel */ 270 SUNXI_CCU_PREDIV_POWER_OF_TWO), 271 272 SUNXI_CCU_PREDIV(H3_CLK_AHB2, "ahb2", ahb2_parents, 273 AHB2_CFG_REG, /* reg */ 274 0, /* prediv */ 275 __BIT(1), /* prediv_sel */ 276 0, /* div */ 277 __BITS(1,0), /* sel */ 278 SUNXI_CCU_PREDIV_DIVIDE_BY_TWO), 279 280 SUNXI_CCU_DIV(H3_CLK_APB1, "apb1", apb1_parents, 281 AHB1_APB1_CFG_REG, /* reg */ 282 __BITS(9,8), /* div */ 283 0, /* sel */ 284 SUNXI_CCU_DIV_POWER_OF_TWO|SUNXI_CCU_DIV_ZERO_IS_ONE), 285 286 SUNXI_CCU_NM(H3_CLK_APB2, "apb2", apb2_parents, 287 APB2_CFG_REG, /* reg */ 288 __BITS(17,16), /* n */ 289 __BITS(4,0), /* m */ 290 __BITS(25,24), /* sel */ 291 0, /* enable */ 292 SUNXI_CCU_NM_POWER_OF_TWO), 293 294 SUNXI_CCU_DIV_GATE(H3_CLK_THS, "ths", ths_parents, 295 THS_CLK_REG, /* reg */ 296 __BITS(1,0), /* div */ 297 __BITS(25,24), /* sel */ 298 __BIT(31), /* enable */ 299 SUNXI_CCU_DIV_TIMES_TWO), 300 301 SUNXI_CCU_NM(H3_CLK_MMC0, "mmc0", mod_parents, 302 SDMMC0_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31), 303 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 304 SUNXI_CCU_PHASE(H3_CLK_MMC0_SAMPLE, "mmc0_sample", "mmc0", 305 SDMMC0_CLK_REG, __BITS(22,20)), 306 SUNXI_CCU_PHASE(H3_CLK_MMC0_OUTPUT, "mmc0_output", "mmc0", 307 SDMMC0_CLK_REG, __BITS(10,8)), 308 SUNXI_CCU_NM(H3_CLK_MMC1, "mmc1", mod_parents, 309 SDMMC1_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31), 310 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 311 SUNXI_CCU_PHASE(H3_CLK_MMC1_SAMPLE, "mmc1_sample", "mmc1", 312 SDMMC1_CLK_REG, __BITS(22,20)), 313 SUNXI_CCU_PHASE(H3_CLK_MMC1_OUTPUT, "mmc1_output", "mmc1", 314 SDMMC1_CLK_REG, __BITS(10,8)), 315 SUNXI_CCU_NM(H3_CLK_MMC2, "mmc2", mod_parents, 316 SDMMC2_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31), 317 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 318 SUNXI_CCU_PHASE(H3_CLK_MMC2_SAMPLE, "mmc2_sample", "mmc2", 319 SDMMC2_CLK_REG, __BITS(22,20)), 320 SUNXI_CCU_PHASE(H3_CLK_MMC2_OUTPUT, "mmc2_output", "mmc2", 321 SDMMC2_CLK_REG, __BITS(10,8)), 322 323 SUNXI_CCU_NM(H3_CLK_SPI0, "spi0", mod_parents, 324 SPI0_CLK_REG, /* reg */ 325 __BITS(17,16), /* n */ 326 __BITS(3,0), /* m */ 327 __BITS(25,24), /* sel */ 328 __BIT(31), /* enable */ 329 SUNXI_CCU_NM_ROUND_DOWN), 330 SUNXI_CCU_NM(H3_CLK_SPI1, "spi1", mod_parents, 331 SPI1_CLK_REG, /* reg */ 332 __BITS(17,16), /* n */ 333 __BITS(3,0), /* m */ 334 __BITS(25,24), /* sel */ 335 __BIT(31), /* enable */ 336 SUNXI_CCU_NM_ROUND_DOWN), 337 338 SUNXI_CCU_GATE(H3_CLK_AC_DIG, "ac_dig", "pll_audio", 339 AC_DIG_CLK_REG, 31), 340 341 SUNXI_CCU_GATE(H3_CLK_BUS_DMA, "bus-dma", "ahb1", 342 BUS_CLK_GATING_REG0, 6), 343 SUNXI_CCU_GATE(H3_CLK_BUS_MMC0, "bus-mmc0", "ahb1", 344 BUS_CLK_GATING_REG0, 8), 345 SUNXI_CCU_GATE(H3_CLK_BUS_MMC1, "bus-mmc1", "ahb1", 346 BUS_CLK_GATING_REG0, 9), 347 SUNXI_CCU_GATE(H3_CLK_BUS_MMC2, "bus-mmc2", "ahb1", 348 BUS_CLK_GATING_REG0, 10), 349 SUNXI_CCU_GATE(H3_CLK_BUS_EMAC, "bus-emac", "ahb2", 350 BUS_CLK_GATING_REG0, 17), 351 SUNXI_CCU_GATE(H3_CLK_BUS_SPI0, "bus-spi0", "ahb1", 352 BUS_CLK_GATING_REG0, 20), 353 SUNXI_CCU_GATE(H3_CLK_BUS_SPI1, "bus-spi1", "ahb1", 354 BUS_CLK_GATING_REG0, 21), 355 SUNXI_CCU_GATE(H3_CLK_BUS_OTG, "bus-otg", "ahb1", 356 BUS_CLK_GATING_REG0, 23), 357 SUNXI_CCU_GATE(H3_CLK_BUS_EHCI0, "bus-ehci0", "ahb1", 358 BUS_CLK_GATING_REG0, 24), 359 SUNXI_CCU_GATE(H3_CLK_BUS_EHCI1, "bus-ehci1", "ahb2", 360 BUS_CLK_GATING_REG0, 25), 361 SUNXI_CCU_GATE(H3_CLK_BUS_EHCI2, "bus-ehci2", "ahb2", 362 BUS_CLK_GATING_REG0, 26), 363 SUNXI_CCU_GATE(H3_CLK_BUS_EHCI3, "bus-ehci3", "ahb2", 364 BUS_CLK_GATING_REG0, 27), 365 SUNXI_CCU_GATE(H3_CLK_BUS_OHCI0, "bus-ohci0", "ahb1", 366 BUS_CLK_GATING_REG0, 28), 367 SUNXI_CCU_GATE(H3_CLK_BUS_OHCI1, "bus-ohci1", "ahb2", 368 BUS_CLK_GATING_REG0, 29), 369 SUNXI_CCU_GATE(H3_CLK_BUS_OHCI2, "bus-ohci2", "ahb2", 370 BUS_CLK_GATING_REG0, 30), 371 SUNXI_CCU_GATE(H3_CLK_BUS_OHCI3, "bus-ohci3", "ahb2", 372 BUS_CLK_GATING_REG0, 31), 373 374 SUNXI_CCU_GATE(H3_CLK_BUS_CODEC, "bus-codec", "apb1", 375 BUS_CLK_GATING_REG2, 0), 376 SUNXI_CCU_GATE(H3_CLK_BUS_PIO, "bus-pio", "apb1", 377 BUS_CLK_GATING_REG2, 5), 378 SUNXI_CCU_GATE(H3_CLK_BUS_THS, "bus-ths", "apb2", 379 BUS_CLK_GATING_REG2, 8), 380 381 SUNXI_CCU_GATE(H3_CLK_BUS_I2C0, "bus-i2c0", "apb2", 382 BUS_CLK_GATING_REG3, 0), 383 SUNXI_CCU_GATE(H3_CLK_BUS_I2C1, "bus-i2c1", "apb2", 384 BUS_CLK_GATING_REG3, 1), 385 SUNXI_CCU_GATE(H3_CLK_BUS_I2C2, "bus-i2c2", "apb2", 386 BUS_CLK_GATING_REG3, 2), 387 SUNXI_CCU_GATE(H3_CLK_BUS_UART0, "bus-uart0", "apb2", 388 BUS_CLK_GATING_REG3, 16), 389 SUNXI_CCU_GATE(H3_CLK_BUS_UART1, "bus-uart1", "apb2", 390 BUS_CLK_GATING_REG3, 17), 391 SUNXI_CCU_GATE(H3_CLK_BUS_UART2, "bus-uart2", "apb2", 392 BUS_CLK_GATING_REG3, 18), 393 SUNXI_CCU_GATE(H3_CLK_BUS_UART3, "bus-uart3", "apb2", 394 BUS_CLK_GATING_REG3, 19), 395 396 SUNXI_CCU_GATE(H3_CLK_BUS_EPHY, "bus-ephy", "ahb1", 397 BUS_CLK_GATING_REG4, 0), 398 399 SUNXI_CCU_GATE(H3_CLK_USBPHY0, "usb-phy0", "hosc", 400 USBPHY_CFG_REG, 8), 401 SUNXI_CCU_GATE(H3_CLK_USBPHY1, "usb-phy1", "hosc", 402 USBPHY_CFG_REG, 9), 403 SUNXI_CCU_GATE(H3_CLK_USBPHY2, "usb-phy2", "hosc", 404 USBPHY_CFG_REG, 10), 405 SUNXI_CCU_GATE(H3_CLK_USBPHY3, "usb-phy3", "hosc", 406 USBPHY_CFG_REG, 11), 407 SUNXI_CCU_GATE(H3_CLK_USBOHCI0, "usb-ohci0", "hosc", 408 USBPHY_CFG_REG, 16), 409 SUNXI_CCU_GATE(H3_CLK_USBOHCI1, "usb-ohci1", "hosc", 410 USBPHY_CFG_REG, 17), 411 SUNXI_CCU_GATE(H3_CLK_USBOHCI2, "usb-ohci2", "hosc", 412 USBPHY_CFG_REG, 18), 413 SUNXI_CCU_GATE(H3_CLK_USBOHCI3, "usb-ohci3", "hosc", 414 USBPHY_CFG_REG, 19), 415 }; 416 417 static void 418 sun8i_h3_ccu_init(struct sunxi_ccu_softc *sc) 419 { 420 uint32_t val; 421 422 /* Set AHB2 source to PLL_PERIPH/2 */ 423 val = CCU_READ(sc, AHB2_CFG_REG); 424 val &= ~AHB2_CLK_CFG; 425 val |= __SHIFTIN(AHB2_CLK_CFG_PLL_PERIPH0_2, AHB2_CLK_CFG); 426 CCU_WRITE(sc, AHB2_CFG_REG, val); 427 } 428 429 static int 430 sun8i_h3_ccu_match(device_t parent, cfdata_t cf, void *aux) 431 { 432 struct fdt_attach_args * const faa = aux; 433 434 return of_match_compatible(faa->faa_phandle, compatible); 435 } 436 437 static void 438 sun8i_h3_ccu_attach(device_t parent, device_t self, void *aux) 439 { 440 struct sunxi_ccu_softc * const sc = device_private(self); 441 struct fdt_attach_args * const faa = aux; 442 443 sc->sc_dev = self; 444 sc->sc_phandle = faa->faa_phandle; 445 sc->sc_bst = faa->faa_bst; 446 447 sc->sc_resets = sun8i_h3_ccu_resets; 448 sc->sc_nresets = __arraycount(sun8i_h3_ccu_resets); 449 450 sc->sc_clks = sun8i_h3_ccu_clks; 451 sc->sc_nclks = __arraycount(sun8i_h3_ccu_clks); 452 453 if (sunxi_ccu_attach(sc) != 0) 454 return; 455 456 aprint_naive("\n"); 457 aprint_normal(": H3 CCU\n"); 458 459 sun8i_h3_ccu_init(sc); 460 461 sunxi_ccu_print(sc); 462 } 463
Indexes created Thu Oct 02 10:09:58 GMT 2025