sun8i_h3_ccu.c revision 1.16
1 /* $NetBSD: sun8i_h3_ccu.c,v 1.16 2019/01/31 01:49:28 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * Copyright (c) 2017 Emmanuel Vadot <manu (at) freebsd.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 32 __KERNEL_RCSID(1, "$NetBSD: sun8i_h3_ccu.c,v 1.16 2019/01/31 01:49:28 jmcneill Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/systm.h> 38 39 #include <dev/fdt/fdtvar.h> 40 41 #include <arm/sunxi/sunxi_ccu.h> 42 #include <arm/sunxi/sun8i_h3_ccu.h> 43 44 #define PLL_CPUX_CTRL_REG 0x000 45 #define PLL_AUDIO_CTRL_REG 0x008 46 #define PLL_VIDEO_CTRL_REG 0x010 47 #define PLL_PERIPH0_CTRL_REG 0x028 48 #define PLL_DE_CTRL_REG 0x048 49 #define AHB1_APB1_CFG_REG 0x054 50 #define APB2_CFG_REG 0x058 51 #define AHB2_CFG_REG 0x05c 52 #define AHB2_CLK_CFG __BITS(1,0) 53 #define AHB2_CLK_CFG_PLL_PERIPH0_2 1 54 #define BUS_CLK_GATING_REG0 0x060 55 #define BUS_CLK_GATING_REG1 0x064 56 #define BUS_CLK_GATING_REG2 0x068 57 #define BUS_CLK_GATING_REG3 0x06c 58 #define BUS_CLK_GATING_REG4 0x070 59 #define THS_CLK_REG 0x074 60 #define SDMMC0_CLK_REG 0x088 61 #define SDMMC1_CLK_REG 0x08c 62 #define SDMMC2_CLK_REG 0x090 63 #define SPI0_CLK_REG 0x0a0 64 #define SPI1_CLK_REG 0x0a4 65 #define USBPHY_CFG_REG 0x0cc 66 #define MBUS_RST_REG 0x0fc 67 #define DE_CLK_REG 0x104 68 #define TCON0_CLK_REG 0x118 69 #define AC_DIG_CLK_REG 0x140 70 #define HDMI_CLK_REG 0x150 71 #define HDMI_SLOW_CLK_REG 0x154 72 #define BUS_SOFT_RST_REG0 0x2c0 73 #define BUS_SOFT_RST_REG1 0x2c4 74 #define BUS_SOFT_RST_REG2 0x2c8 75 #define BUS_SOFT_RST_REG3 0x2d0 76 #define BUS_SOFT_RST_REG4 0x2d8 77 78 static int sun8i_h3_ccu_match(device_t, cfdata_t, void *); 79 static void sun8i_h3_ccu_attach(device_t, device_t, void *); 80 81 static const char * const compatible[] = { 82 "allwinner,sun8i-h3-ccu", 83 "allwinner,sun50i-h5-ccu", 84 NULL 85 }; 86 87 CFATTACH_DECL_NEW(sunxi_h3_ccu, sizeof(struct sunxi_ccu_softc), 88 sun8i_h3_ccu_match, sun8i_h3_ccu_attach, NULL, NULL); 89 90 static struct sunxi_ccu_reset sun8i_h3_ccu_resets[] = { 91 SUNXI_CCU_RESET(H3_RST_USB_PHY0, USBPHY_CFG_REG, 0), 92 SUNXI_CCU_RESET(H3_RST_USB_PHY1, USBPHY_CFG_REG, 1), 93 SUNXI_CCU_RESET(H3_RST_USB_PHY2, USBPHY_CFG_REG, 2), 94 SUNXI_CCU_RESET(H3_RST_USB_PHY3, USBPHY_CFG_REG, 3), 95 96 SUNXI_CCU_RESET(H3_RST_MBUS, MBUS_RST_REG, 31), 97 98 SUNXI_CCU_RESET(H3_RST_BUS_CE, BUS_SOFT_RST_REG0, 5), 99 SUNXI_CCU_RESET(H3_RST_BUS_DMA, BUS_SOFT_RST_REG0, 6), 100 SUNXI_CCU_RESET(H3_RST_BUS_MMC0, BUS_SOFT_RST_REG0, 8), 101 SUNXI_CCU_RESET(H3_RST_BUS_MMC1, BUS_SOFT_RST_REG0, 9), 102 SUNXI_CCU_RESET(H3_RST_BUS_MMC2, BUS_SOFT_RST_REG0, 10), 103 SUNXI_CCU_RESET(H3_RST_BUS_NAND, BUS_SOFT_RST_REG0, 13), 104 SUNXI_CCU_RESET(H3_RST_BUS_DRAM, BUS_SOFT_RST_REG0, 14), 105 SUNXI_CCU_RESET(H3_RST_BUS_EMAC, BUS_SOFT_RST_REG0, 17), 106 SUNXI_CCU_RESET(H3_RST_BUS_TS, BUS_SOFT_RST_REG0, 18), 107 SUNXI_CCU_RESET(H3_RST_BUS_HSTIMER, BUS_SOFT_RST_REG0, 19), 108 SUNXI_CCU_RESET(H3_RST_BUS_SPI0, BUS_SOFT_RST_REG0, 20), 109 SUNXI_CCU_RESET(H3_RST_BUS_SPI1, BUS_SOFT_RST_REG0, 21), 110 SUNXI_CCU_RESET(H3_RST_BUS_OTG, BUS_SOFT_RST_REG0, 23), 111 SUNXI_CCU_RESET(H3_RST_BUS_EHCI0, BUS_SOFT_RST_REG0, 24), 112 SUNXI_CCU_RESET(H3_RST_BUS_EHCI1, BUS_SOFT_RST_REG0, 25), 113 SUNXI_CCU_RESET(H3_RST_BUS_EHCI2, BUS_SOFT_RST_REG0, 26), 114 SUNXI_CCU_RESET(H3_RST_BUS_EHCI3, BUS_SOFT_RST_REG0, 27), 115 SUNXI_CCU_RESET(H3_RST_BUS_OHCI0, BUS_SOFT_RST_REG0, 28), 116 SUNXI_CCU_RESET(H3_RST_BUS_OHCI1, BUS_SOFT_RST_REG0, 29), 117 SUNXI_CCU_RESET(H3_RST_BUS_OHCI2, BUS_SOFT_RST_REG0, 30), 118 SUNXI_CCU_RESET(H3_RST_BUS_OHCI3, BUS_SOFT_RST_REG0, 31), 119 120 SUNXI_CCU_RESET(H3_RST_BUS_VE, BUS_SOFT_RST_REG1, 0), 121 SUNXI_CCU_RESET(H3_RST_BUS_TCON0, BUS_SOFT_RST_REG1, 3), 122 SUNXI_CCU_RESET(H3_RST_BUS_TCON1, BUS_SOFT_RST_REG1, 4), 123 SUNXI_CCU_RESET(H3_RST_BUS_DEINTERLACE, BUS_SOFT_RST_REG1, 5), 124 SUNXI_CCU_RESET(H3_RST_BUS_CSI, BUS_SOFT_RST_REG1, 8), 125 SUNXI_CCU_RESET(H3_RST_BUS_TVE, BUS_SOFT_RST_REG1, 9), 126 SUNXI_CCU_RESET(H3_RST_BUS_HDMI0, BUS_SOFT_RST_REG1, 10), 127 SUNXI_CCU_RESET(H3_RST_BUS_HDMI1, BUS_SOFT_RST_REG1, 11), 128 SUNXI_CCU_RESET(H3_RST_BUS_DE, BUS_SOFT_RST_REG1, 12), 129 SUNXI_CCU_RESET(H3_RST_BUS_GPU, BUS_SOFT_RST_REG1, 20), 130 SUNXI_CCU_RESET(H3_RST_BUS_MSGBOX, BUS_SOFT_RST_REG1, 21), 131 SUNXI_CCU_RESET(H3_RST_BUS_SPINLOCK, BUS_SOFT_RST_REG1, 22), 132 SUNXI_CCU_RESET(H3_RST_BUS_DBG, BUS_SOFT_RST_REG1, 31), 133 134 SUNXI_CCU_RESET(H3_RST_BUS_EPHY, BUS_SOFT_RST_REG2, 2), 135 136 SUNXI_CCU_RESET(H3_RST_BUS_CODEC, BUS_SOFT_RST_REG3, 0), 137 SUNXI_CCU_RESET(H3_RST_BUS_SPDIF, BUS_SOFT_RST_REG3, 1), 138 SUNXI_CCU_RESET(H3_RST_BUS_THS, BUS_SOFT_RST_REG3, 8), 139 SUNXI_CCU_RESET(H3_RST_BUS_I2S0, BUS_SOFT_RST_REG3, 12), 140 SUNXI_CCU_RESET(H3_RST_BUS_I2S1, BUS_SOFT_RST_REG3, 13), 141 SUNXI_CCU_RESET(H3_RST_BUS_I2S2, BUS_SOFT_RST_REG3, 14), 142 143 SUNXI_CCU_RESET(H3_RST_BUS_I2C0, BUS_SOFT_RST_REG4, 0), 144 SUNXI_CCU_RESET(H3_RST_BUS_I2C1, BUS_SOFT_RST_REG4, 1), 145 SUNXI_CCU_RESET(H3_RST_BUS_I2C2, BUS_SOFT_RST_REG4, 2), 146 SUNXI_CCU_RESET(H3_RST_BUS_UART0, BUS_SOFT_RST_REG4, 16), 147 SUNXI_CCU_RESET(H3_RST_BUS_UART1, BUS_SOFT_RST_REG4, 17), 148 SUNXI_CCU_RESET(H3_RST_BUS_UART2, BUS_SOFT_RST_REG4, 18), 149 SUNXI_CCU_RESET(H3_RST_BUS_UART3, BUS_SOFT_RST_REG4, 19), 150 SUNXI_CCU_RESET(H3_RST_BUS_SCR, BUS_SOFT_RST_REG4, 20), 151 }; 152 153 static const char *ahb1_parents[] = { "losc", "hosc", "axi", "pll_periph0" }; 154 static const char *ahb2_parents[] = { "ahb1", "pll_periph0" }; 155 static const char *apb1_parents[] = { "ahb1" }; 156 static const char *apb2_parents[] = { "losc", "hosc", "pll_periph0" }; 157 static const char *mod_parents[] = { "hosc", "pll_periph0", "pll_periph1" }; 158 static const char *ths_parents[] = { "hosc" }; 159 static const char *de_parents[] = { "pll_periph0_2x", "pll_de" }; 160 static const char *hdmi_parents[] = { "pll_video" }; 161 static const char *tcon0_parents[] = { "pll_video" }; 162 163 static const struct sunxi_ccu_nkmp_tbl sun8i_h3_cpux_table[] = { 164 { 60000000, 9, 0, 0, 2 }, 165 { 66000000, 10, 0, 0, 2 }, 166 { 72000000, 11, 0, 0, 2 }, 167 { 78000000, 12, 0, 0, 2 }, 168 { 84000000, 13, 0, 0, 2 }, 169 { 90000000, 14, 0, 0, 2 }, 170 { 96000000, 15, 0, 0, 2 }, 171 { 102000000, 16, 0, 0, 2 }, 172 { 108000000, 17, 0, 0, 2 }, 173 { 114000000, 18, 0, 0, 2 }, 174 { 120000000, 9, 0, 0, 1 }, 175 { 132000000, 10, 0, 0, 1 }, 176 { 144000000, 11, 0, 0, 1 }, 177 { 156000000, 12, 0, 0, 1 }, 178 { 168000000, 13, 0, 0, 1 }, 179 { 180000000, 14, 0, 0, 1 }, 180 { 192000000, 15, 0, 0, 1 }, 181 { 204000000, 16, 0, 0, 1 }, 182 { 216000000, 17, 0, 0, 1 }, 183 { 228000000, 18, 0, 0, 1 }, 184 { 240000000, 9, 0, 0, 0 }, 185 { 264000000, 10, 0, 0, 0 }, 186 { 288000000, 11, 0, 0, 0 }, 187 { 312000000, 12, 0, 0, 0 }, 188 { 336000000, 13, 0, 0, 0 }, 189 { 360000000, 14, 0, 0, 0 }, 190 { 384000000, 15, 0, 0, 0 }, 191 { 408000000, 16, 0, 0, 0 }, 192 { 432000000, 17, 0, 0, 0 }, 193 { 456000000, 18, 0, 0, 0 }, 194 { 480000000, 19, 0, 0, 0 }, 195 { 504000000, 20, 0, 0, 0 }, 196 { 528000000, 21, 0, 0, 0 }, 197 { 552000000, 22, 0, 0, 0 }, 198 { 576000000, 23, 0, 0, 0 }, 199 { 600000000, 24, 0, 0, 0 }, 200 { 624000000, 25, 0, 0, 0 }, 201 { 648000000, 26, 0, 0, 0 }, 202 { 672000000, 27, 0, 0, 0 }, 203 { 696000000, 28, 0, 0, 0 }, 204 { 720000000, 29, 0, 0, 0 }, 205 { 768000000, 15, 1, 0, 0 }, 206 { 792000000, 10, 2, 0, 0 }, 207 { 816000000, 16, 1, 0, 0 }, 208 { 864000000, 17, 1, 0, 0 }, 209 { 912000000, 18, 1, 0, 0 }, 210 { 936000000, 12, 2, 0, 0 }, 211 { 960000000, 19, 1, 0, 0 }, 212 { 1008000000, 20, 1, 0, 0 }, 213 { 1056000000, 21, 1, 0, 0 }, 214 { 1080000000, 14, 2, 0, 0 }, 215 { 1104000000, 22, 1, 0, 0 }, 216 { 1152000000, 23, 1, 0, 0 }, 217 { 1200000000, 24, 1, 0, 0 }, 218 { 1224000000, 16, 2, 0, 0 }, 219 { 1248000000, 25, 1, 0, 0 }, 220 { 1296000000, 26, 1, 0, 0 }, 221 { 1344000000, 27, 1, 0, 0 }, 222 { 1368000000, 18, 2, 0, 0 }, 223 { 1392000000, 28, 1, 0, 0 }, 224 { 1440000000, 29, 1, 0, 0 }, 225 { 1512000000, 20, 2, 0, 0 }, 226 { 1536000000, 15, 3, 0, 0 }, 227 { 1584000000, 21, 2, 0, 0 }, 228 { 1632000000, 16, 3, 0, 0 }, 229 { 1656000000, 22, 2, 0, 0 }, 230 { 1728000000, 23, 2, 0, 0 }, 231 { 1800000000, 24, 2, 0, 0 }, 232 { 1824000000, 18, 3, 0, 0 }, 233 { 1872000000, 25, 2, 0, 0 }, 234 { 0 } 235 }; 236 237 static const struct sunxi_ccu_nkmp_tbl sun8i_h3_ac_dig_table[] = { 238 { 24576000, 13, 0, 0, 13 }, 239 { 0 } 240 }; 241 242 static struct sunxi_ccu_clk sun8i_h3_ccu_clks[] = { 243 SUNXI_CCU_NKMP_TABLE(H3_CLK_CPUX, "pll_cpux", "hosc", 244 PLL_CPUX_CTRL_REG, /* reg */ 245 __BITS(12,8), /* n */ 246 __BITS(5,4), /* k */ 247 __BITS(1,0), /* m */ 248 __BITS(17,16), /* p */ 249 __BIT(31), /* enable */ 250 __BIT(28), /* lock */ 251 sun8i_h3_cpux_table, /* table */ 252 SUNXI_CCU_NKMP_SCALE_CLOCK | SUNXI_CCU_NKMP_FACTOR_P_POW2), 253 254 SUNXI_CCU_NKMP(H3_CLK_PLL_PERIPH0, "pll_periph0", "hosc", 255 PLL_PERIPH0_CTRL_REG, /* reg */ 256 __BITS(12,8), /* n */ 257 __BITS(5,4), /* k */ 258 0, /* m */ 259 __BITS(17,16), /* p */ 260 __BIT(31), /* enable */ 261 SUNXI_CCU_NKMP_DIVIDE_BY_TWO), 262 263 SUNXI_CCU_FIXED_FACTOR(H3_CLK_PLL_PERIPH0_2X, "pll_periph0_2x", "pll_periph0", 1, 2), 264 265 SUNXI_CCU_FRACTIONAL(H3_CLK_PLL_VIDEO, "pll_video", "hosc", 266 PLL_VIDEO_CTRL_REG, /* reg */ 267 __BITS(14,8), /* m */ 268 16, /* m_min */ 269 50, /* m_max */ 270 __BIT(24), /* div_en */ 271 __BIT(25), /* frac_sel */ 272 270000000, 297000000, /* frac values */ 273 __BITS(3,0), /* prediv */ 274 4, /* prediv_val */ 275 __BIT(31), /* enable */ 276 SUNXI_CCU_FRACTIONAL_PLUSONE | SUNXI_CCU_FRACTIONAL_SET_ENABLE), 277 278 SUNXI_CCU_NKMP_TABLE(H3_CLK_PLL_AUDIO_BASE, "pll_audio", "hosc", 279 PLL_AUDIO_CTRL_REG, /* reg */ 280 __BITS(14,8), /* n */ 281 0, /* k */ 282 __BITS(4,0), /* m */ 283 __BITS(19,16), /* p */ 284 __BIT(31), /* enable */ 285 __BIT(28), /* lock */ 286 sun8i_h3_ac_dig_table, /* table */ 287 0), 288 289 SUNXI_CCU_FRACTIONAL(H3_CLK_PLL_DE, "pll_de", "hosc", 290 PLL_DE_CTRL_REG, /* reg */ 291 __BITS(14,8), /* m */ 292 16, /* m_min */ 293 50, /* m_max */ 294 __BIT(24), /* div_en */ 295 __BIT(25), /* frac_sel */ 296 270000000, 297000000, /* frac values */ 297 __BITS(3,0), /* prediv */ 298 2, /* prediv_val */ 299 __BIT(31), /* enable */ 300 SUNXI_CCU_FRACTIONAL_PLUSONE | SUNXI_CCU_FRACTIONAL_SET_ENABLE), 301 302 SUNXI_CCU_PREDIV(H3_CLK_AHB1, "ahb1", ahb1_parents, 303 AHB1_APB1_CFG_REG, /* reg */ 304 __BITS(7,6), /* prediv */ 305 __BIT(3), /* prediv_sel */ 306 __BITS(5,4), /* div */ 307 __BITS(13,12), /* sel */ 308 SUNXI_CCU_PREDIV_POWER_OF_TWO), 309 310 SUNXI_CCU_PREDIV(H3_CLK_AHB2, "ahb2", ahb2_parents, 311 AHB2_CFG_REG, /* reg */ 312 0, /* prediv */ 313 __BIT(1), /* prediv_sel */ 314 0, /* div */ 315 __BITS(1,0), /* sel */ 316 SUNXI_CCU_PREDIV_DIVIDE_BY_TWO), 317 318 SUNXI_CCU_DIV(H3_CLK_APB1, "apb1", apb1_parents, 319 AHB1_APB1_CFG_REG, /* reg */ 320 __BITS(9,8), /* div */ 321 0, /* sel */ 322 SUNXI_CCU_DIV_POWER_OF_TWO|SUNXI_CCU_DIV_ZERO_IS_ONE), 323 324 SUNXI_CCU_NM(H3_CLK_APB2, "apb2", apb2_parents, 325 APB2_CFG_REG, /* reg */ 326 __BITS(17,16), /* n */ 327 __BITS(4,0), /* m */ 328 __BITS(25,24), /* sel */ 329 0, /* enable */ 330 SUNXI_CCU_NM_POWER_OF_TWO), 331 332 SUNXI_CCU_DIV_GATE(H3_CLK_THS, "ths", ths_parents, 333 THS_CLK_REG, /* reg */ 334 __BITS(1,0), /* div */ 335 __BITS(25,24), /* sel */ 336 __BIT(31), /* enable */ 337 SUNXI_CCU_DIV_TIMES_TWO), 338 339 SUNXI_CCU_DIV_GATE(H3_CLK_DE, "de", de_parents, 340 DE_CLK_REG, /* reg */ 341 __BITS(3,0), /* div */ 342 __BITS(26,24), /* sel */ 343 __BIT(31), /* enable */ 344 0), 345 346 SUNXI_CCU_NM(H3_CLK_MMC0, "mmc0", mod_parents, 347 SDMMC0_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31), 348 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 349 SUNXI_CCU_PHASE(H3_CLK_MMC0_SAMPLE, "mmc0_sample", "mmc0", 350 SDMMC0_CLK_REG, __BITS(22,20)), 351 SUNXI_CCU_PHASE(H3_CLK_MMC0_OUTPUT, "mmc0_output", "mmc0", 352 SDMMC0_CLK_REG, __BITS(10,8)), 353 SUNXI_CCU_NM(H3_CLK_MMC1, "mmc1", mod_parents, 354 SDMMC1_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31), 355 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 356 SUNXI_CCU_PHASE(H3_CLK_MMC1_SAMPLE, "mmc1_sample", "mmc1", 357 SDMMC1_CLK_REG, __BITS(22,20)), 358 SUNXI_CCU_PHASE(H3_CLK_MMC1_OUTPUT, "mmc1_output", "mmc1", 359 SDMMC1_CLK_REG, __BITS(10,8)), 360 SUNXI_CCU_NM(H3_CLK_MMC2, "mmc2", mod_parents, 361 SDMMC2_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31), 362 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 363 SUNXI_CCU_PHASE(H3_CLK_MMC2_SAMPLE, "mmc2_sample", "mmc2", 364 SDMMC2_CLK_REG, __BITS(22,20)), 365 SUNXI_CCU_PHASE(H3_CLK_MMC2_OUTPUT, "mmc2_output", "mmc2", 366 SDMMC2_CLK_REG, __BITS(10,8)), 367 368 SUNXI_CCU_NM(H3_CLK_SPI0, "spi0", mod_parents, 369 SPI0_CLK_REG, /* reg */ 370 __BITS(17,16), /* n */ 371 __BITS(3,0), /* m */ 372 __BITS(25,24), /* sel */ 373 __BIT(31), /* enable */ 374 SUNXI_CCU_NM_ROUND_DOWN), 375 SUNXI_CCU_NM(H3_CLK_SPI1, "spi1", mod_parents, 376 SPI1_CLK_REG, /* reg */ 377 __BITS(17,16), /* n */ 378 __BITS(3,0), /* m */ 379 __BITS(25,24), /* sel */ 380 __BIT(31), /* enable */ 381 SUNXI_CCU_NM_ROUND_DOWN), 382 383 SUNXI_CCU_GATE(H3_CLK_AC_DIG, "ac_dig", "pll_audio", 384 AC_DIG_CLK_REG, 31), 385 386 SUNXI_CCU_DIV_GATE(H3_CLK_HDMI, "hdmi", hdmi_parents, 387 HDMI_CLK_REG, /* reg */ 388 __BITS(3,0), /* div */ 389 __BITS(25,24), /* sel */ 390 __BIT(31), /* enable */ 391 0), 392 393 SUNXI_CCU_GATE(H3_CLK_HDMI_DDC, "hdmi-ddc", "hosc", 394 HDMI_SLOW_CLK_REG, 31), 395 396 SUNXI_CCU_DIV_GATE(H3_CLK_TCON0, "tcon0", tcon0_parents, 397 TCON0_CLK_REG, /* reg */ 398 __BITS(3,0), /* div */ 399 __BITS(26,24), /* sel */ 400 __BIT(31), /* enable */ 401 0), 402 403 SUNXI_CCU_GATE(H3_CLK_BUS_DMA, "bus-dma", "ahb1", 404 BUS_CLK_GATING_REG0, 6), 405 SUNXI_CCU_GATE(H3_CLK_BUS_MMC0, "bus-mmc0", "ahb1", 406 BUS_CLK_GATING_REG0, 8), 407 SUNXI_CCU_GATE(H3_CLK_BUS_MMC1, "bus-mmc1", "ahb1", 408 BUS_CLK_GATING_REG0, 9), 409 SUNXI_CCU_GATE(H3_CLK_BUS_MMC2, "bus-mmc2", "ahb1", 410 BUS_CLK_GATING_REG0, 10), 411 SUNXI_CCU_GATE(H3_CLK_BUS_EMAC, "bus-emac", "ahb2", 412 BUS_CLK_GATING_REG0, 17), 413 SUNXI_CCU_GATE(H3_CLK_BUS_SPI0, "bus-spi0", "ahb1", 414 BUS_CLK_GATING_REG0, 20), 415 SUNXI_CCU_GATE(H3_CLK_BUS_SPI1, "bus-spi1", "ahb1", 416 BUS_CLK_GATING_REG0, 21), 417 SUNXI_CCU_GATE(H3_CLK_BUS_OTG, "bus-otg", "ahb1", 418 BUS_CLK_GATING_REG0, 23), 419 SUNXI_CCU_GATE(H3_CLK_BUS_EHCI0, "bus-ehci0", "ahb1", 420 BUS_CLK_GATING_REG0, 24), 421 SUNXI_CCU_GATE(H3_CLK_BUS_EHCI1, "bus-ehci1", "ahb2", 422 BUS_CLK_GATING_REG0, 25), 423 SUNXI_CCU_GATE(H3_CLK_BUS_EHCI2, "bus-ehci2", "ahb2", 424 BUS_CLK_GATING_REG0, 26), 425 SUNXI_CCU_GATE(H3_CLK_BUS_EHCI3, "bus-ehci3", "ahb2", 426 BUS_CLK_GATING_REG0, 27), 427 SUNXI_CCU_GATE(H3_CLK_BUS_OHCI0, "bus-ohci0", "ahb1", 428 BUS_CLK_GATING_REG0, 28), 429 SUNXI_CCU_GATE(H3_CLK_BUS_OHCI1, "bus-ohci1", "ahb2", 430 BUS_CLK_GATING_REG0, 29), 431 SUNXI_CCU_GATE(H3_CLK_BUS_OHCI2, "bus-ohci2", "ahb2", 432 BUS_CLK_GATING_REG0, 30), 433 SUNXI_CCU_GATE(H3_CLK_BUS_OHCI3, "bus-ohci3", "ahb2", 434 BUS_CLK_GATING_REG0, 31), 435 436 SUNXI_CCU_GATE(H3_CLK_BUS_GPU, "bus-gpu", "ahb1", 437 BUS_CLK_GATING_REG1, 20), 438 SUNXI_CCU_GATE(H3_CLK_BUS_DE, "bus-de", "ahb1", 439 BUS_CLK_GATING_REG1, 12), 440 SUNXI_CCU_GATE(H3_CLK_BUS_HDMI, "bus-hdmi", "ahb1", 441 BUS_CLK_GATING_REG1, 11), 442 SUNXI_CCU_GATE(H3_CLK_BUS_TVE, "bus-tve", "ahb1", 443 BUS_CLK_GATING_REG1, 9), 444 SUNXI_CCU_GATE(H3_CLK_BUS_DEINTERLACE, "bus-deinterlace", "ahb1", 445 BUS_CLK_GATING_REG1, 5), 446 SUNXI_CCU_GATE(H3_CLK_BUS_TCON1, "bus-tcon1", "ahb1", 447 BUS_CLK_GATING_REG1, 4), 448 SUNXI_CCU_GATE(H3_CLK_BUS_TCON0, "bus-tcon0", "ahb1", 449 BUS_CLK_GATING_REG1, 3), 450 451 SUNXI_CCU_GATE(H3_CLK_BUS_CODEC, "bus-codec", "apb1", 452 BUS_CLK_GATING_REG2, 0), 453 SUNXI_CCU_GATE(H3_CLK_BUS_PIO, "bus-pio", "apb1", 454 BUS_CLK_GATING_REG2, 5), 455 SUNXI_CCU_GATE(H3_CLK_BUS_THS, "bus-ths", "apb2", 456 BUS_CLK_GATING_REG2, 8), 457 458 SUNXI_CCU_GATE(H3_CLK_BUS_I2C0, "bus-i2c0", "apb2", 459 BUS_CLK_GATING_REG3, 0), 460 SUNXI_CCU_GATE(H3_CLK_BUS_I2C1, "bus-i2c1", "apb2", 461 BUS_CLK_GATING_REG3, 1), 462 SUNXI_CCU_GATE(H3_CLK_BUS_I2C2, "bus-i2c2", "apb2", 463 BUS_CLK_GATING_REG3, 2), 464 SUNXI_CCU_GATE(H3_CLK_BUS_UART0, "bus-uart0", "apb2", 465 BUS_CLK_GATING_REG3, 16), 466 SUNXI_CCU_GATE(H3_CLK_BUS_UART1, "bus-uart1", "apb2", 467 BUS_CLK_GATING_REG3, 17), 468 SUNXI_CCU_GATE(H3_CLK_BUS_UART2, "bus-uart2", "apb2", 469 BUS_CLK_GATING_REG3, 18), 470 SUNXI_CCU_GATE(H3_CLK_BUS_UART3, "bus-uart3", "apb2", 471 BUS_CLK_GATING_REG3, 19), 472 473 SUNXI_CCU_GATE(H3_CLK_BUS_EPHY, "bus-ephy", "ahb1", 474 BUS_CLK_GATING_REG4, 0), 475 476 SUNXI_CCU_GATE(H3_CLK_USBPHY0, "usb-phy0", "hosc", 477 USBPHY_CFG_REG, 8), 478 SUNXI_CCU_GATE(H3_CLK_USBPHY1, "usb-phy1", "hosc", 479 USBPHY_CFG_REG, 9), 480 SUNXI_CCU_GATE(H3_CLK_USBPHY2, "usb-phy2", "hosc", 481 USBPHY_CFG_REG, 10), 482 SUNXI_CCU_GATE(H3_CLK_USBPHY3, "usb-phy3", "hosc", 483 USBPHY_CFG_REG, 11), 484 SUNXI_CCU_GATE(H3_CLK_USBOHCI0, "usb-ohci0", "hosc", 485 USBPHY_CFG_REG, 16), 486 SUNXI_CCU_GATE(H3_CLK_USBOHCI1, "usb-ohci1", "hosc", 487 USBPHY_CFG_REG, 17), 488 SUNXI_CCU_GATE(H3_CLK_USBOHCI2, "usb-ohci2", "hosc", 489 USBPHY_CFG_REG, 18), 490 SUNXI_CCU_GATE(H3_CLK_USBOHCI3, "usb-ohci3", "hosc", 491 USBPHY_CFG_REG, 19), 492 }; 493 494 static void 495 sun8i_h3_ccu_init(struct sunxi_ccu_softc *sc) 496 { 497 uint32_t val; 498 499 /* Set AHB2 source to PLL_PERIPH/2 */ 500 val = CCU_READ(sc, AHB2_CFG_REG); 501 val &= ~AHB2_CLK_CFG; 502 val |= __SHIFTIN(AHB2_CLK_CFG_PLL_PERIPH0_2, AHB2_CLK_CFG); 503 CCU_WRITE(sc, AHB2_CFG_REG, val); 504 } 505 506 static int 507 sun8i_h3_ccu_match(device_t parent, cfdata_t cf, void *aux) 508 { 509 struct fdt_attach_args * const faa = aux; 510 511 return of_match_compatible(faa->faa_phandle, compatible); 512 } 513 514 static void 515 sun8i_h3_ccu_attach(device_t parent, device_t self, void *aux) 516 { 517 struct sunxi_ccu_softc * const sc = device_private(self); 518 struct fdt_attach_args * const faa = aux; 519 520 sc->sc_dev = self; 521 sc->sc_phandle = faa->faa_phandle; 522 sc->sc_bst = faa->faa_bst; 523 524 sc->sc_resets = sun8i_h3_ccu_resets; 525 sc->sc_nresets = __arraycount(sun8i_h3_ccu_resets); 526 527 sc->sc_clks = sun8i_h3_ccu_clks; 528 sc->sc_nclks = __arraycount(sun8i_h3_ccu_clks); 529 530 if (sunxi_ccu_attach(sc) != 0) 531 return; 532 533 aprint_naive("\n"); 534 aprint_normal(": H3 CCU\n"); 535 536 sun8i_h3_ccu_init(sc); 537 538 sunxi_ccu_print(sc); 539 } 540
Indexes created Thu Oct 02 10:09:58 GMT 2025