sun8i_h3_ccu.c revision 1.6
1 /* $NetBSD: sun8i_h3_ccu.c,v 1.6 2017/07/02 13:36:46 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * Copyright (c) 2017 Emmanuel Vadot <manu (at) freebsd.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 32 __KERNEL_RCSID(1, "$NetBSD: sun8i_h3_ccu.c,v 1.6 2017/07/02 13:36:46 jmcneill Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/systm.h> 38 39 #include <dev/fdt/fdtvar.h> 40 41 #include <arm/sunxi/sunxi_ccu.h> 42 #include <arm/sunxi/sun8i_h3_ccu.h> 43 44 #define PLL_PERIPH0_CTRL_REG 0x028 45 #define AHB1_APB1_CFG_REG 0x054 46 #define APB2_CFG_REG 0x058 47 #define BUS_CLK_GATING_REG0 0x060 48 #define BUS_CLK_GATING_REG2 0x068 49 #define BUS_CLK_GATING_REG3 0x06c 50 #define SDMMC0_CLK_REG 0x088 51 #define SDMMC1_CLK_REG 0x08c 52 #define SDMMC2_CLK_REG 0x090 53 #define USBPHY_CFG_REG 0x0cc 54 #define MBUS_RST_REG 0x0fc 55 #define BUS_SOFT_RST_REG0 0x2c0 56 #define BUS_SOFT_RST_REG1 0x2c4 57 #define BUS_SOFT_RST_REG2 0x2c8 58 #define BUS_SOFT_RST_REG3 0x2d0 59 #define BUS_SOFT_RST_REG4 0x2d8 60 61 static int sun8i_h3_ccu_match(device_t, cfdata_t, void *); 62 static void sun8i_h3_ccu_attach(device_t, device_t, void *); 63 64 static const char * const compatible[] = { 65 "allwinner,sun8i-h3-ccu", 66 NULL 67 }; 68 69 CFATTACH_DECL_NEW(sunxi_h3_ccu, sizeof(struct sunxi_ccu_softc), 70 sun8i_h3_ccu_match, sun8i_h3_ccu_attach, NULL, NULL); 71 72 static struct sunxi_ccu_reset sun8i_h3_ccu_resets[] = { 73 SUNXI_CCU_RESET(H3_RST_USB_PHY0, USBPHY_CFG_REG, 0), 74 SUNXI_CCU_RESET(H3_RST_USB_PHY1, USBPHY_CFG_REG, 1), 75 SUNXI_CCU_RESET(H3_RST_USB_PHY2, USBPHY_CFG_REG, 2), 76 SUNXI_CCU_RESET(H3_RST_USB_PHY3, USBPHY_CFG_REG, 3), 77 78 SUNXI_CCU_RESET(H3_RST_MBUS, MBUS_RST_REG, 31), 79 80 SUNXI_CCU_RESET(H3_RST_BUS_CE, BUS_SOFT_RST_REG0, 5), 81 SUNXI_CCU_RESET(H3_RST_BUS_DMA, BUS_SOFT_RST_REG0, 6), 82 SUNXI_CCU_RESET(H3_RST_BUS_MMC0, BUS_SOFT_RST_REG0, 8), 83 SUNXI_CCU_RESET(H3_RST_BUS_MMC1, BUS_SOFT_RST_REG0, 9), 84 SUNXI_CCU_RESET(H3_RST_BUS_MMC2, BUS_SOFT_RST_REG0, 10), 85 SUNXI_CCU_RESET(H3_RST_BUS_NAND, BUS_SOFT_RST_REG0, 13), 86 SUNXI_CCU_RESET(H3_RST_BUS_DRAM, BUS_SOFT_RST_REG0, 14), 87 SUNXI_CCU_RESET(H3_RST_BUS_EMAC, BUS_SOFT_RST_REG0, 17), 88 SUNXI_CCU_RESET(H3_RST_BUS_TS, BUS_SOFT_RST_REG0, 18), 89 SUNXI_CCU_RESET(H3_RST_BUS_HSTIMER, BUS_SOFT_RST_REG0, 19), 90 SUNXI_CCU_RESET(H3_RST_BUS_SPI0, BUS_SOFT_RST_REG0, 20), 91 SUNXI_CCU_RESET(H3_RST_BUS_SPI1, BUS_SOFT_RST_REG0, 21), 92 SUNXI_CCU_RESET(H3_RST_BUS_OTG, BUS_SOFT_RST_REG0, 23), 93 SUNXI_CCU_RESET(H3_RST_BUS_EHCI0, BUS_SOFT_RST_REG0, 24), 94 SUNXI_CCU_RESET(H3_RST_BUS_EHCI1, BUS_SOFT_RST_REG0, 25), 95 SUNXI_CCU_RESET(H3_RST_BUS_EHCI2, BUS_SOFT_RST_REG0, 26), 96 SUNXI_CCU_RESET(H3_RST_BUS_EHCI3, BUS_SOFT_RST_REG0, 27), 97 SUNXI_CCU_RESET(H3_RST_BUS_OHCI0, BUS_SOFT_RST_REG0, 28), 98 SUNXI_CCU_RESET(H3_RST_BUS_OHCI1, BUS_SOFT_RST_REG0, 29), 99 SUNXI_CCU_RESET(H3_RST_BUS_OHCI2, BUS_SOFT_RST_REG0, 30), 100 SUNXI_CCU_RESET(H3_RST_BUS_OHCI3, BUS_SOFT_RST_REG0, 31), 101 102 SUNXI_CCU_RESET(H3_RST_BUS_VE, BUS_SOFT_RST_REG1, 0), 103 SUNXI_CCU_RESET(H3_RST_BUS_TCON0, BUS_SOFT_RST_REG1, 3), 104 SUNXI_CCU_RESET(H3_RST_BUS_TCON1, BUS_SOFT_RST_REG1, 4), 105 SUNXI_CCU_RESET(H3_RST_BUS_DEINTERLACE, BUS_SOFT_RST_REG1, 5), 106 SUNXI_CCU_RESET(H3_RST_BUS_CSI, BUS_SOFT_RST_REG1, 8), 107 SUNXI_CCU_RESET(H3_RST_BUS_TVE, BUS_SOFT_RST_REG1, 9), 108 SUNXI_CCU_RESET(H3_RST_BUS_HDMI0, BUS_SOFT_RST_REG1, 10), 109 SUNXI_CCU_RESET(H3_RST_BUS_HDMI1, BUS_SOFT_RST_REG1, 11), 110 SUNXI_CCU_RESET(H3_RST_BUS_DE, BUS_SOFT_RST_REG1, 12), 111 SUNXI_CCU_RESET(H3_RST_BUS_GPU, BUS_SOFT_RST_REG1, 20), 112 SUNXI_CCU_RESET(H3_RST_BUS_MSGBOX, BUS_SOFT_RST_REG1, 21), 113 SUNXI_CCU_RESET(H3_RST_BUS_SPINLOCK, BUS_SOFT_RST_REG1, 22), 114 SUNXI_CCU_RESET(H3_RST_BUS_DBG, BUS_SOFT_RST_REG1, 31), 115 116 SUNXI_CCU_RESET(H3_RST_BUS_EPHY, BUS_SOFT_RST_REG2, 2), 117 118 SUNXI_CCU_RESET(H3_RST_BUS_CODEC, BUS_SOFT_RST_REG3, 0), 119 SUNXI_CCU_RESET(H3_RST_BUS_SPDIF, BUS_SOFT_RST_REG3, 1), 120 SUNXI_CCU_RESET(H3_RST_BUS_THS, BUS_SOFT_RST_REG3, 8), 121 SUNXI_CCU_RESET(H3_RST_BUS_I2S0, BUS_SOFT_RST_REG3, 12), 122 SUNXI_CCU_RESET(H3_RST_BUS_I2S1, BUS_SOFT_RST_REG3, 13), 123 SUNXI_CCU_RESET(H3_RST_BUS_I2S2, BUS_SOFT_RST_REG3, 14), 124 125 SUNXI_CCU_RESET(H3_RST_BUS_I2C0, BUS_SOFT_RST_REG4, 0), 126 SUNXI_CCU_RESET(H3_RST_BUS_I2C1, BUS_SOFT_RST_REG4, 1), 127 SUNXI_CCU_RESET(H3_RST_BUS_I2C2, BUS_SOFT_RST_REG4, 2), 128 SUNXI_CCU_RESET(H3_RST_BUS_UART0, BUS_SOFT_RST_REG4, 16), 129 SUNXI_CCU_RESET(H3_RST_BUS_UART1, BUS_SOFT_RST_REG4, 17), 130 SUNXI_CCU_RESET(H3_RST_BUS_UART2, BUS_SOFT_RST_REG4, 18), 131 SUNXI_CCU_RESET(H3_RST_BUS_UART3, BUS_SOFT_RST_REG4, 19), 132 SUNXI_CCU_RESET(H3_RST_BUS_SCR, BUS_SOFT_RST_REG4, 20), 133 }; 134 135 static const char *ahb1_parents[] = { "losc", "hosc", "axi", "pll_periph0" }; 136 static const char *ahb2_parents[] = { "ahb1", "pll_periph0" }; 137 static const char *apb1_parents[] = { "ahb1" }; 138 static const char *apb2_parents[] = { "losc", "hosc", "pll_periph0" }; 139 static const char *mod_parents[] = { "hosc", "pll_periph0", "pll_periph1" }; 140 141 static struct sunxi_ccu_clk sun8i_h3_ccu_clks[] = { 142 SUNXI_CCU_NKMP(H3_CLK_PLL_PERIPH0, "pll_periph0", "hosc", 143 PLL_PERIPH0_CTRL_REG, /* reg */ 144 __BITS(12,8), /* n */ 145 __BITS(5,4), /* k */ 146 0, /* m */ 147 __BITS(17,16), /* p */ 148 __BIT(31), /* enable */ 149 SUNXI_CCU_NKMP_DIVIDE_BY_TWO), 150 151 SUNXI_CCU_PREDIV(H3_CLK_AHB1, "ahb1", ahb1_parents, 152 AHB1_APB1_CFG_REG, /* reg */ 153 __BITS(7,6), /* prediv */ 154 __BIT(3), /* prediv_sel */ 155 __BITS(5,4), /* div */ 156 __BITS(13,12), /* sel */ 157 SUNXI_CCU_PREDIV_POWER_OF_TWO), 158 159 SUNXI_CCU_PREDIV(H3_CLK_AHB2, "ahb2", ahb2_parents, 160 APB2_CFG_REG, /* reg */ 161 0, /* prediv */ 162 __BIT(1), /* prediv_sel */ 163 0, /* div */ 164 __BITS(1,0), /* sel */ 165 SUNXI_CCU_PREDIV_DIVIDE_BY_TWO), 166 167 SUNXI_CCU_DIV(H3_CLK_APB1, "apb1", apb1_parents, 168 AHB1_APB1_CFG_REG, /* reg */ 169 __BITS(9,8), /* div */ 170 0, /* sel */ 171 SUNXI_CCU_DIV_POWER_OF_TWO|SUNXI_CCU_DIV_ZERO_IS_ONE), 172 173 SUNXI_CCU_NM(H3_CLK_APB2, "apb2", apb2_parents, 174 APB2_CFG_REG, /* reg */ 175 __BITS(17,16), /* n */ 176 __BITS(4,0), /* m */ 177 __BITS(25,24), /* sel */ 178 0, /* enable */ 179 SUNXI_CCU_NM_POWER_OF_TWO), 180 181 SUNXI_CCU_NM(H3_CLK_MMC0, "mmc0", mod_parents, 182 SDMMC0_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31), 183 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 184 SUNXI_CCU_NM(H3_CLK_MMC1, "mmc1", mod_parents, 185 SDMMC1_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31), 186 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 187 SUNXI_CCU_NM(H3_CLK_MMC2, "mmc2", mod_parents, 188 SDMMC2_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31), 189 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 190 191 SUNXI_CCU_GATE(H3_CLK_BUS_MMC0, "bus-mmc0", "ahb1", 192 BUS_CLK_GATING_REG0, 8), 193 SUNXI_CCU_GATE(H3_CLK_BUS_MMC1, "bus-mmc1", "ahb1", 194 BUS_CLK_GATING_REG0, 9), 195 SUNXI_CCU_GATE(H3_CLK_BUS_MMC2, "bus-mmc2", "ahb1", 196 BUS_CLK_GATING_REG0, 10), 197 SUNXI_CCU_GATE(H3_CLK_BUS_EMAC, "bus-emac", "ahb2", 198 BUS_CLK_GATING_REG0, 17), 199 SUNXI_CCU_GATE(H3_CLK_BUS_OTG, "bus-otg", "ahb1", 200 BUS_CLK_GATING_REG0, 23), 201 SUNXI_CCU_GATE(H3_CLK_BUS_EHCI0, "bus-ehci0", "ahb1", 202 BUS_CLK_GATING_REG0, 24), 203 SUNXI_CCU_GATE(H3_CLK_BUS_EHCI1, "bus-ehci1", "ahb2", 204 BUS_CLK_GATING_REG0, 25), 205 SUNXI_CCU_GATE(H3_CLK_BUS_EHCI2, "bus-ehci2", "ahb2", 206 BUS_CLK_GATING_REG0, 26), 207 SUNXI_CCU_GATE(H3_CLK_BUS_EHCI3, "bus-ehci3", "ahb2", 208 BUS_CLK_GATING_REG0, 27), 209 SUNXI_CCU_GATE(H3_CLK_BUS_OHCI0, "bus-ohci0", "ahb1", 210 BUS_CLK_GATING_REG0, 28), 211 SUNXI_CCU_GATE(H3_CLK_BUS_OHCI1, "bus-ohci1", "ahb2", 212 BUS_CLK_GATING_REG0, 29), 213 SUNXI_CCU_GATE(H3_CLK_BUS_OHCI2, "bus-ohci2", "ahb2", 214 BUS_CLK_GATING_REG0, 30), 215 SUNXI_CCU_GATE(H3_CLK_BUS_OHCI3, "bus-ohci3", "ahb2", 216 BUS_CLK_GATING_REG0, 31), 217 218 SUNXI_CCU_GATE(H3_CLK_BUS_PIO, "bus-pio", "apb1", 219 BUS_CLK_GATING_REG2, 5), 220 221 SUNXI_CCU_GATE(H3_CLK_BUS_I2C0, "bus-i2c0", "apb2", 222 BUS_CLK_GATING_REG3, 0), 223 SUNXI_CCU_GATE(H3_CLK_BUS_I2C1, "bus-i2c1", "apb2", 224 BUS_CLK_GATING_REG3, 1), 225 SUNXI_CCU_GATE(H3_CLK_BUS_I2C2, "bus-i2c2", "apb2", 226 BUS_CLK_GATING_REG3, 2), 227 SUNXI_CCU_GATE(H3_CLK_BUS_UART0, "bus-uart0", "apb2", 228 BUS_CLK_GATING_REG3, 16), 229 SUNXI_CCU_GATE(H3_CLK_BUS_UART1, "bus-uart1", "apb2", 230 BUS_CLK_GATING_REG3, 17), 231 SUNXI_CCU_GATE(H3_CLK_BUS_UART2, "bus-uart2", "apb2", 232 BUS_CLK_GATING_REG3, 18), 233 SUNXI_CCU_GATE(H3_CLK_BUS_UART3, "bus-uart3", "apb2", 234 BUS_CLK_GATING_REG3, 19), 235 236 SUNXI_CCU_GATE(H3_CLK_USBPHY0, "usb-phy0", "hosc", 237 USBPHY_CFG_REG, 8), 238 SUNXI_CCU_GATE(H3_CLK_USBPHY1, "usb-phy1", "hosc", 239 USBPHY_CFG_REG, 9), 240 SUNXI_CCU_GATE(H3_CLK_USBPHY2, "usb-phy2", "hosc", 241 USBPHY_CFG_REG, 10), 242 SUNXI_CCU_GATE(H3_CLK_USBPHY3, "usb-phy3", "hosc", 243 USBPHY_CFG_REG, 11), 244 SUNXI_CCU_GATE(H3_CLK_USBOHCI0, "usb-ohci0", "hosc", 245 USBPHY_CFG_REG, 16), 246 SUNXI_CCU_GATE(H3_CLK_USBOHCI1, "usb-ohci1", "hosc", 247 USBPHY_CFG_REG, 17), 248 SUNXI_CCU_GATE(H3_CLK_USBOHCI2, "usb-ohci2", "hosc", 249 USBPHY_CFG_REG, 18), 250 SUNXI_CCU_GATE(H3_CLK_USBOHCI3, "usb-ohci3", "hosc", 251 USBPHY_CFG_REG, 19), 252 }; 253 254 static int 255 sun8i_h3_ccu_match(device_t parent, cfdata_t cf, void *aux) 256 { 257 struct fdt_attach_args * const faa = aux; 258 259 return of_match_compatible(faa->faa_phandle, compatible); 260 } 261 262 static void 263 sun8i_h3_ccu_attach(device_t parent, device_t self, void *aux) 264 { 265 struct sunxi_ccu_softc * const sc = device_private(self); 266 struct fdt_attach_args * const faa = aux; 267 268 sc->sc_dev = self; 269 sc->sc_phandle = faa->faa_phandle; 270 sc->sc_bst = faa->faa_bst; 271 272 sc->sc_resets = sun8i_h3_ccu_resets; 273 sc->sc_nresets = __arraycount(sun8i_h3_ccu_resets); 274 275 sc->sc_clks = sun8i_h3_ccu_clks; 276 sc->sc_nclks = __arraycount(sun8i_h3_ccu_clks); 277 278 if (sunxi_ccu_attach(sc) != 0) 279 return; 280 281 aprint_naive("\n"); 282 aprint_normal(": H3 CCU\n"); 283 284 sunxi_ccu_print(sc); 285 } 286
Indexes created Thu Oct 02 10:09:58 GMT 2025