sun8i_h3_ccu.c revision 1.7
1 /* $NetBSD: sun8i_h3_ccu.c,v 1.7 2017/07/07 21:19:50 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * Copyright (c) 2017 Emmanuel Vadot <manu (at) freebsd.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 32 __KERNEL_RCSID(1, "$NetBSD: sun8i_h3_ccu.c,v 1.7 2017/07/07 21:19:50 jmcneill Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/systm.h> 38 39 #include <dev/fdt/fdtvar.h> 40 41 #include <arm/sunxi/sunxi_ccu.h> 42 #include <arm/sunxi/sun8i_h3_ccu.h> 43 44 #define PLL_PERIPH0_CTRL_REG 0x028 45 #define AHB1_APB1_CFG_REG 0x054 46 #define APB2_CFG_REG 0x058 47 #define AHB2_CFG_REG 0x05c 48 #define AHB2_CLK_CFG __BITS(1,0) 49 #define AHB2_CLK_CFG_PLL_PERIPH0_2 1 50 #define BUS_CLK_GATING_REG0 0x060 51 #define BUS_CLK_GATING_REG2 0x068 52 #define BUS_CLK_GATING_REG3 0x06c 53 #define SDMMC0_CLK_REG 0x088 54 #define SDMMC1_CLK_REG 0x08c 55 #define SDMMC2_CLK_REG 0x090 56 #define USBPHY_CFG_REG 0x0cc 57 #define MBUS_RST_REG 0x0fc 58 #define BUS_SOFT_RST_REG0 0x2c0 59 #define BUS_SOFT_RST_REG1 0x2c4 60 #define BUS_SOFT_RST_REG2 0x2c8 61 #define BUS_SOFT_RST_REG3 0x2d0 62 #define BUS_SOFT_RST_REG4 0x2d8 63 64 static int sun8i_h3_ccu_match(device_t, cfdata_t, void *); 65 static void sun8i_h3_ccu_attach(device_t, device_t, void *); 66 67 static const char * const compatible[] = { 68 "allwinner,sun8i-h3-ccu", 69 NULL 70 }; 71 72 CFATTACH_DECL_NEW(sunxi_h3_ccu, sizeof(struct sunxi_ccu_softc), 73 sun8i_h3_ccu_match, sun8i_h3_ccu_attach, NULL, NULL); 74 75 static struct sunxi_ccu_reset sun8i_h3_ccu_resets[] = { 76 SUNXI_CCU_RESET(H3_RST_USB_PHY0, USBPHY_CFG_REG, 0), 77 SUNXI_CCU_RESET(H3_RST_USB_PHY1, USBPHY_CFG_REG, 1), 78 SUNXI_CCU_RESET(H3_RST_USB_PHY2, USBPHY_CFG_REG, 2), 79 SUNXI_CCU_RESET(H3_RST_USB_PHY3, USBPHY_CFG_REG, 3), 80 81 SUNXI_CCU_RESET(H3_RST_MBUS, MBUS_RST_REG, 31), 82 83 SUNXI_CCU_RESET(H3_RST_BUS_CE, BUS_SOFT_RST_REG0, 5), 84 SUNXI_CCU_RESET(H3_RST_BUS_DMA, BUS_SOFT_RST_REG0, 6), 85 SUNXI_CCU_RESET(H3_RST_BUS_MMC0, BUS_SOFT_RST_REG0, 8), 86 SUNXI_CCU_RESET(H3_RST_BUS_MMC1, BUS_SOFT_RST_REG0, 9), 87 SUNXI_CCU_RESET(H3_RST_BUS_MMC2, BUS_SOFT_RST_REG0, 10), 88 SUNXI_CCU_RESET(H3_RST_BUS_NAND, BUS_SOFT_RST_REG0, 13), 89 SUNXI_CCU_RESET(H3_RST_BUS_DRAM, BUS_SOFT_RST_REG0, 14), 90 SUNXI_CCU_RESET(H3_RST_BUS_EMAC, BUS_SOFT_RST_REG0, 17), 91 SUNXI_CCU_RESET(H3_RST_BUS_TS, BUS_SOFT_RST_REG0, 18), 92 SUNXI_CCU_RESET(H3_RST_BUS_HSTIMER, BUS_SOFT_RST_REG0, 19), 93 SUNXI_CCU_RESET(H3_RST_BUS_SPI0, BUS_SOFT_RST_REG0, 20), 94 SUNXI_CCU_RESET(H3_RST_BUS_SPI1, BUS_SOFT_RST_REG0, 21), 95 SUNXI_CCU_RESET(H3_RST_BUS_OTG, BUS_SOFT_RST_REG0, 23), 96 SUNXI_CCU_RESET(H3_RST_BUS_EHCI0, BUS_SOFT_RST_REG0, 24), 97 SUNXI_CCU_RESET(H3_RST_BUS_EHCI1, BUS_SOFT_RST_REG0, 25), 98 SUNXI_CCU_RESET(H3_RST_BUS_EHCI2, BUS_SOFT_RST_REG0, 26), 99 SUNXI_CCU_RESET(H3_RST_BUS_EHCI3, BUS_SOFT_RST_REG0, 27), 100 SUNXI_CCU_RESET(H3_RST_BUS_OHCI0, BUS_SOFT_RST_REG0, 28), 101 SUNXI_CCU_RESET(H3_RST_BUS_OHCI1, BUS_SOFT_RST_REG0, 29), 102 SUNXI_CCU_RESET(H3_RST_BUS_OHCI2, BUS_SOFT_RST_REG0, 30), 103 SUNXI_CCU_RESET(H3_RST_BUS_OHCI3, BUS_SOFT_RST_REG0, 31), 104 105 SUNXI_CCU_RESET(H3_RST_BUS_VE, BUS_SOFT_RST_REG1, 0), 106 SUNXI_CCU_RESET(H3_RST_BUS_TCON0, BUS_SOFT_RST_REG1, 3), 107 SUNXI_CCU_RESET(H3_RST_BUS_TCON1, BUS_SOFT_RST_REG1, 4), 108 SUNXI_CCU_RESET(H3_RST_BUS_DEINTERLACE, BUS_SOFT_RST_REG1, 5), 109 SUNXI_CCU_RESET(H3_RST_BUS_CSI, BUS_SOFT_RST_REG1, 8), 110 SUNXI_CCU_RESET(H3_RST_BUS_TVE, BUS_SOFT_RST_REG1, 9), 111 SUNXI_CCU_RESET(H3_RST_BUS_HDMI0, BUS_SOFT_RST_REG1, 10), 112 SUNXI_CCU_RESET(H3_RST_BUS_HDMI1, BUS_SOFT_RST_REG1, 11), 113 SUNXI_CCU_RESET(H3_RST_BUS_DE, BUS_SOFT_RST_REG1, 12), 114 SUNXI_CCU_RESET(H3_RST_BUS_GPU, BUS_SOFT_RST_REG1, 20), 115 SUNXI_CCU_RESET(H3_RST_BUS_MSGBOX, BUS_SOFT_RST_REG1, 21), 116 SUNXI_CCU_RESET(H3_RST_BUS_SPINLOCK, BUS_SOFT_RST_REG1, 22), 117 SUNXI_CCU_RESET(H3_RST_BUS_DBG, BUS_SOFT_RST_REG1, 31), 118 119 SUNXI_CCU_RESET(H3_RST_BUS_EPHY, BUS_SOFT_RST_REG2, 2), 120 121 SUNXI_CCU_RESET(H3_RST_BUS_CODEC, BUS_SOFT_RST_REG3, 0), 122 SUNXI_CCU_RESET(H3_RST_BUS_SPDIF, BUS_SOFT_RST_REG3, 1), 123 SUNXI_CCU_RESET(H3_RST_BUS_THS, BUS_SOFT_RST_REG3, 8), 124 SUNXI_CCU_RESET(H3_RST_BUS_I2S0, BUS_SOFT_RST_REG3, 12), 125 SUNXI_CCU_RESET(H3_RST_BUS_I2S1, BUS_SOFT_RST_REG3, 13), 126 SUNXI_CCU_RESET(H3_RST_BUS_I2S2, BUS_SOFT_RST_REG3, 14), 127 128 SUNXI_CCU_RESET(H3_RST_BUS_I2C0, BUS_SOFT_RST_REG4, 0), 129 SUNXI_CCU_RESET(H3_RST_BUS_I2C1, BUS_SOFT_RST_REG4, 1), 130 SUNXI_CCU_RESET(H3_RST_BUS_I2C2, BUS_SOFT_RST_REG4, 2), 131 SUNXI_CCU_RESET(H3_RST_BUS_UART0, BUS_SOFT_RST_REG4, 16), 132 SUNXI_CCU_RESET(H3_RST_BUS_UART1, BUS_SOFT_RST_REG4, 17), 133 SUNXI_CCU_RESET(H3_RST_BUS_UART2, BUS_SOFT_RST_REG4, 18), 134 SUNXI_CCU_RESET(H3_RST_BUS_UART3, BUS_SOFT_RST_REG4, 19), 135 SUNXI_CCU_RESET(H3_RST_BUS_SCR, BUS_SOFT_RST_REG4, 20), 136 }; 137 138 static const char *ahb1_parents[] = { "losc", "hosc", "axi", "pll_periph0" }; 139 static const char *ahb2_parents[] = { "ahb1", "pll_periph0" }; 140 static const char *apb1_parents[] = { "ahb1" }; 141 static const char *apb2_parents[] = { "losc", "hosc", "pll_periph0" }; 142 static const char *mod_parents[] = { "hosc", "pll_periph0", "pll_periph1" }; 143 144 static struct sunxi_ccu_clk sun8i_h3_ccu_clks[] = { 145 SUNXI_CCU_NKMP(H3_CLK_PLL_PERIPH0, "pll_periph0", "hosc", 146 PLL_PERIPH0_CTRL_REG, /* reg */ 147 __BITS(12,8), /* n */ 148 __BITS(5,4), /* k */ 149 0, /* m */ 150 __BITS(17,16), /* p */ 151 __BIT(31), /* enable */ 152 SUNXI_CCU_NKMP_DIVIDE_BY_TWO), 153 154 SUNXI_CCU_PREDIV(H3_CLK_AHB1, "ahb1", ahb1_parents, 155 AHB1_APB1_CFG_REG, /* reg */ 156 __BITS(7,6), /* prediv */ 157 __BIT(3), /* prediv_sel */ 158 __BITS(5,4), /* div */ 159 __BITS(13,12), /* sel */ 160 SUNXI_CCU_PREDIV_POWER_OF_TWO), 161 162 SUNXI_CCU_PREDIV(H3_CLK_AHB2, "ahb2", ahb2_parents, 163 AHB2_CFG_REG, /* reg */ 164 0, /* prediv */ 165 __BIT(1), /* prediv_sel */ 166 0, /* div */ 167 __BITS(1,0), /* sel */ 168 SUNXI_CCU_PREDIV_DIVIDE_BY_TWO), 169 170 SUNXI_CCU_DIV(H3_CLK_APB1, "apb1", apb1_parents, 171 AHB1_APB1_CFG_REG, /* reg */ 172 __BITS(9,8), /* div */ 173 0, /* sel */ 174 SUNXI_CCU_DIV_POWER_OF_TWO|SUNXI_CCU_DIV_ZERO_IS_ONE), 175 176 SUNXI_CCU_NM(H3_CLK_APB2, "apb2", apb2_parents, 177 APB2_CFG_REG, /* reg */ 178 __BITS(17,16), /* n */ 179 __BITS(4,0), /* m */ 180 __BITS(25,24), /* sel */ 181 0, /* enable */ 182 SUNXI_CCU_NM_POWER_OF_TWO), 183 184 SUNXI_CCU_NM(H3_CLK_MMC0, "mmc0", mod_parents, 185 SDMMC0_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31), 186 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 187 SUNXI_CCU_NM(H3_CLK_MMC1, "mmc1", mod_parents, 188 SDMMC1_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31), 189 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 190 SUNXI_CCU_NM(H3_CLK_MMC2, "mmc2", mod_parents, 191 SDMMC2_CLK_REG, __BITS(17, 16), __BITS(3,0), __BITS(25, 24), __BIT(31), 192 SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN), 193 194 SUNXI_CCU_GATE(H3_CLK_BUS_MMC0, "bus-mmc0", "ahb1", 195 BUS_CLK_GATING_REG0, 8), 196 SUNXI_CCU_GATE(H3_CLK_BUS_MMC1, "bus-mmc1", "ahb1", 197 BUS_CLK_GATING_REG0, 9), 198 SUNXI_CCU_GATE(H3_CLK_BUS_MMC2, "bus-mmc2", "ahb1", 199 BUS_CLK_GATING_REG0, 10), 200 SUNXI_CCU_GATE(H3_CLK_BUS_EMAC, "bus-emac", "ahb2", 201 BUS_CLK_GATING_REG0, 17), 202 SUNXI_CCU_GATE(H3_CLK_BUS_OTG, "bus-otg", "ahb1", 203 BUS_CLK_GATING_REG0, 23), 204 SUNXI_CCU_GATE(H3_CLK_BUS_EHCI0, "bus-ehci0", "ahb1", 205 BUS_CLK_GATING_REG0, 24), 206 SUNXI_CCU_GATE(H3_CLK_BUS_EHCI1, "bus-ehci1", "ahb2", 207 BUS_CLK_GATING_REG0, 25), 208 SUNXI_CCU_GATE(H3_CLK_BUS_EHCI2, "bus-ehci2", "ahb2", 209 BUS_CLK_GATING_REG0, 26), 210 SUNXI_CCU_GATE(H3_CLK_BUS_EHCI3, "bus-ehci3", "ahb2", 211 BUS_CLK_GATING_REG0, 27), 212 SUNXI_CCU_GATE(H3_CLK_BUS_OHCI0, "bus-ohci0", "ahb1", 213 BUS_CLK_GATING_REG0, 28), 214 SUNXI_CCU_GATE(H3_CLK_BUS_OHCI1, "bus-ohci1", "ahb2", 215 BUS_CLK_GATING_REG0, 29), 216 SUNXI_CCU_GATE(H3_CLK_BUS_OHCI2, "bus-ohci2", "ahb2", 217 BUS_CLK_GATING_REG0, 30), 218 SUNXI_CCU_GATE(H3_CLK_BUS_OHCI3, "bus-ohci3", "ahb2", 219 BUS_CLK_GATING_REG0, 31), 220 221 SUNXI_CCU_GATE(H3_CLK_BUS_PIO, "bus-pio", "apb1", 222 BUS_CLK_GATING_REG2, 5), 223 224 SUNXI_CCU_GATE(H3_CLK_BUS_I2C0, "bus-i2c0", "apb2", 225 BUS_CLK_GATING_REG3, 0), 226 SUNXI_CCU_GATE(H3_CLK_BUS_I2C1, "bus-i2c1", "apb2", 227 BUS_CLK_GATING_REG3, 1), 228 SUNXI_CCU_GATE(H3_CLK_BUS_I2C2, "bus-i2c2", "apb2", 229 BUS_CLK_GATING_REG3, 2), 230 SUNXI_CCU_GATE(H3_CLK_BUS_UART0, "bus-uart0", "apb2", 231 BUS_CLK_GATING_REG3, 16), 232 SUNXI_CCU_GATE(H3_CLK_BUS_UART1, "bus-uart1", "apb2", 233 BUS_CLK_GATING_REG3, 17), 234 SUNXI_CCU_GATE(H3_CLK_BUS_UART2, "bus-uart2", "apb2", 235 BUS_CLK_GATING_REG3, 18), 236 SUNXI_CCU_GATE(H3_CLK_BUS_UART3, "bus-uart3", "apb2", 237 BUS_CLK_GATING_REG3, 19), 238 239 SUNXI_CCU_GATE(H3_CLK_USBPHY0, "usb-phy0", "hosc", 240 USBPHY_CFG_REG, 8), 241 SUNXI_CCU_GATE(H3_CLK_USBPHY1, "usb-phy1", "hosc", 242 USBPHY_CFG_REG, 9), 243 SUNXI_CCU_GATE(H3_CLK_USBPHY2, "usb-phy2", "hosc", 244 USBPHY_CFG_REG, 10), 245 SUNXI_CCU_GATE(H3_CLK_USBPHY3, "usb-phy3", "hosc", 246 USBPHY_CFG_REG, 11), 247 SUNXI_CCU_GATE(H3_CLK_USBOHCI0, "usb-ohci0", "hosc", 248 USBPHY_CFG_REG, 16), 249 SUNXI_CCU_GATE(H3_CLK_USBOHCI1, "usb-ohci1", "hosc", 250 USBPHY_CFG_REG, 17), 251 SUNXI_CCU_GATE(H3_CLK_USBOHCI2, "usb-ohci2", "hosc", 252 USBPHY_CFG_REG, 18), 253 SUNXI_CCU_GATE(H3_CLK_USBOHCI3, "usb-ohci3", "hosc", 254 USBPHY_CFG_REG, 19), 255 }; 256 257 static void 258 sun8i_h3_ccu_init(struct sunxi_ccu_softc *sc) 259 { 260 uint32_t val; 261 262 /* Set AHB2 source to PLL_PERIPH/2 */ 263 val = CCU_READ(sc, AHB2_CFG_REG); 264 val &= ~AHB2_CLK_CFG; 265 val |= __SHIFTIN(AHB2_CLK_CFG_PLL_PERIPH0_2, AHB2_CLK_CFG); 266 CCU_WRITE(sc, AHB2_CFG_REG, val); 267 } 268 269 static int 270 sun8i_h3_ccu_match(device_t parent, cfdata_t cf, void *aux) 271 { 272 struct fdt_attach_args * const faa = aux; 273 274 return of_match_compatible(faa->faa_phandle, compatible); 275 } 276 277 static void 278 sun8i_h3_ccu_attach(device_t parent, device_t self, void *aux) 279 { 280 struct sunxi_ccu_softc * const sc = device_private(self); 281 struct fdt_attach_args * const faa = aux; 282 283 sc->sc_dev = self; 284 sc->sc_phandle = faa->faa_phandle; 285 sc->sc_bst = faa->faa_bst; 286 287 sc->sc_resets = sun8i_h3_ccu_resets; 288 sc->sc_nresets = __arraycount(sun8i_h3_ccu_resets); 289 290 sc->sc_clks = sun8i_h3_ccu_clks; 291 sc->sc_nclks = __arraycount(sun8i_h3_ccu_clks); 292 293 if (sunxi_ccu_attach(sc) != 0) 294 return; 295 296 aprint_naive("\n"); 297 aprint_normal(": H3 CCU\n"); 298 299 sun8i_h3_ccu_init(sc); 300 301 sunxi_ccu_print(sc); 302 } 303
Indexes created Thu Oct 02 10:09:58 GMT 2025