1 1.1 jmcneill /* $NetBSD: sun8i_h3_ccu.h,v 1.1 2017/06/28 23:51:29 jmcneill Exp $ */ 2 1.1 jmcneill 3 1.1 jmcneill /*- 4 1.1 jmcneill * Copyright (c) 2017 Emmanuel Vadot <manu (at) freebsd.org> 5 1.1 jmcneill * All rights reserved. 6 1.1 jmcneill * 7 1.1 jmcneill * Redistribution and use in source and binary forms, with or without 8 1.1 jmcneill * modification, are permitted provided that the following conditions 9 1.1 jmcneill * are met: 10 1.1 jmcneill * 1. Redistributions of source code must retain the above copyright 11 1.1 jmcneill * notice, this list of conditions and the following disclaimer. 12 1.1 jmcneill * 2. Redistributions in binary form must reproduce the above copyright 13 1.1 jmcneill * notice, this list of conditions and the following disclaimer in the 14 1.1 jmcneill * documentation and/or other materials provided with the distribution. 15 1.1 jmcneill * 16 1.1 jmcneill * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 1.1 jmcneill * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 1.1 jmcneill * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 1.1 jmcneill * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 1.1 jmcneill * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 1.1 jmcneill * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 1.1 jmcneill * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 1.1 jmcneill * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 1.1 jmcneill * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 1.1 jmcneill * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 1.1 jmcneill * SUCH DAMAGE. 27 1.1 jmcneill * 28 1.1 jmcneill * $FreeBSD$ 29 1.1 jmcneill */ 30 1.1 jmcneill 31 1.1 jmcneill #ifndef __CCU_H3_H__ 32 1.1 jmcneill #define __CCU_H3_H__ 33 1.1 jmcneill 34 1.1 jmcneill #define H3_RST_USB_PHY0 0 35 1.1 jmcneill #define H3_RST_USB_PHY1 1 36 1.1 jmcneill #define H3_RST_USB_PHY2 2 37 1.1 jmcneill #define H3_RST_USB_PHY3 3 38 1.1 jmcneill #define H3_RST_MBUS 4 39 1.1 jmcneill #define H3_RST_BUS_CE 5 40 1.1 jmcneill #define H3_RST_BUS_DMA 6 41 1.1 jmcneill #define H3_RST_BUS_MMC0 7 42 1.1 jmcneill #define H3_RST_BUS_MMC1 8 43 1.1 jmcneill #define H3_RST_BUS_MMC2 9 44 1.1 jmcneill #define H3_RST_BUS_NAND 10 45 1.1 jmcneill #define H3_RST_BUS_DRAM 11 46 1.1 jmcneill #define H3_RST_BUS_EMAC 12 47 1.1 jmcneill #define H3_RST_BUS_TS 13 48 1.1 jmcneill #define H3_RST_BUS_HSTIMER 14 49 1.1 jmcneill #define H3_RST_BUS_SPI0 15 50 1.1 jmcneill #define H3_RST_BUS_SPI1 16 51 1.1 jmcneill #define H3_RST_BUS_OTG 17 52 1.1 jmcneill #define H3_RST_BUS_EHCI0 18 53 1.1 jmcneill #define H3_RST_BUS_EHCI1 19 54 1.1 jmcneill #define H3_RST_BUS_EHCI2 20 55 1.1 jmcneill #define H3_RST_BUS_EHCI3 21 56 1.1 jmcneill #define H3_RST_BUS_OHCI0 22 57 1.1 jmcneill #define H3_RST_BUS_OHCI1 23 58 1.1 jmcneill #define H3_RST_BUS_OHCI2 24 59 1.1 jmcneill #define H3_RST_BUS_OHCI3 25 60 1.1 jmcneill #define H3_RST_BUS_VE 26 61 1.1 jmcneill #define H3_RST_BUS_TCON0 27 62 1.1 jmcneill #define H3_RST_BUS_TCON1 28 63 1.1 jmcneill #define H3_RST_BUS_DEINTERLACE 29 64 1.1 jmcneill #define H3_RST_BUS_CSI 30 65 1.1 jmcneill #define H3_RST_BUS_TVE 31 66 1.1 jmcneill #define H3_RST_BUS_HDMI0 32 67 1.1 jmcneill #define H3_RST_BUS_HDMI1 33 68 1.1 jmcneill #define H3_RST_BUS_DE 34 69 1.1 jmcneill #define H3_RST_BUS_GPU 35 70 1.1 jmcneill #define H3_RST_BUS_MSGBOX 36 71 1.1 jmcneill #define H3_RST_BUS_SPINLOCK 37 72 1.1 jmcneill #define H3_RST_BUS_DBG 38 73 1.1 jmcneill #define H3_RST_BUS_EPHY 39 74 1.1 jmcneill #define H3_RST_BUS_CODEC 40 75 1.1 jmcneill #define H3_RST_BUS_SPDIF 41 76 1.1 jmcneill #define H3_RST_BUS_THS 42 77 1.1 jmcneill #define H3_RST_BUS_I2S0 43 78 1.1 jmcneill #define H3_RST_BUS_I2S1 44 79 1.1 jmcneill #define H3_RST_BUS_I2S2 45 80 1.1 jmcneill #define H3_RST_BUS_I2C0 46 81 1.1 jmcneill #define H3_RST_BUS_I2C1 47 82 1.1 jmcneill #define H3_RST_BUS_I2C2 48 83 1.1 jmcneill #define H3_RST_BUS_UART0 49 84 1.1 jmcneill #define H3_RST_BUS_UART1 50 85 1.1 jmcneill #define H3_RST_BUS_UART2 51 86 1.1 jmcneill #define H3_RST_BUS_UART3 52 87 1.1 jmcneill #define H3_RST_BUS_SCR 53 88 1.1 jmcneill 89 1.1 jmcneill #define H3_CLK_PLL_CPUX 0 90 1.1 jmcneill #define H3_CLK_PLL_AUDIO_BASE 1 91 1.1 jmcneill #define H3_CLK_PLL_AUDIO 2 92 1.1 jmcneill #define H3_CLK_PLL_AUDIO_2X 3 93 1.1 jmcneill #define H3_CLK_PLL_AUDIO_4X 4 94 1.1 jmcneill #define H3_CLK_PLL_AUDIO_8X 5 95 1.1 jmcneill #define H3_CLK_PLL_VIDEO 6 96 1.1 jmcneill #define H3_CLK_PLL_VE 7 97 1.1 jmcneill #define H3_CLK_PLL_DDR 8 98 1.1 jmcneill #define H3_CLK_PLL_PERIPH0 9 99 1.1 jmcneill #define H3_CLK_PLL_PERIPH0_2X 10 100 1.1 jmcneill #define H3_CLK_PLL_GPU 11 101 1.1 jmcneill #define H3_CLK_PLL_PERIPH1 12 102 1.1 jmcneill #define H3_CLK_PLL_DE 13 103 1.1 jmcneill #define H3_CLK_CPUX 14 104 1.1 jmcneill #define H3_CLK_AXI 15 105 1.1 jmcneill #define H3_CLK_AHB1 16 106 1.1 jmcneill #define H3_CLK_APB1 17 107 1.1 jmcneill #define H3_CLK_APB2 18 108 1.1 jmcneill #define H3_CLK_AHB2 19 109 1.1 jmcneill #define H3_CLK_BUS_CE 20 110 1.1 jmcneill #define H3_CLK_BUS_DMA 21 111 1.1 jmcneill #define H3_CLK_BUS_MMC0 22 112 1.1 jmcneill #define H3_CLK_BUS_MMC1 23 113 1.1 jmcneill #define H3_CLK_BUS_MMC2 24 114 1.1 jmcneill #define H3_CLK_BUS_NAND 25 115 1.1 jmcneill #define H3_CLK_BUS_DRAM 26 116 1.1 jmcneill #define H3_CLK_BUS_EMAC 27 117 1.1 jmcneill #define H3_CLK_BUS_TS 28 118 1.1 jmcneill #define H3_CLK_BUS_HSTIMER 29 119 1.1 jmcneill #define H3_CLK_BUS_SPI0 30 120 1.1 jmcneill #define H3_CLK_BUS_SPI1 31 121 1.1 jmcneill #define H3_CLK_BUS_OTG 32 122 1.1 jmcneill #define H3_CLK_BUS_EHCI0 33 123 1.1 jmcneill #define H3_CLK_BUS_EHCI1 34 124 1.1 jmcneill #define H3_CLK_BUS_EHCI2 35 125 1.1 jmcneill #define H3_CLK_BUS_EHCI3 36 126 1.1 jmcneill #define H3_CLK_BUS_OHCI0 37 127 1.1 jmcneill #define H3_CLK_BUS_OHCI1 38 128 1.1 jmcneill #define H3_CLK_BUS_OHCI2 39 129 1.1 jmcneill #define H3_CLK_BUS_OHCI3 40 130 1.1 jmcneill #define H3_CLK_BUS_VE 41 131 1.1 jmcneill #define H3_CLK_BUS_TCON0 42 132 1.1 jmcneill #define H3_CLK_BUS_TCON1 43 133 1.1 jmcneill #define H3_CLK_BUS_DEINTERLACE 44 134 1.1 jmcneill #define H3_CLK_BUS_CSI 45 135 1.1 jmcneill #define H3_CLK_BUS_TVE 46 136 1.1 jmcneill #define H3_CLK_BUS_HDMI 47 137 1.1 jmcneill #define H3_CLK_BUS_DE 48 138 1.1 jmcneill #define H3_CLK_BUS_GPU 49 139 1.1 jmcneill #define H3_CLK_BUS_MSGBOX 50 140 1.1 jmcneill #define H3_CLK_BUS_SPINLOCK 51 141 1.1 jmcneill #define H3_CLK_BUS_CODEC 52 142 1.1 jmcneill #define H3_CLK_BUS_SPDIF 53 143 1.1 jmcneill #define H3_CLK_BUS_PIO 54 144 1.1 jmcneill #define H3_CLK_BUS_THS 55 145 1.1 jmcneill #define H3_CLK_BUS_I2S0 56 146 1.1 jmcneill #define H3_CLK_BUS_I2S1 57 147 1.1 jmcneill #define H3_CLK_BUS_I2S2 58 148 1.1 jmcneill #define H3_CLK_BUS_I2C0 59 149 1.1 jmcneill #define H3_CLK_BUS_I2C1 60 150 1.1 jmcneill #define H3_CLK_BUS_I2C2 61 151 1.1 jmcneill #define H3_CLK_BUS_UART0 62 152 1.1 jmcneill #define H3_CLK_BUS_UART1 63 153 1.1 jmcneill #define H3_CLK_BUS_UART2 64 154 1.1 jmcneill #define H3_CLK_BUS_UART3 65 155 1.1 jmcneill #define H3_CLK_BUS_SCR 66 156 1.1 jmcneill #define H3_CLK_BUS_EPHY 67 157 1.1 jmcneill #define H3_CLK_BUS_DBG 68 158 1.1 jmcneill #define H3_CLK_THS 69 159 1.1 jmcneill #define H3_CLK_NAND 70 160 1.1 jmcneill #define H3_CLK_MMC0 71 161 1.1 jmcneill #define H3_CLK_MMC0_SAMPLE 72 162 1.1 jmcneill #define H3_CLK_MMC0_OUTPUT 73 163 1.1 jmcneill #define H3_CLK_MMC1 74 164 1.1 jmcneill #define H3_CLK_MMC1_SAMPLE 75 165 1.1 jmcneill #define H3_CLK_MMC1_OUTPUT 76 166 1.1 jmcneill #define H3_CLK_MMC2 77 167 1.1 jmcneill #define H3_CLK_MMC2_SAMPLE 78 168 1.1 jmcneill #define H3_CLK_MMC2_OUTPUT 79 169 1.1 jmcneill #define H3_CLK_TS 80 170 1.1 jmcneill #define H3_CLK_CE 81 171 1.1 jmcneill #define H3_CLK_SPI0 82 172 1.1 jmcneill #define H3_CLK_SPI1 83 173 1.1 jmcneill #define H3_CLK_I2S0 84 174 1.1 jmcneill #define H3_CLK_I2S1 85 175 1.1 jmcneill #define H3_CLK_I2S2 86 176 1.1 jmcneill #define H3_CLK_SPDIF 87 177 1.1 jmcneill #define H3_CLK_USBPHY0 88 178 1.1 jmcneill #define H3_CLK_USBPHY1 89 179 1.1 jmcneill #define H3_CLK_USBPHY2 90 180 1.1 jmcneill #define H3_CLK_USBPHY3 91 181 1.1 jmcneill #define H3_CLK_USBOHCI0 92 182 1.1 jmcneill #define H3_CLK_USBOHCI1 93 183 1.1 jmcneill #define H3_CLK_USBOHCI2 94 184 1.1 jmcneill #define H3_CLK_USBOHCI3 95 185 1.1 jmcneill #define H3_CLK_DRAM 96 186 1.1 jmcneill #define H3_CLK_DRAM_VE 97 187 1.1 jmcneill #define H3_CLK_DRAM_CSI 98 188 1.1 jmcneill #define H3_CLK_DRAM_DEINTERLACE 99 189 1.1 jmcneill #define H3_CLK_DRAM_TS 100 190 1.1 jmcneill #define H3_CLK_DE 101 191 1.1 jmcneill #define H3_CLK_TCON0 102 192 1.1 jmcneill #define H3_CLK_TVE 103 193 1.1 jmcneill #define H3_CLK_DEINTERLACE 104 194 1.1 jmcneill #define H3_CLK_CSI_MISC 105 195 1.1 jmcneill #define H3_CLK_CSI_SCLK 106 196 1.1 jmcneill #define H3_CLK_CSI_MCLK 107 197 1.1 jmcneill #define H3_CLK_VE 108 198 1.1 jmcneill #define H3_CLK_AC_DIG 109 199 1.1 jmcneill #define H3_CLK_AVS 110 200 1.1 jmcneill #define H3_CLK_HDMI 111 201 1.1 jmcneill #define H3_CLK_HDMI_DDC 112 202 1.1 jmcneill #define H3_CLK_MBUS 113 203 1.1 jmcneill #define H3_CLK_GPU 114 204 1.1 jmcneill 205 1.1 jmcneill #endif /* __CCU_H3_H__ */ 206