sun8i_h3_ccu.h revision 1.1.4.2 1 /* $NetBSD: sun8i_h3_ccu.h,v 1.1.4.2 2017/07/18 19:13:08 snj Exp $ */
2
3 /*-
4 * Copyright (c) 2017 Emmanuel Vadot <manu (at) freebsd.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 * $FreeBSD$
29 */
30
31 #ifndef __CCU_H3_H__
32 #define __CCU_H3_H__
33
34 #define H3_RST_USB_PHY0 0
35 #define H3_RST_USB_PHY1 1
36 #define H3_RST_USB_PHY2 2
37 #define H3_RST_USB_PHY3 3
38 #define H3_RST_MBUS 4
39 #define H3_RST_BUS_CE 5
40 #define H3_RST_BUS_DMA 6
41 #define H3_RST_BUS_MMC0 7
42 #define H3_RST_BUS_MMC1 8
43 #define H3_RST_BUS_MMC2 9
44 #define H3_RST_BUS_NAND 10
45 #define H3_RST_BUS_DRAM 11
46 #define H3_RST_BUS_EMAC 12
47 #define H3_RST_BUS_TS 13
48 #define H3_RST_BUS_HSTIMER 14
49 #define H3_RST_BUS_SPI0 15
50 #define H3_RST_BUS_SPI1 16
51 #define H3_RST_BUS_OTG 17
52 #define H3_RST_BUS_EHCI0 18
53 #define H3_RST_BUS_EHCI1 19
54 #define H3_RST_BUS_EHCI2 20
55 #define H3_RST_BUS_EHCI3 21
56 #define H3_RST_BUS_OHCI0 22
57 #define H3_RST_BUS_OHCI1 23
58 #define H3_RST_BUS_OHCI2 24
59 #define H3_RST_BUS_OHCI3 25
60 #define H3_RST_BUS_VE 26
61 #define H3_RST_BUS_TCON0 27
62 #define H3_RST_BUS_TCON1 28
63 #define H3_RST_BUS_DEINTERLACE 29
64 #define H3_RST_BUS_CSI 30
65 #define H3_RST_BUS_TVE 31
66 #define H3_RST_BUS_HDMI0 32
67 #define H3_RST_BUS_HDMI1 33
68 #define H3_RST_BUS_DE 34
69 #define H3_RST_BUS_GPU 35
70 #define H3_RST_BUS_MSGBOX 36
71 #define H3_RST_BUS_SPINLOCK 37
72 #define H3_RST_BUS_DBG 38
73 #define H3_RST_BUS_EPHY 39
74 #define H3_RST_BUS_CODEC 40
75 #define H3_RST_BUS_SPDIF 41
76 #define H3_RST_BUS_THS 42
77 #define H3_RST_BUS_I2S0 43
78 #define H3_RST_BUS_I2S1 44
79 #define H3_RST_BUS_I2S2 45
80 #define H3_RST_BUS_I2C0 46
81 #define H3_RST_BUS_I2C1 47
82 #define H3_RST_BUS_I2C2 48
83 #define H3_RST_BUS_UART0 49
84 #define H3_RST_BUS_UART1 50
85 #define H3_RST_BUS_UART2 51
86 #define H3_RST_BUS_UART3 52
87 #define H3_RST_BUS_SCR 53
88
89 #define H3_CLK_PLL_CPUX 0
90 #define H3_CLK_PLL_AUDIO_BASE 1
91 #define H3_CLK_PLL_AUDIO 2
92 #define H3_CLK_PLL_AUDIO_2X 3
93 #define H3_CLK_PLL_AUDIO_4X 4
94 #define H3_CLK_PLL_AUDIO_8X 5
95 #define H3_CLK_PLL_VIDEO 6
96 #define H3_CLK_PLL_VE 7
97 #define H3_CLK_PLL_DDR 8
98 #define H3_CLK_PLL_PERIPH0 9
99 #define H3_CLK_PLL_PERIPH0_2X 10
100 #define H3_CLK_PLL_GPU 11
101 #define H3_CLK_PLL_PERIPH1 12
102 #define H3_CLK_PLL_DE 13
103 #define H3_CLK_CPUX 14
104 #define H3_CLK_AXI 15
105 #define H3_CLK_AHB1 16
106 #define H3_CLK_APB1 17
107 #define H3_CLK_APB2 18
108 #define H3_CLK_AHB2 19
109 #define H3_CLK_BUS_CE 20
110 #define H3_CLK_BUS_DMA 21
111 #define H3_CLK_BUS_MMC0 22
112 #define H3_CLK_BUS_MMC1 23
113 #define H3_CLK_BUS_MMC2 24
114 #define H3_CLK_BUS_NAND 25
115 #define H3_CLK_BUS_DRAM 26
116 #define H3_CLK_BUS_EMAC 27
117 #define H3_CLK_BUS_TS 28
118 #define H3_CLK_BUS_HSTIMER 29
119 #define H3_CLK_BUS_SPI0 30
120 #define H3_CLK_BUS_SPI1 31
121 #define H3_CLK_BUS_OTG 32
122 #define H3_CLK_BUS_EHCI0 33
123 #define H3_CLK_BUS_EHCI1 34
124 #define H3_CLK_BUS_EHCI2 35
125 #define H3_CLK_BUS_EHCI3 36
126 #define H3_CLK_BUS_OHCI0 37
127 #define H3_CLK_BUS_OHCI1 38
128 #define H3_CLK_BUS_OHCI2 39
129 #define H3_CLK_BUS_OHCI3 40
130 #define H3_CLK_BUS_VE 41
131 #define H3_CLK_BUS_TCON0 42
132 #define H3_CLK_BUS_TCON1 43
133 #define H3_CLK_BUS_DEINTERLACE 44
134 #define H3_CLK_BUS_CSI 45
135 #define H3_CLK_BUS_TVE 46
136 #define H3_CLK_BUS_HDMI 47
137 #define H3_CLK_BUS_DE 48
138 #define H3_CLK_BUS_GPU 49
139 #define H3_CLK_BUS_MSGBOX 50
140 #define H3_CLK_BUS_SPINLOCK 51
141 #define H3_CLK_BUS_CODEC 52
142 #define H3_CLK_BUS_SPDIF 53
143 #define H3_CLK_BUS_PIO 54
144 #define H3_CLK_BUS_THS 55
145 #define H3_CLK_BUS_I2S0 56
146 #define H3_CLK_BUS_I2S1 57
147 #define H3_CLK_BUS_I2S2 58
148 #define H3_CLK_BUS_I2C0 59
149 #define H3_CLK_BUS_I2C1 60
150 #define H3_CLK_BUS_I2C2 61
151 #define H3_CLK_BUS_UART0 62
152 #define H3_CLK_BUS_UART1 63
153 #define H3_CLK_BUS_UART2 64
154 #define H3_CLK_BUS_UART3 65
155 #define H3_CLK_BUS_SCR 66
156 #define H3_CLK_BUS_EPHY 67
157 #define H3_CLK_BUS_DBG 68
158 #define H3_CLK_THS 69
159 #define H3_CLK_NAND 70
160 #define H3_CLK_MMC0 71
161 #define H3_CLK_MMC0_SAMPLE 72
162 #define H3_CLK_MMC0_OUTPUT 73
163 #define H3_CLK_MMC1 74
164 #define H3_CLK_MMC1_SAMPLE 75
165 #define H3_CLK_MMC1_OUTPUT 76
166 #define H3_CLK_MMC2 77
167 #define H3_CLK_MMC2_SAMPLE 78
168 #define H3_CLK_MMC2_OUTPUT 79
169 #define H3_CLK_TS 80
170 #define H3_CLK_CE 81
171 #define H3_CLK_SPI0 82
172 #define H3_CLK_SPI1 83
173 #define H3_CLK_I2S0 84
174 #define H3_CLK_I2S1 85
175 #define H3_CLK_I2S2 86
176 #define H3_CLK_SPDIF 87
177 #define H3_CLK_USBPHY0 88
178 #define H3_CLK_USBPHY1 89
179 #define H3_CLK_USBPHY2 90
180 #define H3_CLK_USBPHY3 91
181 #define H3_CLK_USBOHCI0 92
182 #define H3_CLK_USBOHCI1 93
183 #define H3_CLK_USBOHCI2 94
184 #define H3_CLK_USBOHCI3 95
185 #define H3_CLK_DRAM 96
186 #define H3_CLK_DRAM_VE 97
187 #define H3_CLK_DRAM_CSI 98
188 #define H3_CLK_DRAM_DEINTERLACE 99
189 #define H3_CLK_DRAM_TS 100
190 #define H3_CLK_DE 101
191 #define H3_CLK_TCON0 102
192 #define H3_CLK_TVE 103
193 #define H3_CLK_DEINTERLACE 104
194 #define H3_CLK_CSI_MISC 105
195 #define H3_CLK_CSI_SCLK 106
196 #define H3_CLK_CSI_MCLK 107
197 #define H3_CLK_VE 108
198 #define H3_CLK_AC_DIG 109
199 #define H3_CLK_AVS 110
200 #define H3_CLK_HDMI 111
201 #define H3_CLK_HDMI_DDC 112
202 #define H3_CLK_MBUS 113
203 #define H3_CLK_GPU 114
204
205 #endif /* __CCU_H3_H__ */
206