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      1  1.1  jmcneill /* $NetBSD: sun9i_a80_ccu.h,v 1.1 2017/10/08 18:00:36 jmcneill Exp $ */
      2  1.1  jmcneill 
      3  1.1  jmcneill /*-
      4  1.1  jmcneill  * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca>
      5  1.1  jmcneill  * All rights reserved.
      6  1.1  jmcneill  *
      7  1.1  jmcneill  * Redistribution and use in source and binary forms, with or without
      8  1.1  jmcneill  * modification, are permitted provided that the following conditions
      9  1.1  jmcneill  * are met:
     10  1.1  jmcneill  * 1. Redistributions of source code must retain the above copyright
     11  1.1  jmcneill  *    notice, this list of conditions and the following disclaimer.
     12  1.1  jmcneill  * 2. Redistributions in binary form must reproduce the above copyright
     13  1.1  jmcneill  *    notice, this list of conditions and the following disclaimer in the
     14  1.1  jmcneill  *    documentation and/or other materials provided with the distribution.
     15  1.1  jmcneill  *
     16  1.1  jmcneill  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     17  1.1  jmcneill  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     18  1.1  jmcneill  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     19  1.1  jmcneill  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     20  1.1  jmcneill  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
     21  1.1  jmcneill  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     22  1.1  jmcneill  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
     23  1.1  jmcneill  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     24  1.1  jmcneill  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     25  1.1  jmcneill  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     26  1.1  jmcneill  * SUCH DAMAGE.
     27  1.1  jmcneill  */
     28  1.1  jmcneill 
     29  1.1  jmcneill #ifndef _SUN9I_A80_CCU_H
     30  1.1  jmcneill #define	_SUN9I_A80_CCU_H
     31  1.1  jmcneill 
     32  1.1  jmcneill #define	A80_RST_BUS_FD		0
     33  1.1  jmcneill #define	A80_RST_BUS_VE		1
     34  1.1  jmcneill #define	A80_RST_BUS_GPU_CTRL	2
     35  1.1  jmcneill #define	A80_RST_BUS_SS		3
     36  1.1  jmcneill #define	A80_RST_BUS_MMC		4
     37  1.1  jmcneill #define	A80_RST_BUS_NAND0	5
     38  1.1  jmcneill #define	A80_RST_BUS_NAND1	6
     39  1.1  jmcneill #define	A80_RST_BUS_SDRAM	7
     40  1.1  jmcneill #define	A80_RST_BUS_SATA	8
     41  1.1  jmcneill #define	A80_RST_BUS_TS		9
     42  1.1  jmcneill #define	A80_RST_BUS_SPI0	10
     43  1.1  jmcneill #define	A80_RST_BUS_SPI1	11
     44  1.1  jmcneill #define	A80_RST_BUS_SPI2	12
     45  1.1  jmcneill #define	A80_RST_BUS_SPI3	13
     46  1.1  jmcneill #define	A80_RST_BUS_OTG		14
     47  1.1  jmcneill #define	A80_RST_BUS_OTG_PHY	15
     48  1.1  jmcneill #define	A80_RST_BUS_MIPI_HSI	16
     49  1.1  jmcneill #define	A80_RST_BUS_GMAC	17
     50  1.1  jmcneill #define	A80_RST_BUS_MSGBOX	18
     51  1.1  jmcneill #define	A80_RST_BUS_SPINLOCK	19
     52  1.1  jmcneill #define	A80_RST_BUS_HSTIMER	20
     53  1.1  jmcneill #define	A80_RST_BUS_DMA		21
     54  1.1  jmcneill #define	A80_RST_BUS_LCD0	22
     55  1.1  jmcneill #define	A80_RST_BUS_LCD1	23
     56  1.1  jmcneill #define	A80_RST_BUS_EDP		24
     57  1.1  jmcneill #define	A80_RST_BUS_LVDS	25
     58  1.1  jmcneill #define	A80_RST_BUS_CSI		26
     59  1.1  jmcneill #define	A80_RST_BUS_HDMI0	27
     60  1.1  jmcneill #define	A80_RST_BUS_HDMI1	28
     61  1.1  jmcneill #define	A80_RST_BUS_DE		29
     62  1.1  jmcneill #define	A80_RST_BUS_MP		30
     63  1.1  jmcneill #define	A80_RST_BUS_GPU		31
     64  1.1  jmcneill #define	A80_RST_BUS_MIPI_DSI	32
     65  1.1  jmcneill #define	A80_RST_BUS_SPDIF	33
     66  1.1  jmcneill #define	A80_RST_BUS_AC97	34
     67  1.1  jmcneill #define	A80_RST_BUS_I2S0	35
     68  1.1  jmcneill #define	A80_RST_BUS_I2S1	36
     69  1.1  jmcneill #define	A80_RST_BUS_LRADC	37
     70  1.1  jmcneill #define	A80_RST_BUS_GPADC	38
     71  1.1  jmcneill #define	A80_RST_BUS_CIR_TX	39
     72  1.1  jmcneill #define	A80_RST_BUS_I2C0	40
     73  1.1  jmcneill #define	A80_RST_BUS_I2C1	41
     74  1.1  jmcneill #define	A80_RST_BUS_I2C2	42
     75  1.1  jmcneill #define	A80_RST_BUS_I2C3	43
     76  1.1  jmcneill #define	A80_RST_BUS_I2C4	44
     77  1.1  jmcneill #define	A80_RST_BUS_UART0	45
     78  1.1  jmcneill #define	A80_RST_BUS_UART1	46
     79  1.1  jmcneill #define	A80_RST_BUS_UART2	47
     80  1.1  jmcneill #define	A80_RST_BUS_UART3	48
     81  1.1  jmcneill #define	A80_RST_BUS_UART4	49
     82  1.1  jmcneill #define	A80_RST_BUS_UART5	50
     83  1.1  jmcneill 
     84  1.1  jmcneill #define	A80_CLK_PLL_C0CPUX	0
     85  1.1  jmcneill #define	A80_CLK_PLL_C1CPUX	1
     86  1.1  jmcneill #define	A80_CLK_PLL_AUDIO	2
     87  1.1  jmcneill #define	A80_CLK_PLL_PERIPH0	3
     88  1.1  jmcneill #define	A80_CLK_PLL_VE		4
     89  1.1  jmcneill #define	A80_CLK_PLL_DDR		5
     90  1.1  jmcneill #define	A80_CLK_PLL_VIDEO0	6
     91  1.1  jmcneill #define	A80_CLK_PLL_VIDEO1	7
     92  1.1  jmcneill #define	A80_CLK_PLL_GPU		8
     93  1.1  jmcneill #define	A80_CLK_PLL_DE		9
     94  1.1  jmcneill #define	A80_CLK_PLL_ISP		10
     95  1.1  jmcneill #define	A80_CLK_PLL_PERIPH1	11
     96  1.1  jmcneill #define	A80_CLK_C0CPUX		12
     97  1.1  jmcneill #define	A80_CLK_C1CPUX		13
     98  1.1  jmcneill #define	A80_CLK_ATB0		14
     99  1.1  jmcneill #define	A80_CLK_AXI0		15
    100  1.1  jmcneill #define	A80_CLK_ATB1		16
    101  1.1  jmcneill #define	A80_CLK_AXI1		17
    102  1.1  jmcneill #define	A80_CLK_GTBUS		18
    103  1.1  jmcneill #define	A80_CLK_AHB0		19
    104  1.1  jmcneill #define	A80_CLK_AHB1		20
    105  1.1  jmcneill #define	A80_CLK_AHB2		21
    106  1.1  jmcneill #define	A80_CLK_APB0		22
    107  1.1  jmcneill #define	A80_CLK_APB1		23
    108  1.1  jmcneill #define	A80_CLK_CCI400		24
    109  1.1  jmcneill #define	A80_CLK_ATS		25
    110  1.1  jmcneill #define	A80_CLK_TRACE		26
    111  1.1  jmcneill #define	A80_CLK_OUT_A		27
    112  1.1  jmcneill #define	A80_CLK_OUT_B		28
    113  1.1  jmcneill #define	A80_CLK_NAND0_0		29
    114  1.1  jmcneill #define	A80_CLK_NAND0_1		30
    115  1.1  jmcneill #define	A80_CLK_NAND1_0		31
    116  1.1  jmcneill #define	A80_CLK_NAND1_1		32
    117  1.1  jmcneill #define	A80_CLK_MMC0		33
    118  1.1  jmcneill #define	A80_CLK_MMC0_SAMPLE	34
    119  1.1  jmcneill #define	A80_CLK_MMC0_OUTPUT	35
    120  1.1  jmcneill #define	A80_CLK_MMC1		36
    121  1.1  jmcneill #define	A80_CLK_MMC1_SAMPLE	37
    122  1.1  jmcneill #define	A80_CLK_MMC1_OUTPUT	38
    123  1.1  jmcneill #define	A80_CLK_MMC2		39
    124  1.1  jmcneill #define	A80_CLK_MMC2_SAMPLE	40
    125  1.1  jmcneill #define	A80_CLK_MMC2_OUTPUT	41
    126  1.1  jmcneill #define	A80_CLK_MMC3		42
    127  1.1  jmcneill #define	A80_CLK_MMC3_SAMPLE	43
    128  1.1  jmcneill #define	A80_CLK_MMC3_OUTPUT	44
    129  1.1  jmcneill #define	A80_CLK_TS		45
    130  1.1  jmcneill #define	A80_CLK_SS		46
    131  1.1  jmcneill #define	A80_CLK_SPI0		47
    132  1.1  jmcneill #define	A80_CLK_SPI1		48
    133  1.1  jmcneill #define	A80_CLK_SPI2		49
    134  1.1  jmcneill #define	A80_CLK_SPI3		50
    135  1.1  jmcneill #define	A80_CLK_I2S0		51
    136  1.1  jmcneill #define	A80_CLK_I2S1		52
    137  1.1  jmcneill #define	A80_CLK_SPDIF		53
    138  1.1  jmcneill #define	A80_CLK_SDRAM		54
    139  1.1  jmcneill #define	A80_CLK_DE		55
    140  1.1  jmcneill #define	A80_CLK_EDP		56
    141  1.1  jmcneill #define	A80_CLK_MP		57
    142  1.1  jmcneill #define	A80_CLK_LCD0		58
    143  1.1  jmcneill #define	A80_CLK_LCD1		59
    144  1.1  jmcneill #define	A80_CLK_MIPI_DSI0	60
    145  1.1  jmcneill #define	A80_CLK_MIPI_DSI1	61
    146  1.1  jmcneill #define	A80_CLK_HDMI		62
    147  1.1  jmcneill #define	A80_CLK_HDMI_SLOW	63
    148  1.1  jmcneill #define	A80_CLK_MIPI_CSI	64
    149  1.1  jmcneill #define	A80_CLK_CSI_ISP		65
    150  1.1  jmcneill #define	A80_CLK_CSI_MISC	66
    151  1.1  jmcneill #define	A80_CLK_CSI0_MCLK	67
    152  1.1  jmcneill #define	A80_CLK_CSI1_MCLK	68
    153  1.1  jmcneill #define	A80_CLK_FD		69
    154  1.1  jmcneill #define	A80_CLK_VE		70
    155  1.1  jmcneill #define	A80_CLK_AVS		71
    156  1.1  jmcneill #define	A80_CLK_GPU_CORE	72
    157  1.1  jmcneill #define	A80_CLK_GPU_MEMORY	73
    158  1.1  jmcneill #define	A80_CLK_GPU_AXI		74
    159  1.1  jmcneill #define	A80_CLK_SATA		75
    160  1.1  jmcneill #define	A80_CLK_AC97		76
    161  1.1  jmcneill #define	A80_CLK_MIPI_HSI	77
    162  1.1  jmcneill #define	A80_CLK_GPADC		78
    163  1.1  jmcneill #define	A80_CLK_CIR_TX		79
    164  1.1  jmcneill #define	A80_CLK_BUS_FD		80
    165  1.1  jmcneill #define	A80_CLK_BUS_VE		81
    166  1.1  jmcneill #define	A80_CLK_BUS_GPU_CTRL	82
    167  1.1  jmcneill #define	A80_CLK_BUS_SS		83
    168  1.1  jmcneill #define	A80_CLK_BUS_MMC		84
    169  1.1  jmcneill #define	A80_CLK_BUS_NAND0	85
    170  1.1  jmcneill #define	A80_CLK_BUS_NAND1	86
    171  1.1  jmcneill #define	A80_CLK_BUS_SDRAM	87
    172  1.1  jmcneill #define	A80_CLK_BUS_MIPI_HSI	88
    173  1.1  jmcneill #define	A80_CLK_BUS_SATA	89
    174  1.1  jmcneill #define	A80_CLK_BUS_TS		90
    175  1.1  jmcneill #define	A80_CLK_BUS_SPI0	91
    176  1.1  jmcneill #define	A80_CLK_BUS_SPI1	92
    177  1.1  jmcneill #define	A80_CLK_BUS_SPI2	93
    178  1.1  jmcneill #define	A80_CLK_BUS_SPI3	94
    179  1.1  jmcneill #define	A80_CLK_BUS_OTG		95
    180  1.1  jmcneill #define	A80_CLK_BUS_USB		96
    181  1.1  jmcneill #define	A80_CLK_BUS_GMAC	97
    182  1.1  jmcneill #define	A80_CLK_BUS_MSGBOX	98
    183  1.1  jmcneill #define	A80_CLK_BUS_SPINLOCK	99
    184  1.1  jmcneill #define	A80_CLK_BUS_HSTIMER	100
    185  1.1  jmcneill #define	A80_CLK_BUS_DMA		101
    186  1.1  jmcneill #define	A80_CLK_BUS_LCD0	102
    187  1.1  jmcneill #define	A80_CLK_BUS_LCD1	103
    188  1.1  jmcneill #define	A80_CLK_BUS_EDP		104
    189  1.1  jmcneill #define	A80_CLK_BUS_CSI		105
    190  1.1  jmcneill #define	A80_CLK_BUS_HDMI	106
    191  1.1  jmcneill #define	A80_CLK_BUS_DE		107
    192  1.1  jmcneill #define	A80_CLK_BUS_MP		108
    193  1.1  jmcneill #define	A80_CLK_BUS_MIPI_DSI	109
    194  1.1  jmcneill #define	A80_CLK_BUS_SPDIF	110
    195  1.1  jmcneill #define	A80_CLK_BUS_PIO		111
    196  1.1  jmcneill #define	A80_CLK_BUS_AC97	112
    197  1.1  jmcneill #define	A80_CLK_BUS_I2S0	113
    198  1.1  jmcneill #define	A80_CLK_BUS_I2S1	114
    199  1.1  jmcneill #define	A80_CLK_BUS_LRADC	115
    200  1.1  jmcneill #define	A80_CLK_BUS_GPADC	116
    201  1.1  jmcneill #define	A80_CLK_BUS_TWD		117
    202  1.1  jmcneill #define	A80_CLK_BUS_CIR_TX	118
    203  1.1  jmcneill #define	A80_CLK_BUS_I2C0	119
    204  1.1  jmcneill #define	A80_CLK_BUS_I2C1	120
    205  1.1  jmcneill #define	A80_CLK_BUS_I2C2	121
    206  1.1  jmcneill #define	A80_CLK_BUS_I2C3	122
    207  1.1  jmcneill #define	A80_CLK_BUS_I2C4	123
    208  1.1  jmcneill #define	A80_CLK_BUS_UART0	124
    209  1.1  jmcneill #define	A80_CLK_BUS_UART1	125
    210  1.1  jmcneill #define	A80_CLK_BUS_UART2	126
    211  1.1  jmcneill #define	A80_CLK_BUS_UART3	127
    212  1.1  jmcneill #define	A80_CLK_BUS_UART4	128
    213  1.1  jmcneill #define	A80_CLK_BUS_UART5	129
    214  1.1  jmcneill 
    215  1.1  jmcneill #endif /* !_SUN9I_A80_CCU_H */
    216