sunxi_ccu.c revision 1.10 1 1.10 jmcneill /* $NetBSD: sunxi_ccu.c,v 1.10 2018/04/28 15:21:24 jmcneill Exp $ */
2 1.1 jmcneill
3 1.1 jmcneill /*-
4 1.1 jmcneill * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca>
5 1.1 jmcneill * All rights reserved.
6 1.1 jmcneill *
7 1.1 jmcneill * Redistribution and use in source and binary forms, with or without
8 1.1 jmcneill * modification, are permitted provided that the following conditions
9 1.1 jmcneill * are met:
10 1.1 jmcneill * 1. Redistributions of source code must retain the above copyright
11 1.1 jmcneill * notice, this list of conditions and the following disclaimer.
12 1.1 jmcneill * 2. Redistributions in binary form must reproduce the above copyright
13 1.1 jmcneill * notice, this list of conditions and the following disclaimer in the
14 1.1 jmcneill * documentation and/or other materials provided with the distribution.
15 1.1 jmcneill *
16 1.1 jmcneill * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 1.1 jmcneill * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 1.1 jmcneill * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 1.1 jmcneill * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 1.1 jmcneill * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 1.1 jmcneill * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 1.1 jmcneill * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 1.1 jmcneill * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 1.1 jmcneill * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 1.1 jmcneill * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 1.1 jmcneill * SUCH DAMAGE.
27 1.1 jmcneill */
28 1.1 jmcneill
29 1.1 jmcneill #include "opt_soc.h"
30 1.1 jmcneill #include "opt_multiprocessor.h"
31 1.1 jmcneill #include "opt_fdt_arm.h"
32 1.1 jmcneill
33 1.1 jmcneill #include <sys/cdefs.h>
34 1.10 jmcneill __KERNEL_RCSID(0, "$NetBSD: sunxi_ccu.c,v 1.10 2018/04/28 15:21:24 jmcneill Exp $");
35 1.1 jmcneill
36 1.1 jmcneill #include <sys/param.h>
37 1.1 jmcneill #include <sys/bus.h>
38 1.1 jmcneill #include <sys/cpu.h>
39 1.1 jmcneill #include <sys/device.h>
40 1.1 jmcneill
41 1.1 jmcneill #include <dev/fdt/fdtvar.h>
42 1.1 jmcneill
43 1.1 jmcneill #include <dev/clk/clk_backend.h>
44 1.1 jmcneill
45 1.1 jmcneill #include <arm/sunxi/sunxi_ccu.h>
46 1.1 jmcneill
47 1.1 jmcneill static void *
48 1.1 jmcneill sunxi_ccu_reset_acquire(device_t dev, const void *data, size_t len)
49 1.1 jmcneill {
50 1.1 jmcneill struct sunxi_ccu_softc * const sc = device_private(dev);
51 1.1 jmcneill struct sunxi_ccu_reset *reset;
52 1.1 jmcneill
53 1.1 jmcneill if (len != 4)
54 1.1 jmcneill return NULL;
55 1.1 jmcneill
56 1.1 jmcneill const u_int reset_id = be32dec(data);
57 1.1 jmcneill
58 1.1 jmcneill if (reset_id >= sc->sc_nresets)
59 1.1 jmcneill return NULL;
60 1.1 jmcneill
61 1.1 jmcneill reset = &sc->sc_resets[reset_id];
62 1.1 jmcneill if (reset->mask == 0)
63 1.1 jmcneill return NULL;
64 1.1 jmcneill
65 1.1 jmcneill return reset;
66 1.1 jmcneill }
67 1.1 jmcneill
68 1.1 jmcneill static void
69 1.1 jmcneill sunxi_ccu_reset_release(device_t dev, void *priv)
70 1.1 jmcneill {
71 1.1 jmcneill }
72 1.1 jmcneill
73 1.1 jmcneill static int
74 1.1 jmcneill sunxi_ccu_reset_assert(device_t dev, void *priv)
75 1.1 jmcneill {
76 1.1 jmcneill struct sunxi_ccu_softc * const sc = device_private(dev);
77 1.1 jmcneill struct sunxi_ccu_reset * const reset = priv;
78 1.1 jmcneill
79 1.1 jmcneill const uint32_t val = CCU_READ(sc, reset->reg);
80 1.1 jmcneill CCU_WRITE(sc, reset->reg, val & ~reset->mask);
81 1.1 jmcneill
82 1.1 jmcneill return 0;
83 1.1 jmcneill }
84 1.1 jmcneill
85 1.1 jmcneill static int
86 1.1 jmcneill sunxi_ccu_reset_deassert(device_t dev, void *priv)
87 1.1 jmcneill {
88 1.1 jmcneill struct sunxi_ccu_softc * const sc = device_private(dev);
89 1.1 jmcneill struct sunxi_ccu_reset * const reset = priv;
90 1.1 jmcneill
91 1.1 jmcneill const uint32_t val = CCU_READ(sc, reset->reg);
92 1.1 jmcneill CCU_WRITE(sc, reset->reg, val | reset->mask);
93 1.1 jmcneill
94 1.1 jmcneill return 0;
95 1.1 jmcneill }
96 1.1 jmcneill
97 1.1 jmcneill static const struct fdtbus_reset_controller_func sunxi_ccu_fdtreset_funcs = {
98 1.1 jmcneill .acquire = sunxi_ccu_reset_acquire,
99 1.1 jmcneill .release = sunxi_ccu_reset_release,
100 1.1 jmcneill .reset_assert = sunxi_ccu_reset_assert,
101 1.1 jmcneill .reset_deassert = sunxi_ccu_reset_deassert,
102 1.1 jmcneill };
103 1.1 jmcneill
104 1.1 jmcneill static struct clk *
105 1.1 jmcneill sunxi_ccu_clock_decode(device_t dev, const void *data, size_t len)
106 1.1 jmcneill {
107 1.1 jmcneill struct sunxi_ccu_softc * const sc = device_private(dev);
108 1.1 jmcneill struct sunxi_ccu_clk *clk;
109 1.1 jmcneill
110 1.1 jmcneill if (len != 4)
111 1.1 jmcneill return NULL;
112 1.1 jmcneill
113 1.1 jmcneill const u_int clock_id = be32dec(data);
114 1.1 jmcneill if (clock_id >= sc->sc_nclks)
115 1.1 jmcneill return NULL;
116 1.1 jmcneill
117 1.1 jmcneill clk = &sc->sc_clks[clock_id];
118 1.1 jmcneill if (clk->type == SUNXI_CCU_UNKNOWN)
119 1.1 jmcneill return NULL;
120 1.1 jmcneill
121 1.1 jmcneill return &clk->base;
122 1.1 jmcneill }
123 1.1 jmcneill
124 1.1 jmcneill static const struct fdtbus_clock_controller_func sunxi_ccu_fdtclock_funcs = {
125 1.1 jmcneill .decode = sunxi_ccu_clock_decode,
126 1.1 jmcneill };
127 1.1 jmcneill
128 1.1 jmcneill static struct clk *
129 1.1 jmcneill sunxi_ccu_clock_get(void *priv, const char *name)
130 1.1 jmcneill {
131 1.1 jmcneill struct sunxi_ccu_softc * const sc = priv;
132 1.1 jmcneill struct sunxi_ccu_clk *clk;
133 1.1 jmcneill
134 1.1 jmcneill clk = sunxi_ccu_clock_find(sc, name);
135 1.1 jmcneill if (clk == NULL)
136 1.1 jmcneill return NULL;
137 1.1 jmcneill
138 1.1 jmcneill return &clk->base;
139 1.1 jmcneill }
140 1.1 jmcneill
141 1.1 jmcneill static void
142 1.1 jmcneill sunxi_ccu_clock_put(void *priv, struct clk *clk)
143 1.1 jmcneill {
144 1.1 jmcneill }
145 1.1 jmcneill
146 1.1 jmcneill static u_int
147 1.1 jmcneill sunxi_ccu_clock_get_rate(void *priv, struct clk *clkp)
148 1.1 jmcneill {
149 1.1 jmcneill struct sunxi_ccu_softc * const sc = priv;
150 1.1 jmcneill struct sunxi_ccu_clk *clk = (struct sunxi_ccu_clk *)clkp;
151 1.1 jmcneill struct clk *clkp_parent;
152 1.1 jmcneill
153 1.1 jmcneill if (clk->get_rate)
154 1.1 jmcneill return clk->get_rate(sc, clk);
155 1.1 jmcneill
156 1.1 jmcneill clkp_parent = clk_get_parent(clkp);
157 1.1 jmcneill if (clkp_parent == NULL) {
158 1.1 jmcneill aprint_error("%s: no parent for %s\n", __func__, clk->base.name);
159 1.1 jmcneill return 0;
160 1.1 jmcneill }
161 1.1 jmcneill
162 1.1 jmcneill return clk_get_rate(clkp_parent);
163 1.1 jmcneill }
164 1.1 jmcneill
165 1.1 jmcneill static int
166 1.1 jmcneill sunxi_ccu_clock_set_rate(void *priv, struct clk *clkp, u_int rate)
167 1.1 jmcneill {
168 1.1 jmcneill struct sunxi_ccu_softc * const sc = priv;
169 1.1 jmcneill struct sunxi_ccu_clk *clk = (struct sunxi_ccu_clk *)clkp;
170 1.1 jmcneill struct clk *clkp_parent;
171 1.1 jmcneill
172 1.1 jmcneill if (clkp->flags & CLK_SET_RATE_PARENT) {
173 1.1 jmcneill clkp_parent = clk_get_parent(clkp);
174 1.1 jmcneill if (clkp_parent == NULL) {
175 1.1 jmcneill aprint_error("%s: no parent for %s\n", __func__, clk->base.name);
176 1.1 jmcneill return ENXIO;
177 1.1 jmcneill }
178 1.1 jmcneill return clk_set_rate(clkp_parent, rate);
179 1.1 jmcneill }
180 1.1 jmcneill
181 1.1 jmcneill if (clk->set_rate)
182 1.1 jmcneill return clk->set_rate(sc, clk, rate);
183 1.1 jmcneill
184 1.1 jmcneill return ENXIO;
185 1.1 jmcneill }
186 1.1 jmcneill
187 1.9 bouyer static u_int
188 1.9 bouyer sunxi_ccu_clock_round_rate(void *priv, struct clk *clkp, u_int rate)
189 1.9 bouyer {
190 1.9 bouyer struct sunxi_ccu_softc * const sc = priv;
191 1.9 bouyer struct sunxi_ccu_clk *clk = (struct sunxi_ccu_clk *)clkp;
192 1.9 bouyer struct clk *clkp_parent;
193 1.9 bouyer
194 1.9 bouyer if (clkp->flags & CLK_SET_RATE_PARENT) {
195 1.9 bouyer clkp_parent = clk_get_parent(clkp);
196 1.9 bouyer if (clkp_parent == NULL) {
197 1.9 bouyer aprint_error("%s: no parent for %s\n", __func__, clk->base.name);
198 1.9 bouyer return 0;
199 1.9 bouyer }
200 1.9 bouyer return clk_round_rate(clkp_parent, rate);
201 1.9 bouyer }
202 1.9 bouyer
203 1.9 bouyer if (clk->round_rate)
204 1.9 bouyer return clk->round_rate(sc, clk, rate);
205 1.9 bouyer
206 1.9 bouyer return 0;
207 1.9 bouyer }
208 1.9 bouyer
209 1.1 jmcneill static int
210 1.1 jmcneill sunxi_ccu_clock_enable(void *priv, struct clk *clkp)
211 1.1 jmcneill {
212 1.1 jmcneill struct sunxi_ccu_softc * const sc = priv;
213 1.1 jmcneill struct sunxi_ccu_clk *clk = (struct sunxi_ccu_clk *)clkp;
214 1.1 jmcneill struct clk *clkp_parent;
215 1.1 jmcneill int error = 0;
216 1.1 jmcneill
217 1.1 jmcneill clkp_parent = clk_get_parent(clkp);
218 1.1 jmcneill if (clkp_parent != NULL) {
219 1.1 jmcneill error = clk_enable(clkp_parent);
220 1.1 jmcneill if (error != 0)
221 1.1 jmcneill return error;
222 1.1 jmcneill }
223 1.1 jmcneill
224 1.1 jmcneill if (clk->enable)
225 1.1 jmcneill error = clk->enable(sc, clk, 1);
226 1.1 jmcneill
227 1.1 jmcneill return error;
228 1.1 jmcneill }
229 1.1 jmcneill
230 1.1 jmcneill static int
231 1.1 jmcneill sunxi_ccu_clock_disable(void *priv, struct clk *clkp)
232 1.1 jmcneill {
233 1.1 jmcneill struct sunxi_ccu_softc * const sc = priv;
234 1.1 jmcneill struct sunxi_ccu_clk *clk = (struct sunxi_ccu_clk *)clkp;
235 1.1 jmcneill int error = EINVAL;
236 1.1 jmcneill
237 1.1 jmcneill if (clk->enable)
238 1.1 jmcneill error = clk->enable(sc, clk, 0);
239 1.1 jmcneill
240 1.1 jmcneill return error;
241 1.1 jmcneill }
242 1.1 jmcneill
243 1.1 jmcneill static int
244 1.1 jmcneill sunxi_ccu_clock_set_parent(void *priv, struct clk *clkp,
245 1.1 jmcneill struct clk *clkp_parent)
246 1.1 jmcneill {
247 1.1 jmcneill struct sunxi_ccu_softc * const sc = priv;
248 1.1 jmcneill struct sunxi_ccu_clk *clk = (struct sunxi_ccu_clk *)clkp;
249 1.1 jmcneill
250 1.1 jmcneill if (clk->set_parent == NULL)
251 1.1 jmcneill return EINVAL;
252 1.1 jmcneill
253 1.1 jmcneill return clk->set_parent(sc, clk, clkp_parent->name);
254 1.1 jmcneill }
255 1.1 jmcneill
256 1.1 jmcneill static struct clk *
257 1.1 jmcneill sunxi_ccu_clock_get_parent(void *priv, struct clk *clkp)
258 1.1 jmcneill {
259 1.1 jmcneill struct sunxi_ccu_softc * const sc = priv;
260 1.1 jmcneill struct sunxi_ccu_clk *clk = (struct sunxi_ccu_clk *)clkp;
261 1.1 jmcneill struct sunxi_ccu_clk *clk_parent;
262 1.1 jmcneill const char *parent;
263 1.1 jmcneill
264 1.1 jmcneill if (clk->get_parent == NULL)
265 1.1 jmcneill return NULL;
266 1.1 jmcneill
267 1.1 jmcneill parent = clk->get_parent(sc, clk);
268 1.1 jmcneill if (parent == NULL)
269 1.1 jmcneill return NULL;
270 1.1 jmcneill
271 1.1 jmcneill clk_parent = sunxi_ccu_clock_find(sc, parent);
272 1.1 jmcneill if (clk_parent != NULL)
273 1.1 jmcneill return &clk_parent->base;
274 1.1 jmcneill
275 1.1 jmcneill /* No parent in this domain, try FDT */
276 1.1 jmcneill return fdtbus_clock_get(sc->sc_phandle, parent);
277 1.1 jmcneill }
278 1.1 jmcneill
279 1.1 jmcneill static const struct clk_funcs sunxi_ccu_clock_funcs = {
280 1.1 jmcneill .get = sunxi_ccu_clock_get,
281 1.1 jmcneill .put = sunxi_ccu_clock_put,
282 1.1 jmcneill .get_rate = sunxi_ccu_clock_get_rate,
283 1.1 jmcneill .set_rate = sunxi_ccu_clock_set_rate,
284 1.9 bouyer .round_rate = sunxi_ccu_clock_round_rate,
285 1.1 jmcneill .enable = sunxi_ccu_clock_enable,
286 1.1 jmcneill .disable = sunxi_ccu_clock_disable,
287 1.1 jmcneill .set_parent = sunxi_ccu_clock_set_parent,
288 1.1 jmcneill .get_parent = sunxi_ccu_clock_get_parent,
289 1.1 jmcneill };
290 1.1 jmcneill
291 1.1 jmcneill struct sunxi_ccu_clk *
292 1.1 jmcneill sunxi_ccu_clock_find(struct sunxi_ccu_softc *sc, const char *name)
293 1.1 jmcneill {
294 1.1 jmcneill for (int i = 0; i < sc->sc_nclks; i++) {
295 1.1 jmcneill if (sc->sc_clks[i].base.name == NULL)
296 1.1 jmcneill continue;
297 1.1 jmcneill if (strcmp(sc->sc_clks[i].base.name, name) == 0)
298 1.1 jmcneill return &sc->sc_clks[i];
299 1.1 jmcneill }
300 1.1 jmcneill
301 1.1 jmcneill return NULL;
302 1.1 jmcneill }
303 1.1 jmcneill
304 1.1 jmcneill int
305 1.1 jmcneill sunxi_ccu_attach(struct sunxi_ccu_softc *sc)
306 1.1 jmcneill {
307 1.1 jmcneill bus_addr_t addr;
308 1.1 jmcneill bus_size_t size;
309 1.1 jmcneill int i;
310 1.1 jmcneill
311 1.1 jmcneill if (fdtbus_get_reg(sc->sc_phandle, 0, &addr, &size) != 0) {
312 1.1 jmcneill aprint_error(": couldn't get registers\n");
313 1.1 jmcneill return ENXIO;
314 1.1 jmcneill }
315 1.1 jmcneill if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
316 1.1 jmcneill aprint_error(": couldn't map registers\n");
317 1.1 jmcneill return ENXIO;
318 1.1 jmcneill }
319 1.1 jmcneill
320 1.10 jmcneill sc->sc_clkdom.name = device_xname(sc->sc_dev);
321 1.1 jmcneill sc->sc_clkdom.funcs = &sunxi_ccu_clock_funcs;
322 1.1 jmcneill sc->sc_clkdom.priv = sc;
323 1.10 jmcneill for (i = 0; i < sc->sc_nclks; i++) {
324 1.1 jmcneill sc->sc_clks[i].base.domain = &sc->sc_clkdom;
325 1.10 jmcneill clk_attach(&sc->sc_clks[i].base);
326 1.10 jmcneill }
327 1.1 jmcneill
328 1.1 jmcneill fdtbus_register_clock_controller(sc->sc_dev, sc->sc_phandle,
329 1.1 jmcneill &sunxi_ccu_fdtclock_funcs);
330 1.1 jmcneill
331 1.1 jmcneill fdtbus_register_reset_controller(sc->sc_dev, sc->sc_phandle,
332 1.1 jmcneill &sunxi_ccu_fdtreset_funcs);
333 1.1 jmcneill
334 1.1 jmcneill return 0;
335 1.1 jmcneill }
336 1.1 jmcneill
337 1.1 jmcneill void
338 1.1 jmcneill sunxi_ccu_print(struct sunxi_ccu_softc *sc)
339 1.1 jmcneill {
340 1.1 jmcneill struct sunxi_ccu_clk *clk;
341 1.1 jmcneill struct clk *clkp_parent;
342 1.1 jmcneill const char *type;
343 1.1 jmcneill int i;
344 1.1 jmcneill
345 1.1 jmcneill for (i = 0; i < sc->sc_nclks; i++) {
346 1.1 jmcneill clk = &sc->sc_clks[i];
347 1.1 jmcneill if (clk->type == SUNXI_CCU_UNKNOWN)
348 1.1 jmcneill continue;
349 1.1 jmcneill
350 1.1 jmcneill clkp_parent = clk_get_parent(&clk->base);
351 1.1 jmcneill
352 1.1 jmcneill switch (clk->type) {
353 1.7 jmcneill case SUNXI_CCU_GATE: type = "gate"; break;
354 1.7 jmcneill case SUNXI_CCU_NM: type = "nm"; break;
355 1.7 jmcneill case SUNXI_CCU_NKMP: type = "nkmp"; break;
356 1.7 jmcneill case SUNXI_CCU_PREDIV: type = "prediv"; break;
357 1.7 jmcneill case SUNXI_CCU_DIV: type = "div"; break;
358 1.7 jmcneill case SUNXI_CCU_PHASE: type = "phase"; break;
359 1.7 jmcneill case SUNXI_CCU_FIXED_FACTOR: type = "fixed-factor"; break;
360 1.8 bouyer case SUNXI_CCU_FRACTIONAL: type = "fractional"; break;
361 1.7 jmcneill default: type = "???"; break;
362 1.1 jmcneill }
363 1.1 jmcneill
364 1.4 jmcneill aprint_debug_dev(sc->sc_dev,
365 1.5 jmcneill "%3d %-12s %2s %-12s %-7s ",
366 1.4 jmcneill i,
367 1.1 jmcneill clk->base.name,
368 1.1 jmcneill clkp_parent ? "<-" : "",
369 1.1 jmcneill clkp_parent ? clkp_parent->name : "",
370 1.5 jmcneill type);
371 1.5 jmcneill aprint_debug("%10d Hz\n", clk_get_rate(&clk->base));
372 1.1 jmcneill }
373 1.1 jmcneill }
374