Home | History | Annotate | Line # | Download | only in sunxi
sunxi_ccu_nm.c revision 1.3
      1 /* $NetBSD: sunxi_ccu_nm.c,v 1.3 2017/06/29 10:53:59 jmcneill Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca>
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
     21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
     23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     26  * SUCH DAMAGE.
     27  */
     28 
     29 #include <sys/cdefs.h>
     30 __KERNEL_RCSID(0, "$NetBSD: sunxi_ccu_nm.c,v 1.3 2017/06/29 10:53:59 jmcneill Exp $");
     31 
     32 #include <sys/param.h>
     33 #include <sys/bus.h>
     34 
     35 #include <dev/clk/clk_backend.h>
     36 
     37 #include <arm/sunxi/sunxi_ccu.h>
     38 
     39 int
     40 sunxi_ccu_nm_enable(struct sunxi_ccu_softc *sc, struct sunxi_ccu_clk *clk,
     41     int enable)
     42 {
     43 	struct sunxi_ccu_nm *nm = &clk->u.nm;
     44 	uint32_t val;
     45 
     46 	KASSERT(clk->type == SUNXI_CCU_NM);
     47 
     48 	if (!nm->enable)
     49 		return enable ? 0 : EINVAL;
     50 
     51 	val = CCU_READ(sc, nm->reg);
     52 	if (enable)
     53 		val |= nm->enable;
     54 	else
     55 		val &= ~nm->enable;
     56 	CCU_WRITE(sc, nm->reg, val);
     57 
     58 	return 0;
     59 }
     60 
     61 u_int
     62 sunxi_ccu_nm_get_rate(struct sunxi_ccu_softc *sc,
     63     struct sunxi_ccu_clk *clk)
     64 {
     65 	struct sunxi_ccu_nm *nm = &clk->u.nm;
     66 	struct clk *clkp, *clkp_parent;
     67 	u_int rate, n, m;
     68 	uint32_t val;
     69 
     70 	KASSERT(clk->type == SUNXI_CCU_NM);
     71 
     72 	clkp = &clk->base;
     73 	clkp_parent = clk_get_parent(clkp);
     74 	if (clkp_parent == NULL)
     75 		return 0;
     76 
     77 	rate = clk_get_rate(clkp_parent);
     78 	if (rate == 0)
     79 		return 0;
     80 
     81 	val = CCU_READ(sc, nm->reg);
     82 	n = __SHIFTOUT(val, nm->n);
     83 	m = __SHIFTOUT(val, nm->m);
     84 
     85 	if (nm->enable && !(val & nm->enable))
     86 		return 0;
     87 
     88 	if (nm->flags & SUNXI_CCU_NM_POWER_OF_TWO)
     89 		n = 1 << n;
     90 	else
     91 		n++;
     92 
     93 	m++;
     94 
     95 	return rate / n / m;
     96 }
     97 
     98 int
     99 sunxi_ccu_nm_set_rate(struct sunxi_ccu_softc *sc,
    100     struct sunxi_ccu_clk *clk, u_int new_rate)
    101 {
    102 	struct sunxi_ccu_nm *nm = &clk->u.nm;
    103 	struct clk *clkp, *clkp_parent;
    104 	u_int parent_rate, best_rate, best_n, best_m, best_parent;
    105 	u_int n, m, pindex, rate;
    106 	int best_diff;
    107 	uint32_t val;
    108 
    109 	const u_int n_max = __SHIFTOUT(nm->n, nm->n);
    110 	const u_int m_max = __SHIFTOUT(nm->m, nm->m);
    111 
    112 	clkp = &clk->base;
    113 	clkp_parent = clk_get_parent(clkp);
    114 	if (clkp_parent == NULL)
    115 		return 0;
    116 
    117 	rate = clk_get_rate(clkp_parent);
    118 	if (rate == 0)
    119 		return 0;
    120 
    121 	best_rate = 0;
    122 	best_diff = INT_MAX;
    123 	for (pindex = 0; pindex < nm->nparents; pindex++) {
    124 		/* XXX
    125 		 * Shouldn't have to set parent to get potential parent clock rate
    126 		 */
    127 		val = CCU_READ(sc, nm->reg);
    128 		val &= ~nm->sel;
    129 		val |= __SHIFTIN(pindex, nm->sel);
    130 		CCU_WRITE(sc, nm->reg, val);
    131 
    132 		clkp_parent = clk_get_parent(clkp);
    133 		if (clkp_parent == NULL)
    134 			continue;
    135 		parent_rate = clk_get_rate(clkp_parent);
    136 		if (parent_rate == 0)
    137 			continue;
    138 
    139 		for (n = 0; n <= n_max; n++) {
    140 			for (m = 0; m <= m_max; m++) {
    141 				if (nm->flags & SUNXI_CCU_NM_POWER_OF_TWO)
    142 					rate = parent_rate / (1 << n) / (m + 1);
    143 				else
    144 					rate = parent_rate / (n + 1) / (m + 1);
    145 
    146 				if (nm->flags & SUNXI_CCU_NM_ROUND_DOWN) {
    147 					const int diff = new_rate - rate;
    148 					if (diff >= 0 && rate > best_rate) {
    149 						best_diff = diff;
    150 						best_rate = rate;
    151 						best_n = n;
    152 						best_m = m;
    153 						best_parent = pindex;
    154 					}
    155 				} else {
    156 					const int diff = abs(new_rate - rate);
    157 					if (diff < best_diff) {
    158 						best_diff = diff;
    159 						best_rate = rate;
    160 						best_n = n;
    161 						best_m = m;
    162 						best_parent = pindex;
    163 					}
    164 				}
    165 			}
    166 		}
    167 	}
    168 
    169 	if (best_rate == 0)
    170 		return ERANGE;
    171 
    172 	val = CCU_READ(sc, nm->reg);
    173 	val &= ~nm->sel;
    174 	val |= __SHIFTIN(best_parent, nm->sel);
    175 	val &= ~nm->n;
    176 	val |= __SHIFTIN(best_n, nm->n);
    177 	val &= ~nm->m;
    178 	val |= __SHIFTIN(best_m, nm->m);
    179 	CCU_WRITE(sc, nm->reg, val);
    180 
    181 	return 0;
    182 }
    183 
    184 int
    185 sunxi_ccu_nm_set_parent(struct sunxi_ccu_softc *sc,
    186     struct sunxi_ccu_clk *clk, const char *name)
    187 {
    188 	struct sunxi_ccu_nm *nm = &clk->u.nm;
    189 	uint32_t val;
    190 	u_int index;
    191 
    192 	KASSERT(clk->type == SUNXI_CCU_NM);
    193 
    194 	if (nm->sel == 0)
    195 		return ENODEV;
    196 
    197 	for (index = 0; index < nm->nparents; index++) {
    198 		if (nm->parents[index] != NULL &&
    199 		    strcmp(nm->parents[index], name) == 0)
    200 			break;
    201 	}
    202 	if (index == nm->nparents)
    203 		return EINVAL;
    204 
    205 	val = CCU_READ(sc, nm->reg);
    206 	val &= ~nm->sel;
    207 	val |= __SHIFTIN(index, nm->sel);
    208 	CCU_WRITE(sc, nm->reg, val);
    209 
    210 	return 0;
    211 }
    212 
    213 const char *
    214 sunxi_ccu_nm_get_parent(struct sunxi_ccu_softc *sc,
    215     struct sunxi_ccu_clk *clk)
    216 {
    217 	struct sunxi_ccu_nm *nm = &clk->u.nm;
    218 	u_int index;
    219 	uint32_t val;
    220 
    221 	KASSERT(clk->type == SUNXI_CCU_NM);
    222 
    223 	val = CCU_READ(sc, nm->reg);
    224 	index = __SHIFTOUT(val, nm->sel);
    225 
    226 	return nm->parents[index];
    227 }
    228