sunxi_codec.c revision 1.2.2.2
1 1.2.2.2 skrll /* $NetBSD: sunxi_codec.c,v 1.2.2.2 2017/08/28 17:51:32 skrll Exp $ */ 2 1.2.2.2 skrll 3 1.2.2.2 skrll /*- 4 1.2.2.2 skrll * Copyright (c) 2014-2017 Jared McNeill <jmcneill (at) invisible.ca> 5 1.2.2.2 skrll * All rights reserved. 6 1.2.2.2 skrll * 7 1.2.2.2 skrll * Redistribution and use in source and binary forms, with or without 8 1.2.2.2 skrll * modification, are permitted provided that the following conditions 9 1.2.2.2 skrll * are met: 10 1.2.2.2 skrll * 1. Redistributions of source code must retain the above copyright 11 1.2.2.2 skrll * notice, this list of conditions and the following disclaimer. 12 1.2.2.2 skrll * 2. Redistributions in binary form must reproduce the above copyright 13 1.2.2.2 skrll * notice, this list of conditions and the following disclaimer in the 14 1.2.2.2 skrll * documentation and/or other materials provided with the distribution. 15 1.2.2.2 skrll * 16 1.2.2.2 skrll * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 1.2.2.2 skrll * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 1.2.2.2 skrll * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 1.2.2.2 skrll * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 1.2.2.2 skrll * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 1.2.2.2 skrll * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 1.2.2.2 skrll * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 1.2.2.2 skrll * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 1.2.2.2 skrll * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 1.2.2.2 skrll * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 1.2.2.2 skrll * SUCH DAMAGE. 27 1.2.2.2 skrll */ 28 1.2.2.2 skrll 29 1.2.2.2 skrll #include "opt_ddb.h" 30 1.2.2.2 skrll 31 1.2.2.2 skrll #include <sys/cdefs.h> 32 1.2.2.2 skrll __KERNEL_RCSID(0, "$NetBSD: sunxi_codec.c,v 1.2.2.2 2017/08/28 17:51:32 skrll Exp $"); 33 1.2.2.2 skrll 34 1.2.2.2 skrll #include <sys/param.h> 35 1.2.2.2 skrll #include <sys/bus.h> 36 1.2.2.2 skrll #include <sys/cpu.h> 37 1.2.2.2 skrll #include <sys/device.h> 38 1.2.2.2 skrll #include <sys/kmem.h> 39 1.2.2.2 skrll #include <sys/gpio.h> 40 1.2.2.2 skrll 41 1.2.2.2 skrll #include <sys/audioio.h> 42 1.2.2.2 skrll #include <dev/audio_if.h> 43 1.2.2.2 skrll #include <dev/auconv.h> 44 1.2.2.2 skrll 45 1.2.2.2 skrll #include <dev/fdt/fdtvar.h> 46 1.2.2.2 skrll 47 1.2.2.2 skrll #include <arm/sunxi/sunxi_codec.h> 48 1.2.2.2 skrll 49 1.2.2.2 skrll #define TX_TRIG_LEVEL 0xf 50 1.2.2.2 skrll #define RX_TRIG_LEVEL 0x7 51 1.2.2.2 skrll #define DRQ_CLR_CNT 0x3 52 1.2.2.2 skrll 53 1.2.2.2 skrll #define AC_DAC_DPC(_sc) ((_sc)->sc_cfg->DPC) 54 1.2.2.2 skrll #define DAC_DPC_EN_DA 0x80000000 55 1.2.2.2 skrll #define AC_DAC_FIFOC(_sc) ((_sc)->sc_cfg->DAC_FIFOC) 56 1.2.2.2 skrll #define DAC_FIFOC_FS __BITS(31,29) 57 1.2.2.2 skrll #define DAC_FS_48KHZ 0 58 1.2.2.2 skrll #define DAC_FS_32KHZ 1 59 1.2.2.2 skrll #define DAC_FS_24KHZ 2 60 1.2.2.2 skrll #define DAC_FS_16KHZ 3 61 1.2.2.2 skrll #define DAC_FS_12KHZ 4 62 1.2.2.2 skrll #define DAC_FS_8KHZ 5 63 1.2.2.2 skrll #define DAC_FS_192KHZ 6 64 1.2.2.2 skrll #define DAC_FS_96KHZ 7 65 1.2.2.2 skrll #define DAC_FIFOC_FIFO_MODE __BITS(25,24) 66 1.2.2.2 skrll #define FIFO_MODE_24_31_8 0 67 1.2.2.2 skrll #define FIFO_MODE_16_31_16 0 68 1.2.2.2 skrll #define FIFO_MODE_16_15_0 1 69 1.2.2.2 skrll #define DAC_FIFOC_DRQ_CLR_CNT __BITS(22,21) 70 1.2.2.2 skrll #define DAC_FIFOC_TX_TRIG_LEVEL __BITS(14,8) 71 1.2.2.2 skrll #define DAC_FIFOC_MONO_EN __BIT(6) 72 1.2.2.2 skrll #define DAC_FIFOC_TX_BITS __BIT(5) 73 1.2.2.2 skrll #define DAC_FIFOC_DRQ_EN __BIT(4) 74 1.2.2.2 skrll #define DAC_FIFOC_FIFO_FLUSH __BIT(0) 75 1.2.2.2 skrll #define AC_DAC_FIFOS(_sc) ((_sc)->sc_cfg->DAC_FIFOS) 76 1.2.2.2 skrll #define AC_DAC_TXDATA(_sc) ((_sc)->sc_cfg->DAC_TXDATA) 77 1.2.2.2 skrll #define AC_ADC_FIFOC(_sc) ((_sc)->sc_cfg->ADC_FIFOC) 78 1.2.2.2 skrll #define ADC_FIFOC_FS __BITS(31,29) 79 1.2.2.2 skrll #define ADC_FS_48KHZ 0 80 1.2.2.2 skrll #define ADC_FIFOC_EN_AD __BIT(28) 81 1.2.2.2 skrll #define ADC_FIFOC_RX_FIFO_MODE __BIT(24) 82 1.2.2.2 skrll #define ADC_FIFOC_RX_TRIG_LEVEL __BITS(12,8) 83 1.2.2.2 skrll #define ADC_FIFOC_MONO_EN __BIT(7) 84 1.2.2.2 skrll #define ADC_FIFOC_RX_BITS __BIT(6) 85 1.2.2.2 skrll #define ADC_FIFOC_DRQ_EN __BIT(4) 86 1.2.2.2 skrll #define ADC_FIFOC_FIFO_FLUSH __BIT(0) 87 1.2.2.2 skrll #define AC_ADC_FIFOS(_sc) ((_sc)->sc_cfg->ADC_FIFOS) 88 1.2.2.2 skrll #define AC_ADC_RXDATA(_sc) ((_sc)->sc_cfg->ADC_RXDATA) 89 1.2.2.2 skrll #define AC_DAC_CNT(_sc) ((_sc)->sc_cfg->DAC_CNT) 90 1.2.2.2 skrll #define AC_ADC_CNT(_sc) ((_sc)->sc_cfg->ADC_CNT) 91 1.2.2.2 skrll 92 1.2.2.2 skrll static const struct of_compat_data compat_data[] = { 93 1.2.2.2 skrll H3_CODEC_COMPATDATA, 94 1.2.2.2 skrll { NULL } 95 1.2.2.2 skrll }; 96 1.2.2.2 skrll 97 1.2.2.2 skrll #define CODEC_READ(sc, reg) \ 98 1.2.2.2 skrll bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 99 1.2.2.2 skrll #define CODEC_WRITE(sc, reg, val) \ 100 1.2.2.2 skrll bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 101 1.2.2.2 skrll 102 1.2.2.2 skrll static int 103 1.2.2.2 skrll sunxi_codec_allocdma(struct sunxi_codec_softc *sc, size_t size, 104 1.2.2.2 skrll size_t align, struct sunxi_codec_dma *dma) 105 1.2.2.2 skrll { 106 1.2.2.2 skrll int error; 107 1.2.2.2 skrll 108 1.2.2.2 skrll dma->dma_size = size; 109 1.2.2.2 skrll error = bus_dmamem_alloc(sc->sc_dmat, dma->dma_size, align, 0, 110 1.2.2.2 skrll dma->dma_segs, 1, &dma->dma_nsegs, BUS_DMA_WAITOK); 111 1.2.2.2 skrll if (error) 112 1.2.2.2 skrll return error; 113 1.2.2.2 skrll 114 1.2.2.2 skrll error = bus_dmamem_map(sc->sc_dmat, dma->dma_segs, dma->dma_nsegs, 115 1.2.2.2 skrll dma->dma_size, &dma->dma_addr, BUS_DMA_WAITOK | BUS_DMA_COHERENT); 116 1.2.2.2 skrll if (error) 117 1.2.2.2 skrll goto free; 118 1.2.2.2 skrll 119 1.2.2.2 skrll error = bus_dmamap_create(sc->sc_dmat, dma->dma_size, dma->dma_nsegs, 120 1.2.2.2 skrll dma->dma_size, 0, BUS_DMA_WAITOK, &dma->dma_map); 121 1.2.2.2 skrll if (error) 122 1.2.2.2 skrll goto unmap; 123 1.2.2.2 skrll 124 1.2.2.2 skrll error = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_addr, 125 1.2.2.2 skrll dma->dma_size, NULL, BUS_DMA_WAITOK); 126 1.2.2.2 skrll if (error) 127 1.2.2.2 skrll goto destroy; 128 1.2.2.2 skrll 129 1.2.2.2 skrll return 0; 130 1.2.2.2 skrll 131 1.2.2.2 skrll destroy: 132 1.2.2.2 skrll bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 133 1.2.2.2 skrll unmap: 134 1.2.2.2 skrll bus_dmamem_unmap(sc->sc_dmat, dma->dma_addr, dma->dma_size); 135 1.2.2.2 skrll free: 136 1.2.2.2 skrll bus_dmamem_free(sc->sc_dmat, dma->dma_segs, dma->dma_nsegs); 137 1.2.2.2 skrll 138 1.2.2.2 skrll return error; 139 1.2.2.2 skrll } 140 1.2.2.2 skrll 141 1.2.2.2 skrll static void 142 1.2.2.2 skrll sunxi_codec_freedma(struct sunxi_codec_softc *sc, struct sunxi_codec_dma *dma) 143 1.2.2.2 skrll { 144 1.2.2.2 skrll bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 145 1.2.2.2 skrll bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 146 1.2.2.2 skrll bus_dmamem_unmap(sc->sc_dmat, dma->dma_addr, dma->dma_size); 147 1.2.2.2 skrll bus_dmamem_free(sc->sc_dmat, dma->dma_segs, dma->dma_nsegs); 148 1.2.2.2 skrll } 149 1.2.2.2 skrll 150 1.2.2.2 skrll static int 151 1.2.2.2 skrll sunxi_codec_transfer(struct sunxi_codec_chan *ch) 152 1.2.2.2 skrll { 153 1.2.2.2 skrll bus_dma_segment_t seg; 154 1.2.2.2 skrll 155 1.2.2.2 skrll seg.ds_addr = ch->ch_cur_phys; 156 1.2.2.2 skrll seg.ds_len = ch->ch_blksize; 157 1.2.2.2 skrll ch->ch_req.dreq_segs = &seg; 158 1.2.2.2 skrll ch->ch_req.dreq_nsegs = 1; 159 1.2.2.2 skrll 160 1.2.2.2 skrll return fdtbus_dma_transfer(ch->ch_dma, &ch->ch_req); 161 1.2.2.2 skrll } 162 1.2.2.2 skrll 163 1.2.2.2 skrll static int 164 1.2.2.2 skrll sunxi_codec_open(void *priv, int flags) 165 1.2.2.2 skrll { 166 1.2.2.2 skrll return 0; 167 1.2.2.2 skrll } 168 1.2.2.2 skrll 169 1.2.2.2 skrll static void 170 1.2.2.2 skrll sunxi_codec_close(void *priv) 171 1.2.2.2 skrll { 172 1.2.2.2 skrll } 173 1.2.2.2 skrll 174 1.2.2.2 skrll static int 175 1.2.2.2 skrll sunxi_codec_drain(void *priv) 176 1.2.2.2 skrll { 177 1.2.2.2 skrll struct sunxi_codec_softc * const sc = priv; 178 1.2.2.2 skrll uint32_t val; 179 1.2.2.2 skrll 180 1.2.2.2 skrll val = CODEC_READ(sc, AC_DAC_FIFOC(sc)); 181 1.2.2.2 skrll CODEC_WRITE(sc, AC_DAC_FIFOC(sc), val | DAC_FIFOC_FIFO_FLUSH); 182 1.2.2.2 skrll 183 1.2.2.2 skrll val = CODEC_READ(sc, AC_ADC_FIFOC(sc)); 184 1.2.2.2 skrll CODEC_WRITE(sc, AC_ADC_FIFOC(sc), val | ADC_FIFOC_FIFO_FLUSH); 185 1.2.2.2 skrll 186 1.2.2.2 skrll return 0; 187 1.2.2.2 skrll } 188 1.2.2.2 skrll 189 1.2.2.2 skrll static int 190 1.2.2.2 skrll sunxi_codec_query_encoding(void *priv, struct audio_encoding *ae) 191 1.2.2.2 skrll { 192 1.2.2.2 skrll struct sunxi_codec_softc * const sc = priv; 193 1.2.2.2 skrll 194 1.2.2.2 skrll return auconv_query_encoding(sc->sc_encodings, ae); 195 1.2.2.2 skrll } 196 1.2.2.2 skrll 197 1.2.2.2 skrll static int 198 1.2.2.2 skrll sunxi_codec_set_params(void *priv, int setmode, int usemode, 199 1.2.2.2 skrll audio_params_t *play, audio_params_t *rec, 200 1.2.2.2 skrll stream_filter_list_t *pfil, stream_filter_list_t *rfil) 201 1.2.2.2 skrll { 202 1.2.2.2 skrll struct sunxi_codec_softc * const sc = priv; 203 1.2.2.2 skrll int index; 204 1.2.2.2 skrll 205 1.2.2.2 skrll if (play && (setmode & AUMODE_PLAY)) { 206 1.2.2.2 skrll index = auconv_set_converter(&sc->sc_format, 1, 207 1.2.2.2 skrll AUMODE_PLAY, play, true, pfil); 208 1.2.2.2 skrll if (index < 0) 209 1.2.2.2 skrll return EINVAL; 210 1.2.2.2 skrll sc->sc_pchan.ch_params = pfil->req_size > 0 ? 211 1.2.2.2 skrll pfil->filters[0].param : *play; 212 1.2.2.2 skrll } 213 1.2.2.2 skrll if (rec && (setmode & AUMODE_RECORD)) { 214 1.2.2.2 skrll index = auconv_set_converter(&sc->sc_format, 1, 215 1.2.2.2 skrll AUMODE_RECORD, rec, true, rfil); 216 1.2.2.2 skrll if (index < 0) 217 1.2.2.2 skrll return EINVAL; 218 1.2.2.2 skrll sc->sc_rchan.ch_params = rfil->req_size > 0 ? 219 1.2.2.2 skrll rfil->filters[0].param : *rec; 220 1.2.2.2 skrll } 221 1.2.2.2 skrll 222 1.2.2.2 skrll return 0; 223 1.2.2.2 skrll } 224 1.2.2.2 skrll 225 1.2.2.2 skrll static int 226 1.2.2.2 skrll sunxi_codec_set_port(void *priv, mixer_ctrl_t *mc) 227 1.2.2.2 skrll { 228 1.2.2.2 skrll struct sunxi_codec_softc * const sc = priv; 229 1.2.2.2 skrll 230 1.2.2.2 skrll return sc->sc_cfg->set_port(sc, mc); 231 1.2.2.2 skrll } 232 1.2.2.2 skrll 233 1.2.2.2 skrll static int 234 1.2.2.2 skrll sunxi_codec_get_port(void *priv, mixer_ctrl_t *mc) 235 1.2.2.2 skrll { 236 1.2.2.2 skrll struct sunxi_codec_softc * const sc = priv; 237 1.2.2.2 skrll 238 1.2.2.2 skrll return sc->sc_cfg->get_port(sc, mc); 239 1.2.2.2 skrll } 240 1.2.2.2 skrll 241 1.2.2.2 skrll static int 242 1.2.2.2 skrll sunxi_codec_query_devinfo(void *priv, mixer_devinfo_t *di) 243 1.2.2.2 skrll { 244 1.2.2.2 skrll struct sunxi_codec_softc * const sc = priv; 245 1.2.2.2 skrll 246 1.2.2.2 skrll return sc->sc_cfg->query_devinfo(sc, di); 247 1.2.2.2 skrll } 248 1.2.2.2 skrll 249 1.2.2.2 skrll static void * 250 1.2.2.2 skrll sunxi_codec_allocm(void *priv, int dir, size_t size) 251 1.2.2.2 skrll { 252 1.2.2.2 skrll struct sunxi_codec_softc * const sc = priv; 253 1.2.2.2 skrll struct sunxi_codec_dma *dma; 254 1.2.2.2 skrll int error; 255 1.2.2.2 skrll 256 1.2.2.2 skrll dma = kmem_alloc(sizeof(*dma), KM_SLEEP); 257 1.2.2.2 skrll 258 1.2.2.2 skrll error = sunxi_codec_allocdma(sc, size, 16, dma); 259 1.2.2.2 skrll if (error) { 260 1.2.2.2 skrll kmem_free(dma, sizeof(*dma)); 261 1.2.2.2 skrll device_printf(sc->sc_dev, "couldn't allocate DMA memory (%d)\n", 262 1.2.2.2 skrll error); 263 1.2.2.2 skrll return NULL; 264 1.2.2.2 skrll } 265 1.2.2.2 skrll 266 1.2.2.2 skrll LIST_INSERT_HEAD(&sc->sc_dmalist, dma, dma_list); 267 1.2.2.2 skrll 268 1.2.2.2 skrll return dma->dma_addr; 269 1.2.2.2 skrll } 270 1.2.2.2 skrll 271 1.2.2.2 skrll static void 272 1.2.2.2 skrll sunxi_codec_freem(void *priv, void *addr, size_t size) 273 1.2.2.2 skrll { 274 1.2.2.2 skrll struct sunxi_codec_softc * const sc = priv; 275 1.2.2.2 skrll struct sunxi_codec_dma *dma; 276 1.2.2.2 skrll 277 1.2.2.2 skrll LIST_FOREACH(dma, &sc->sc_dmalist, dma_list) 278 1.2.2.2 skrll if (dma->dma_addr == addr) { 279 1.2.2.2 skrll sunxi_codec_freedma(sc, dma); 280 1.2.2.2 skrll LIST_REMOVE(dma, dma_list); 281 1.2.2.2 skrll kmem_free(dma, sizeof(*dma)); 282 1.2.2.2 skrll break; 283 1.2.2.2 skrll } 284 1.2.2.2 skrll } 285 1.2.2.2 skrll 286 1.2.2.2 skrll static paddr_t 287 1.2.2.2 skrll sunxi_codec_mappage(void *priv, void *addr, off_t off, int prot) 288 1.2.2.2 skrll { 289 1.2.2.2 skrll struct sunxi_codec_softc * const sc = priv; 290 1.2.2.2 skrll struct sunxi_codec_dma *dma; 291 1.2.2.2 skrll 292 1.2.2.2 skrll if (off < 0) 293 1.2.2.2 skrll return -1; 294 1.2.2.2 skrll 295 1.2.2.2 skrll LIST_FOREACH(dma, &sc->sc_dmalist, dma_list) 296 1.2.2.2 skrll if (dma->dma_addr == addr) { 297 1.2.2.2 skrll return bus_dmamem_mmap(sc->sc_dmat, dma->dma_segs, 298 1.2.2.2 skrll dma->dma_nsegs, off, prot, BUS_DMA_WAITOK); 299 1.2.2.2 skrll } 300 1.2.2.2 skrll 301 1.2.2.2 skrll return -1; 302 1.2.2.2 skrll } 303 1.2.2.2 skrll 304 1.2.2.2 skrll static int 305 1.2.2.2 skrll sunxi_codec_getdev(void *priv, struct audio_device *adev) 306 1.2.2.2 skrll { 307 1.2.2.2 skrll struct sunxi_codec_softc * const sc = priv; 308 1.2.2.2 skrll 309 1.2.2.2 skrll snprintf(adev->name, sizeof(adev->name), "Allwinner"); 310 1.2.2.2 skrll snprintf(adev->version, sizeof(adev->version), "%s", 311 1.2.2.2 skrll sc->sc_cfg->name); 312 1.2.2.2 skrll snprintf(adev->config, sizeof(adev->config), "sunxicodec"); 313 1.2.2.2 skrll 314 1.2.2.2 skrll return 0; 315 1.2.2.2 skrll } 316 1.2.2.2 skrll 317 1.2.2.2 skrll static int 318 1.2.2.2 skrll sunxi_codec_get_props(void *priv) 319 1.2.2.2 skrll { 320 1.2.2.2 skrll return AUDIO_PROP_PLAYBACK|AUDIO_PROP_CAPTURE| 321 1.2.2.2 skrll AUDIO_PROP_INDEPENDENT|AUDIO_PROP_MMAP| 322 1.2.2.2 skrll AUDIO_PROP_FULLDUPLEX; 323 1.2.2.2 skrll } 324 1.2.2.2 skrll 325 1.2.2.2 skrll static int 326 1.2.2.2 skrll sunxi_codec_round_blocksize(void *priv, int bs, int mode, 327 1.2.2.2 skrll const audio_params_t *params) 328 1.2.2.2 skrll { 329 1.2.2.2 skrll bs &= ~3; 330 1.2.2.2 skrll if (bs == 0) 331 1.2.2.2 skrll bs = 4; 332 1.2.2.2 skrll return bs; 333 1.2.2.2 skrll } 334 1.2.2.2 skrll 335 1.2.2.2 skrll static size_t 336 1.2.2.2 skrll sunxi_codec_round_buffersize(void *priv, int dir, size_t bufsize) 337 1.2.2.2 skrll { 338 1.2.2.2 skrll return bufsize; 339 1.2.2.2 skrll } 340 1.2.2.2 skrll 341 1.2.2.2 skrll static int 342 1.2.2.2 skrll sunxi_codec_trigger_output(void *priv, void *start, void *end, int blksize, 343 1.2.2.2 skrll void (*intr)(void *), void *intrarg, const audio_params_t *params) 344 1.2.2.2 skrll { 345 1.2.2.2 skrll struct sunxi_codec_softc * const sc = priv; 346 1.2.2.2 skrll struct sunxi_codec_chan *ch = &sc->sc_pchan; 347 1.2.2.2 skrll struct sunxi_codec_dma *dma; 348 1.2.2.2 skrll bus_addr_t pstart; 349 1.2.2.2 skrll bus_size_t psize; 350 1.2.2.2 skrll uint32_t val; 351 1.2.2.2 skrll int error; 352 1.2.2.2 skrll 353 1.2.2.2 skrll pstart = 0; 354 1.2.2.2 skrll psize = (uintptr_t)end - (uintptr_t)start; 355 1.2.2.2 skrll 356 1.2.2.2 skrll LIST_FOREACH(dma, &sc->sc_dmalist, dma_list) 357 1.2.2.2 skrll if (dma->dma_addr == start) { 358 1.2.2.2 skrll pstart = dma->dma_map->dm_segs[0].ds_addr; 359 1.2.2.2 skrll break; 360 1.2.2.2 skrll } 361 1.2.2.2 skrll if (pstart == 0) { 362 1.2.2.2 skrll device_printf(sc->sc_dev, "bad addr %p\n", start); 363 1.2.2.2 skrll return EINVAL; 364 1.2.2.2 skrll } 365 1.2.2.2 skrll 366 1.2.2.2 skrll ch->ch_intr = intr; 367 1.2.2.2 skrll ch->ch_intrarg = intrarg; 368 1.2.2.2 skrll ch->ch_start_phys = ch->ch_cur_phys = pstart; 369 1.2.2.2 skrll ch->ch_end_phys = pstart + psize; 370 1.2.2.2 skrll ch->ch_blksize = blksize; 371 1.2.2.2 skrll 372 1.2.2.2 skrll /* Flush DAC FIFO */ 373 1.2.2.2 skrll val = CODEC_READ(sc, AC_DAC_FIFOC(sc)); 374 1.2.2.2 skrll CODEC_WRITE(sc, AC_DAC_FIFOC(sc), val | DAC_FIFOC_FIFO_FLUSH); 375 1.2.2.2 skrll 376 1.2.2.2 skrll /* Clear DAC FIFO status */ 377 1.2.2.2 skrll val = CODEC_READ(sc, AC_DAC_FIFOS(sc)); 378 1.2.2.2 skrll CODEC_WRITE(sc, AC_DAC_FIFOS(sc), val); 379 1.2.2.2 skrll 380 1.2.2.2 skrll /* Unmute output */ 381 1.2.2.2 skrll if (sc->sc_cfg->mute) 382 1.2.2.2 skrll sc->sc_cfg->mute(sc, 0, ch->ch_mode); 383 1.2.2.2 skrll 384 1.2.2.2 skrll /* Configure DAC FIFO */ 385 1.2.2.2 skrll CODEC_WRITE(sc, AC_DAC_FIFOC(sc), 386 1.2.2.2 skrll __SHIFTIN(DAC_FS_48KHZ, DAC_FIFOC_FS) | 387 1.2.2.2 skrll __SHIFTIN(FIFO_MODE_16_15_0, DAC_FIFOC_FIFO_MODE) | 388 1.2.2.2 skrll __SHIFTIN(DRQ_CLR_CNT, DAC_FIFOC_DRQ_CLR_CNT) | 389 1.2.2.2 skrll __SHIFTIN(TX_TRIG_LEVEL, DAC_FIFOC_TX_TRIG_LEVEL)); 390 1.2.2.2 skrll 391 1.2.2.2 skrll /* Enable DAC DRQ */ 392 1.2.2.2 skrll val = CODEC_READ(sc, AC_DAC_FIFOC(sc)); 393 1.2.2.2 skrll CODEC_WRITE(sc, AC_DAC_FIFOC(sc), val | DAC_FIFOC_DRQ_EN); 394 1.2.2.2 skrll 395 1.2.2.2 skrll /* Start DMA transfer */ 396 1.2.2.2 skrll error = sunxi_codec_transfer(ch); 397 1.2.2.2 skrll if (error != 0) { 398 1.2.2.2 skrll aprint_error_dev(sc->sc_dev, 399 1.2.2.2 skrll "failed to start DMA transfer: %d\n", error); 400 1.2.2.2 skrll return error; 401 1.2.2.2 skrll } 402 1.2.2.2 skrll 403 1.2.2.2 skrll return 0; 404 1.2.2.2 skrll } 405 1.2.2.2 skrll 406 1.2.2.2 skrll static int 407 1.2.2.2 skrll sunxi_codec_trigger_input(void *priv, void *start, void *end, int blksize, 408 1.2.2.2 skrll void (*intr)(void *), void *intrarg, const audio_params_t *params) 409 1.2.2.2 skrll { 410 1.2.2.2 skrll struct sunxi_codec_softc * const sc = priv; 411 1.2.2.2 skrll struct sunxi_codec_chan *ch = &sc->sc_rchan; 412 1.2.2.2 skrll struct sunxi_codec_dma *dma; 413 1.2.2.2 skrll bus_addr_t pstart; 414 1.2.2.2 skrll bus_size_t psize; 415 1.2.2.2 skrll uint32_t val; 416 1.2.2.2 skrll int error; 417 1.2.2.2 skrll 418 1.2.2.2 skrll pstart = 0; 419 1.2.2.2 skrll psize = (uintptr_t)end - (uintptr_t)start; 420 1.2.2.2 skrll 421 1.2.2.2 skrll LIST_FOREACH(dma, &sc->sc_dmalist, dma_list) 422 1.2.2.2 skrll if (dma->dma_addr == start) { 423 1.2.2.2 skrll pstart = dma->dma_map->dm_segs[0].ds_addr; 424 1.2.2.2 skrll break; 425 1.2.2.2 skrll } 426 1.2.2.2 skrll if (pstart == 0) { 427 1.2.2.2 skrll device_printf(sc->sc_dev, "bad addr %p\n", start); 428 1.2.2.2 skrll return EINVAL; 429 1.2.2.2 skrll } 430 1.2.2.2 skrll 431 1.2.2.2 skrll ch->ch_intr = intr; 432 1.2.2.2 skrll ch->ch_intrarg = intrarg; 433 1.2.2.2 skrll ch->ch_start_phys = ch->ch_cur_phys = pstart; 434 1.2.2.2 skrll ch->ch_end_phys = pstart + psize; 435 1.2.2.2 skrll ch->ch_blksize = blksize; 436 1.2.2.2 skrll 437 1.2.2.2 skrll /* Flush ADC FIFO */ 438 1.2.2.2 skrll val = CODEC_READ(sc, AC_ADC_FIFOC(sc)); 439 1.2.2.2 skrll CODEC_WRITE(sc, AC_ADC_FIFOC(sc), val | ADC_FIFOC_FIFO_FLUSH); 440 1.2.2.2 skrll 441 1.2.2.2 skrll /* Clear ADC FIFO status */ 442 1.2.2.2 skrll val = CODEC_READ(sc, AC_ADC_FIFOS(sc)); 443 1.2.2.2 skrll CODEC_WRITE(sc, AC_ADC_FIFOS(sc), val); 444 1.2.2.2 skrll 445 1.2.2.2 skrll /* Unmute input */ 446 1.2.2.2 skrll if (sc->sc_cfg->mute) 447 1.2.2.2 skrll sc->sc_cfg->mute(sc, 0, ch->ch_mode); 448 1.2.2.2 skrll 449 1.2.2.2 skrll /* Configure ADC FIFO */ 450 1.2.2.2 skrll CODEC_WRITE(sc, AC_ADC_FIFOC(sc), 451 1.2.2.2 skrll __SHIFTIN(ADC_FS_48KHZ, ADC_FIFOC_FS) | 452 1.2.2.2 skrll __SHIFTIN(RX_TRIG_LEVEL, ADC_FIFOC_RX_TRIG_LEVEL) | 453 1.2.2.2 skrll ADC_FIFOC_EN_AD | ADC_FIFOC_RX_FIFO_MODE); 454 1.2.2.2 skrll 455 1.2.2.2 skrll /* Enable ADC DRQ */ 456 1.2.2.2 skrll val = CODEC_READ(sc, AC_ADC_FIFOC(sc)); 457 1.2.2.2 skrll CODEC_WRITE(sc, AC_ADC_FIFOC(sc), val | ADC_FIFOC_DRQ_EN); 458 1.2.2.2 skrll 459 1.2.2.2 skrll /* Start DMA transfer */ 460 1.2.2.2 skrll error = sunxi_codec_transfer(ch); 461 1.2.2.2 skrll if (error != 0) { 462 1.2.2.2 skrll aprint_error_dev(sc->sc_dev, 463 1.2.2.2 skrll "failed to start DMA transfer: %d\n", error); 464 1.2.2.2 skrll return error; 465 1.2.2.2 skrll } 466 1.2.2.2 skrll 467 1.2.2.2 skrll return 0; 468 1.2.2.2 skrll } 469 1.2.2.2 skrll 470 1.2.2.2 skrll static int 471 1.2.2.2 skrll sunxi_codec_halt_output(void *priv) 472 1.2.2.2 skrll { 473 1.2.2.2 skrll struct sunxi_codec_softc * const sc = priv; 474 1.2.2.2 skrll struct sunxi_codec_chan *ch = &sc->sc_pchan; 475 1.2.2.2 skrll uint32_t val; 476 1.2.2.2 skrll 477 1.2.2.2 skrll /* Disable DMA channel */ 478 1.2.2.2 skrll fdtbus_dma_halt(ch->ch_dma); 479 1.2.2.2 skrll 480 1.2.2.2 skrll /* Mute output */ 481 1.2.2.2 skrll if (sc->sc_cfg->mute) 482 1.2.2.2 skrll sc->sc_cfg->mute(sc, 1, ch->ch_mode); 483 1.2.2.2 skrll 484 1.2.2.2 skrll /* Disable DAC DRQ */ 485 1.2.2.2 skrll val = CODEC_READ(sc, AC_DAC_FIFOC(sc)); 486 1.2.2.2 skrll CODEC_WRITE(sc, AC_DAC_FIFOC(sc), val & ~DAC_FIFOC_DRQ_EN); 487 1.2.2.2 skrll 488 1.2.2.2 skrll ch->ch_intr = NULL; 489 1.2.2.2 skrll ch->ch_intrarg = NULL; 490 1.2.2.2 skrll 491 1.2.2.2 skrll return 0; 492 1.2.2.2 skrll } 493 1.2.2.2 skrll 494 1.2.2.2 skrll static int 495 1.2.2.2 skrll sunxi_codec_halt_input(void *priv) 496 1.2.2.2 skrll { 497 1.2.2.2 skrll struct sunxi_codec_softc * const sc = priv; 498 1.2.2.2 skrll struct sunxi_codec_chan *ch = &sc->sc_rchan; 499 1.2.2.2 skrll uint32_t val; 500 1.2.2.2 skrll 501 1.2.2.2 skrll /* Disable DMA channel */ 502 1.2.2.2 skrll fdtbus_dma_halt(ch->ch_dma); 503 1.2.2.2 skrll 504 1.2.2.2 skrll /* Mute output */ 505 1.2.2.2 skrll if (sc->sc_cfg->mute) 506 1.2.2.2 skrll sc->sc_cfg->mute(sc, 1, ch->ch_mode); 507 1.2.2.2 skrll 508 1.2.2.2 skrll /* Disable ADC DRQ */ 509 1.2.2.2 skrll val = CODEC_READ(sc, AC_ADC_FIFOC(sc)); 510 1.2.2.2 skrll CODEC_WRITE(sc, AC_ADC_FIFOC(sc), val & ~ADC_FIFOC_DRQ_EN); 511 1.2.2.2 skrll 512 1.2.2.2 skrll return 0; 513 1.2.2.2 skrll } 514 1.2.2.2 skrll 515 1.2.2.2 skrll static void 516 1.2.2.2 skrll sunxi_codec_get_locks(void *priv, kmutex_t **intr, kmutex_t **thread) 517 1.2.2.2 skrll { 518 1.2.2.2 skrll struct sunxi_codec_softc * const sc = priv; 519 1.2.2.2 skrll 520 1.2.2.2 skrll *intr = &sc->sc_intr_lock; 521 1.2.2.2 skrll *thread = &sc->sc_lock; 522 1.2.2.2 skrll } 523 1.2.2.2 skrll 524 1.2.2.2 skrll static const struct audio_hw_if sunxi_codec_hw_if = { 525 1.2.2.2 skrll .open = sunxi_codec_open, 526 1.2.2.2 skrll .close = sunxi_codec_close, 527 1.2.2.2 skrll .drain = sunxi_codec_drain, 528 1.2.2.2 skrll .query_encoding = sunxi_codec_query_encoding, 529 1.2.2.2 skrll .set_params = sunxi_codec_set_params, 530 1.2.2.2 skrll .allocm = sunxi_codec_allocm, 531 1.2.2.2 skrll .freem = sunxi_codec_freem, 532 1.2.2.2 skrll .mappage = sunxi_codec_mappage, 533 1.2.2.2 skrll .getdev = sunxi_codec_getdev, 534 1.2.2.2 skrll .set_port = sunxi_codec_set_port, 535 1.2.2.2 skrll .get_port = sunxi_codec_get_port, 536 1.2.2.2 skrll .query_devinfo = sunxi_codec_query_devinfo, 537 1.2.2.2 skrll .get_props = sunxi_codec_get_props, 538 1.2.2.2 skrll .round_blocksize = sunxi_codec_round_blocksize, 539 1.2.2.2 skrll .round_buffersize = sunxi_codec_round_buffersize, 540 1.2.2.2 skrll .trigger_output = sunxi_codec_trigger_output, 541 1.2.2.2 skrll .trigger_input = sunxi_codec_trigger_input, 542 1.2.2.2 skrll .halt_output = sunxi_codec_halt_output, 543 1.2.2.2 skrll .halt_input = sunxi_codec_halt_input, 544 1.2.2.2 skrll .get_locks = sunxi_codec_get_locks, 545 1.2.2.2 skrll }; 546 1.2.2.2 skrll 547 1.2.2.2 skrll static void 548 1.2.2.2 skrll sunxi_codec_dmaintr(void *priv) 549 1.2.2.2 skrll { 550 1.2.2.2 skrll struct sunxi_codec_chan * const ch = priv; 551 1.2.2.2 skrll 552 1.2.2.2 skrll ch->ch_cur_phys += ch->ch_blksize; 553 1.2.2.2 skrll if (ch->ch_cur_phys >= ch->ch_end_phys) 554 1.2.2.2 skrll ch->ch_cur_phys = ch->ch_start_phys; 555 1.2.2.2 skrll 556 1.2.2.2 skrll if (ch->ch_intr) { 557 1.2.2.2 skrll ch->ch_intr(ch->ch_intrarg); 558 1.2.2.2 skrll sunxi_codec_transfer(ch); 559 1.2.2.2 skrll } 560 1.2.2.2 skrll } 561 1.2.2.2 skrll 562 1.2.2.2 skrll static int 563 1.2.2.2 skrll sunxi_codec_chan_init(struct sunxi_codec_softc *sc, 564 1.2.2.2 skrll struct sunxi_codec_chan *ch, u_int mode, const char *dmaname) 565 1.2.2.2 skrll { 566 1.2.2.2 skrll ch->ch_sc = sc; 567 1.2.2.2 skrll ch->ch_mode = mode; 568 1.2.2.2 skrll ch->ch_dma = fdtbus_dma_get(sc->sc_phandle, dmaname, sunxi_codec_dmaintr, ch); 569 1.2.2.2 skrll if (ch->ch_dma == NULL) { 570 1.2.2.2 skrll aprint_error(": couldn't get dma channel \"%s\"\n", dmaname); 571 1.2.2.2 skrll return ENXIO; 572 1.2.2.2 skrll } 573 1.2.2.2 skrll 574 1.2.2.2 skrll if (mode == AUMODE_PLAY) { 575 1.2.2.2 skrll ch->ch_req.dreq_dir = FDT_DMA_WRITE; 576 1.2.2.2 skrll ch->ch_req.dreq_dev_phys = 577 1.2.2.2 skrll sc->sc_baseaddr + AC_DAC_TXDATA(sc); 578 1.2.2.2 skrll } else { 579 1.2.2.2 skrll ch->ch_req.dreq_dir = FDT_DMA_READ; 580 1.2.2.2 skrll ch->ch_req.dreq_dev_phys = 581 1.2.2.2 skrll sc->sc_baseaddr + AC_ADC_RXDATA(sc); 582 1.2.2.2 skrll } 583 1.2.2.2 skrll ch->ch_req.dreq_mem_opt.opt_bus_width = 16; 584 1.2.2.2 skrll ch->ch_req.dreq_mem_opt.opt_burst_len = 4; 585 1.2.2.2 skrll ch->ch_req.dreq_dev_opt.opt_bus_width = 16; 586 1.2.2.2 skrll ch->ch_req.dreq_dev_opt.opt_burst_len = 4; 587 1.2.2.2 skrll 588 1.2.2.2 skrll return 0; 589 1.2.2.2 skrll } 590 1.2.2.2 skrll 591 1.2.2.2 skrll static int 592 1.2.2.2 skrll sunxi_codec_clock_init(int phandle) 593 1.2.2.2 skrll { 594 1.2.2.2 skrll struct fdtbus_reset *rst; 595 1.2.2.2 skrll struct clk *clk; 596 1.2.2.2 skrll int error; 597 1.2.2.2 skrll 598 1.2.2.2 skrll /* Set codec clock to 24.576MHz, suitable for 48 kHz sampling rates */ 599 1.2.2.2 skrll clk = fdtbus_clock_get(phandle, "codec"); 600 1.2.2.2 skrll if (clk == NULL) { 601 1.2.2.2 skrll aprint_error(": couldn't find codec clock\n"); 602 1.2.2.2 skrll return ENXIO; 603 1.2.2.2 skrll } 604 1.2.2.2 skrll error = clk_set_rate(clk, 24576000); 605 1.2.2.2 skrll if (error != 0) { 606 1.2.2.2 skrll aprint_error(": couldn't set codec clock rate: %d\n", error); 607 1.2.2.2 skrll return error; 608 1.2.2.2 skrll } 609 1.2.2.2 skrll error = clk_enable(clk); 610 1.2.2.2 skrll if (error != 0) { 611 1.2.2.2 skrll aprint_error(": couldn't enable codec clock: %d\n", error); 612 1.2.2.2 skrll return error; 613 1.2.2.2 skrll } 614 1.2.2.2 skrll 615 1.2.2.2 skrll /* Enable APB clock */ 616 1.2.2.2 skrll clk = fdtbus_clock_get(phandle, "apb"); 617 1.2.2.2 skrll if (clk == NULL) { 618 1.2.2.2 skrll aprint_error(": couldn't find apb clock\n"); 619 1.2.2.2 skrll return ENXIO; 620 1.2.2.2 skrll } 621 1.2.2.2 skrll error = clk_enable(clk); 622 1.2.2.2 skrll if (error != 0) { 623 1.2.2.2 skrll aprint_error(": couldn't enable apb clock: %d\n", error); 624 1.2.2.2 skrll return error; 625 1.2.2.2 skrll } 626 1.2.2.2 skrll 627 1.2.2.2 skrll /* De-assert reset */ 628 1.2.2.2 skrll rst = fdtbus_reset_get_index(phandle, 0); 629 1.2.2.2 skrll if (rst == NULL) { 630 1.2.2.2 skrll aprint_error(": couldn't find reset\n"); 631 1.2.2.2 skrll return ENXIO; 632 1.2.2.2 skrll } 633 1.2.2.2 skrll error = fdtbus_reset_deassert(rst); 634 1.2.2.2 skrll if (error != 0) { 635 1.2.2.2 skrll aprint_error(": couldn't de-assert reset: %d\n", error); 636 1.2.2.2 skrll return error; 637 1.2.2.2 skrll } 638 1.2.2.2 skrll 639 1.2.2.2 skrll return 0; 640 1.2.2.2 skrll } 641 1.2.2.2 skrll 642 1.2.2.2 skrll static int 643 1.2.2.2 skrll sunxi_codec_match(device_t parent, cfdata_t cf, void *aux) 644 1.2.2.2 skrll { 645 1.2.2.2 skrll struct fdt_attach_args * const faa = aux; 646 1.2.2.2 skrll 647 1.2.2.2 skrll return of_match_compat_data(faa->faa_phandle, compat_data); 648 1.2.2.2 skrll } 649 1.2.2.2 skrll 650 1.2.2.2 skrll static void 651 1.2.2.2 skrll sunxi_codec_attach(device_t parent, device_t self, void *aux) 652 1.2.2.2 skrll { 653 1.2.2.2 skrll struct sunxi_codec_softc * const sc = device_private(self); 654 1.2.2.2 skrll struct fdt_attach_args * const faa = aux; 655 1.2.2.2 skrll const int phandle = faa->faa_phandle; 656 1.2.2.2 skrll bus_addr_t addr; 657 1.2.2.2 skrll bus_size_t size; 658 1.2.2.2 skrll uint32_t val; 659 1.2.2.2 skrll int error; 660 1.2.2.2 skrll 661 1.2.2.2 skrll if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 662 1.2.2.2 skrll aprint_error(": couldn't get registers\n"); 663 1.2.2.2 skrll return; 664 1.2.2.2 skrll } 665 1.2.2.2 skrll 666 1.2.2.2 skrll if (sunxi_codec_clock_init(phandle) != 0) 667 1.2.2.2 skrll return; 668 1.2.2.2 skrll 669 1.2.2.2 skrll sc->sc_dev = self; 670 1.2.2.2 skrll sc->sc_phandle = phandle; 671 1.2.2.2 skrll sc->sc_baseaddr = addr; 672 1.2.2.2 skrll sc->sc_bst = faa->faa_bst; 673 1.2.2.2 skrll if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 674 1.2.2.2 skrll aprint_error(": couldn't map registers\n"); 675 1.2.2.2 skrll return; 676 1.2.2.2 skrll } 677 1.2.2.2 skrll sc->sc_dmat = faa->faa_dmat; 678 1.2.2.2 skrll LIST_INIT(&sc->sc_dmalist); 679 1.2.2.2 skrll sc->sc_cfg = (void *)of_search_compatible(phandle, compat_data)->data; 680 1.2.2.2 skrll mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE); 681 1.2.2.2 skrll mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 682 1.2.2.2 skrll 683 1.2.2.2 skrll if (sunxi_codec_chan_init(sc, &sc->sc_pchan, AUMODE_PLAY, "tx") != 0 || 684 1.2.2.2 skrll sunxi_codec_chan_init(sc, &sc->sc_rchan, AUMODE_RECORD, "rx") != 0) { 685 1.2.2.2 skrll aprint_error(": couldn't setup channels\n"); 686 1.2.2.2 skrll return; 687 1.2.2.2 skrll } 688 1.2.2.2 skrll 689 1.2.2.2 skrll /* Optional PA mute GPIO */ 690 1.2.2.2 skrll sc->sc_pin_pa = fdtbus_gpio_acquire(phandle, "allwinner,pa-gpios", GPIO_PIN_OUTPUT); 691 1.2.2.2 skrll if (sc->sc_pin_pa != NULL) 692 1.2.2.2 skrll fdtbus_gpio_write(sc->sc_pin_pa, 1); 693 1.2.2.2 skrll 694 1.2.2.2 skrll aprint_naive("\n"); 695 1.2.2.2 skrll aprint_normal(": %s\n", sc->sc_cfg->name); 696 1.2.2.2 skrll 697 1.2.2.2 skrll /* Enable DAC */ 698 1.2.2.2 skrll val = CODEC_READ(sc, AC_DAC_DPC(sc)); 699 1.2.2.2 skrll val |= DAC_DPC_EN_DA; 700 1.2.2.2 skrll CODEC_WRITE(sc, AC_DAC_DPC(sc), val); 701 1.2.2.2 skrll 702 1.2.2.2 skrll /* Initialize codec */ 703 1.2.2.2 skrll if (sc->sc_cfg->init(sc) != 0) { 704 1.2.2.2 skrll aprint_error_dev(self, "couldn't initialize codec\n"); 705 1.2.2.2 skrll return; 706 1.2.2.2 skrll } 707 1.2.2.2 skrll 708 1.2.2.2 skrll sc->sc_format.mode = AUMODE_PLAY|AUMODE_RECORD; 709 1.2.2.2 skrll sc->sc_format.encoding = AUDIO_ENCODING_SLINEAR_LE; 710 1.2.2.2 skrll sc->sc_format.validbits = 16; 711 1.2.2.2 skrll sc->sc_format.precision = 16; 712 1.2.2.2 skrll sc->sc_format.channels = 2; 713 1.2.2.2 skrll sc->sc_format.channel_mask = AUFMT_STEREO; 714 1.2.2.2 skrll sc->sc_format.frequency_type = 0; 715 1.2.2.2 skrll sc->sc_format.frequency[0] = sc->sc_format.frequency[1] = 48000; 716 1.2.2.2 skrll 717 1.2.2.2 skrll error = auconv_create_encodings(&sc->sc_format, 1, &sc->sc_encodings); 718 1.2.2.2 skrll if (error) { 719 1.2.2.2 skrll aprint_error_dev(self, "couldn't create encodings\n"); 720 1.2.2.2 skrll return; 721 1.2.2.2 skrll } 722 1.2.2.2 skrll 723 1.2.2.2 skrll audio_attach_mi(&sunxi_codec_hw_if, sc, self); 724 1.2.2.2 skrll } 725 1.2.2.2 skrll 726 1.2.2.2 skrll CFATTACH_DECL_NEW(sunxi_codec, sizeof(struct sunxi_codec_softc), 727 1.2.2.2 skrll sunxi_codec_match, sunxi_codec_attach, NULL, NULL); 728 1.2.2.2 skrll 729 1.2.2.2 skrll #ifdef DDB 730 1.2.2.2 skrll void sunxicodec_dump(void); 731 1.2.2.2 skrll 732 1.2.2.2 skrll void 733 1.2.2.2 skrll sunxicodec_dump(void) 734 1.2.2.2 skrll { 735 1.2.2.2 skrll struct sunxi_codec_softc *sc; 736 1.2.2.2 skrll device_t dev; 737 1.2.2.2 skrll 738 1.2.2.2 skrll dev = device_find_by_driver_unit("sunxicodec", 0); 739 1.2.2.2 skrll if (dev == NULL) 740 1.2.2.2 skrll return; 741 1.2.2.2 skrll sc = device_private(dev); 742 1.2.2.2 skrll 743 1.2.2.2 skrll device_printf(dev, "AC_DAC_DPC: %08x\n", CODEC_READ(sc, AC_DAC_DPC(sc))); 744 1.2.2.2 skrll device_printf(dev, "AC_DAC_FIFOC: %08x\n", CODEC_READ(sc, AC_DAC_FIFOC(sc))); 745 1.2.2.2 skrll device_printf(dev, "AC_DAC_FIFOS: %08x\n", CODEC_READ(sc, AC_DAC_FIFOS(sc))); 746 1.2.2.2 skrll device_printf(dev, "AC_ADC_FIFOC: %08x\n", CODEC_READ(sc, AC_ADC_FIFOC(sc))); 747 1.2.2.2 skrll device_printf(dev, "AC_ADC_FIFOS: %08x\n", CODEC_READ(sc, AC_ADC_FIFOS(sc))); 748 1.2.2.2 skrll device_printf(dev, "AC_DAC_CNT: %08x\n", CODEC_READ(sc, AC_DAC_CNT(sc))); 749 1.2.2.2 skrll device_printf(dev, "AC_ADC_CNT: %08x\n", CODEC_READ(sc, AC_ADC_CNT(sc))); 750 1.2.2.2 skrll } 751 1.2.2.2 skrll #endif 752
Indexes created Sat Oct 18 16:10:06 GMT 2025