sunxi_codec.c revision 1.12
1 /* $NetBSD: sunxi_codec.c,v 1.12 2021/01/27 03:10:20 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2014-2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_ddb.h" 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: sunxi_codec.c,v 1.12 2021/01/27 03:10:20 thorpej Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/cpu.h> 37 #include <sys/device.h> 38 #include <sys/kmem.h> 39 #include <sys/gpio.h> 40 41 #include <sys/audioio.h> 42 #include <dev/audio/audio_if.h> 43 44 #include <dev/fdt/fdtvar.h> 45 46 #include <arm/sunxi/sunxi_codec.h> 47 48 #define TX_TRIG_LEVEL 0xf 49 #define RX_TRIG_LEVEL 0x7 50 #define DRQ_CLR_CNT 0x3 51 52 #define AC_DAC_DPC(_sc) ((_sc)->sc_cfg->DPC) 53 #define DAC_DPC_EN_DA 0x80000000 54 #define AC_DAC_FIFOC(_sc) ((_sc)->sc_cfg->DAC_FIFOC) 55 #define DAC_FIFOC_FS __BITS(31,29) 56 #define DAC_FS_48KHZ 0 57 #define DAC_FS_32KHZ 1 58 #define DAC_FS_24KHZ 2 59 #define DAC_FS_16KHZ 3 60 #define DAC_FS_12KHZ 4 61 #define DAC_FS_8KHZ 5 62 #define DAC_FS_192KHZ 6 63 #define DAC_FS_96KHZ 7 64 #define DAC_FIFOC_FIFO_MODE __BITS(25,24) 65 #define FIFO_MODE_24_31_8 0 66 #define FIFO_MODE_16_31_16 0 67 #define FIFO_MODE_16_15_0 1 68 #define DAC_FIFOC_DRQ_CLR_CNT __BITS(22,21) 69 #define DAC_FIFOC_TX_TRIG_LEVEL __BITS(14,8) 70 #define DAC_FIFOC_MONO_EN __BIT(6) 71 #define DAC_FIFOC_TX_BITS __BIT(5) 72 #define DAC_FIFOC_DRQ_EN __BIT(4) 73 #define DAC_FIFOC_FIFO_FLUSH __BIT(0) 74 #define AC_DAC_FIFOS(_sc) ((_sc)->sc_cfg->DAC_FIFOS) 75 #define AC_DAC_TXDATA(_sc) ((_sc)->sc_cfg->DAC_TXDATA) 76 #define AC_ADC_FIFOC(_sc) ((_sc)->sc_cfg->ADC_FIFOC) 77 #define ADC_FIFOC_FS __BITS(31,29) 78 #define ADC_FS_48KHZ 0 79 #define ADC_FIFOC_EN_AD __BIT(28) 80 #define ADC_FIFOC_RX_FIFO_MODE __BIT(24) 81 #define ADC_FIFOC_RX_TRIG_LEVEL __BITS(12,8) 82 #define ADC_FIFOC_MONO_EN __BIT(7) 83 #define ADC_FIFOC_RX_BITS __BIT(6) 84 #define ADC_FIFOC_DRQ_EN __BIT(4) 85 #define ADC_FIFOC_FIFO_FLUSH __BIT(0) 86 #define AC_ADC_FIFOS(_sc) ((_sc)->sc_cfg->ADC_FIFOS) 87 #define AC_ADC_RXDATA(_sc) ((_sc)->sc_cfg->ADC_RXDATA) 88 #define AC_DAC_CNT(_sc) ((_sc)->sc_cfg->DAC_CNT) 89 #define AC_ADC_CNT(_sc) ((_sc)->sc_cfg->ADC_CNT) 90 91 static const struct device_compatible_entry compat_data[] = { 92 A10_CODEC_COMPATDATA, 93 A31_CODEC_COMPATDATA, 94 H3_CODEC_COMPATDATA, 95 96 DEVICE_COMPAT_EOL 97 }; 98 99 #define CODEC_READ(sc, reg) \ 100 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 101 #define CODEC_WRITE(sc, reg, val) \ 102 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 103 104 static int 105 sunxi_codec_allocdma(struct sunxi_codec_softc *sc, size_t size, 106 size_t align, struct sunxi_codec_dma *dma) 107 { 108 int error; 109 110 dma->dma_size = size; 111 error = bus_dmamem_alloc(sc->sc_dmat, dma->dma_size, align, 0, 112 dma->dma_segs, 1, &dma->dma_nsegs, BUS_DMA_WAITOK); 113 if (error) 114 return error; 115 116 error = bus_dmamem_map(sc->sc_dmat, dma->dma_segs, dma->dma_nsegs, 117 dma->dma_size, &dma->dma_addr, BUS_DMA_WAITOK | BUS_DMA_COHERENT); 118 if (error) 119 goto free; 120 121 error = bus_dmamap_create(sc->sc_dmat, dma->dma_size, dma->dma_nsegs, 122 dma->dma_size, 0, BUS_DMA_WAITOK, &dma->dma_map); 123 if (error) 124 goto unmap; 125 126 error = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_addr, 127 dma->dma_size, NULL, BUS_DMA_WAITOK); 128 if (error) 129 goto destroy; 130 131 return 0; 132 133 destroy: 134 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 135 unmap: 136 bus_dmamem_unmap(sc->sc_dmat, dma->dma_addr, dma->dma_size); 137 free: 138 bus_dmamem_free(sc->sc_dmat, dma->dma_segs, dma->dma_nsegs); 139 140 return error; 141 } 142 143 static void 144 sunxi_codec_freedma(struct sunxi_codec_softc *sc, struct sunxi_codec_dma *dma) 145 { 146 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 147 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 148 bus_dmamem_unmap(sc->sc_dmat, dma->dma_addr, dma->dma_size); 149 bus_dmamem_free(sc->sc_dmat, dma->dma_segs, dma->dma_nsegs); 150 } 151 152 static int 153 sunxi_codec_transfer(struct sunxi_codec_chan *ch) 154 { 155 bus_dma_segment_t seg; 156 157 seg.ds_addr = ch->ch_cur_phys; 158 seg.ds_len = ch->ch_blksize; 159 ch->ch_req.dreq_segs = &seg; 160 ch->ch_req.dreq_nsegs = 1; 161 162 return fdtbus_dma_transfer(ch->ch_dma, &ch->ch_req); 163 } 164 165 static int 166 sunxi_codec_query_format(void *priv, audio_format_query_t *afp) 167 { 168 struct sunxi_codec_softc * const sc = priv; 169 170 return audio_query_format(&sc->sc_format, 1, afp); 171 } 172 173 static int 174 sunxi_codec_set_format(void *priv, int setmode, 175 const audio_params_t *play, const audio_params_t *rec, 176 audio_filter_reg_t *pfil, audio_filter_reg_t *rfil) 177 { 178 179 return 0; 180 } 181 182 static int 183 sunxi_codec_set_port(void *priv, mixer_ctrl_t *mc) 184 { 185 struct sunxi_codec_softc * const sc = priv; 186 187 return sc->sc_cfg->set_port(sc, mc); 188 } 189 190 static int 191 sunxi_codec_get_port(void *priv, mixer_ctrl_t *mc) 192 { 193 struct sunxi_codec_softc * const sc = priv; 194 195 return sc->sc_cfg->get_port(sc, mc); 196 } 197 198 static int 199 sunxi_codec_query_devinfo(void *priv, mixer_devinfo_t *di) 200 { 201 struct sunxi_codec_softc * const sc = priv; 202 203 return sc->sc_cfg->query_devinfo(sc, di); 204 } 205 206 static void * 207 sunxi_codec_allocm(void *priv, int dir, size_t size) 208 { 209 struct sunxi_codec_softc * const sc = priv; 210 struct sunxi_codec_dma *dma; 211 int error; 212 213 dma = kmem_alloc(sizeof(*dma), KM_SLEEP); 214 215 error = sunxi_codec_allocdma(sc, size, 16, dma); 216 if (error) { 217 kmem_free(dma, sizeof(*dma)); 218 device_printf(sc->sc_dev, "couldn't allocate DMA memory (%d)\n", 219 error); 220 return NULL; 221 } 222 223 LIST_INSERT_HEAD(&sc->sc_dmalist, dma, dma_list); 224 225 return dma->dma_addr; 226 } 227 228 static void 229 sunxi_codec_freem(void *priv, void *addr, size_t size) 230 { 231 struct sunxi_codec_softc * const sc = priv; 232 struct sunxi_codec_dma *dma; 233 234 LIST_FOREACH(dma, &sc->sc_dmalist, dma_list) 235 if (dma->dma_addr == addr) { 236 sunxi_codec_freedma(sc, dma); 237 LIST_REMOVE(dma, dma_list); 238 kmem_free(dma, sizeof(*dma)); 239 break; 240 } 241 } 242 243 static int 244 sunxi_codec_getdev(void *priv, struct audio_device *adev) 245 { 246 struct sunxi_codec_softc * const sc = priv; 247 248 snprintf(adev->name, sizeof(adev->name), "Allwinner"); 249 snprintf(adev->version, sizeof(adev->version), "%s", 250 sc->sc_cfg->name); 251 snprintf(adev->config, sizeof(adev->config), "sunxicodec"); 252 253 return 0; 254 } 255 256 static int 257 sunxi_codec_get_props(void *priv) 258 { 259 260 return AUDIO_PROP_PLAYBACK | AUDIO_PROP_CAPTURE| 261 AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 262 } 263 264 static int 265 sunxi_codec_trigger_output(void *priv, void *start, void *end, int blksize, 266 void (*intr)(void *), void *intrarg, const audio_params_t *params) 267 { 268 struct sunxi_codec_softc * const sc = priv; 269 struct sunxi_codec_chan *ch = &sc->sc_pchan; 270 struct sunxi_codec_dma *dma; 271 bus_addr_t pstart; 272 bus_size_t psize; 273 uint32_t val; 274 int error; 275 276 pstart = 0; 277 psize = (uintptr_t)end - (uintptr_t)start; 278 279 LIST_FOREACH(dma, &sc->sc_dmalist, dma_list) 280 if (dma->dma_addr == start) { 281 pstart = dma->dma_map->dm_segs[0].ds_addr; 282 break; 283 } 284 if (pstart == 0) { 285 device_printf(sc->sc_dev, "bad addr %p\n", start); 286 return EINVAL; 287 } 288 289 ch->ch_intr = intr; 290 ch->ch_intrarg = intrarg; 291 ch->ch_start_phys = ch->ch_cur_phys = pstart; 292 ch->ch_end_phys = pstart + psize; 293 ch->ch_blksize = blksize; 294 295 /* Flush DAC FIFO */ 296 val = CODEC_READ(sc, AC_DAC_FIFOC(sc)); 297 CODEC_WRITE(sc, AC_DAC_FIFOC(sc), val | DAC_FIFOC_FIFO_FLUSH); 298 299 /* Clear DAC FIFO status */ 300 val = CODEC_READ(sc, AC_DAC_FIFOS(sc)); 301 CODEC_WRITE(sc, AC_DAC_FIFOS(sc), val); 302 303 /* Unmute output */ 304 if (sc->sc_cfg->mute) 305 sc->sc_cfg->mute(sc, 0, ch->ch_mode); 306 307 /* Configure DAC FIFO */ 308 CODEC_WRITE(sc, AC_DAC_FIFOC(sc), 309 __SHIFTIN(DAC_FS_48KHZ, DAC_FIFOC_FS) | 310 __SHIFTIN(FIFO_MODE_16_15_0, DAC_FIFOC_FIFO_MODE) | 311 __SHIFTIN(DRQ_CLR_CNT, DAC_FIFOC_DRQ_CLR_CNT) | 312 __SHIFTIN(TX_TRIG_LEVEL, DAC_FIFOC_TX_TRIG_LEVEL)); 313 314 /* Enable DAC DRQ */ 315 val = CODEC_READ(sc, AC_DAC_FIFOC(sc)); 316 CODEC_WRITE(sc, AC_DAC_FIFOC(sc), val | DAC_FIFOC_DRQ_EN); 317 318 /* Start DMA transfer */ 319 error = sunxi_codec_transfer(ch); 320 if (error != 0) { 321 aprint_error_dev(sc->sc_dev, 322 "failed to start DMA transfer: %d\n", error); 323 return error; 324 } 325 326 return 0; 327 } 328 329 static int 330 sunxi_codec_trigger_input(void *priv, void *start, void *end, int blksize, 331 void (*intr)(void *), void *intrarg, const audio_params_t *params) 332 { 333 struct sunxi_codec_softc * const sc = priv; 334 struct sunxi_codec_chan *ch = &sc->sc_rchan; 335 struct sunxi_codec_dma *dma; 336 bus_addr_t pstart; 337 bus_size_t psize; 338 uint32_t val; 339 int error; 340 341 pstart = 0; 342 psize = (uintptr_t)end - (uintptr_t)start; 343 344 LIST_FOREACH(dma, &sc->sc_dmalist, dma_list) 345 if (dma->dma_addr == start) { 346 pstart = dma->dma_map->dm_segs[0].ds_addr; 347 break; 348 } 349 if (pstart == 0) { 350 device_printf(sc->sc_dev, "bad addr %p\n", start); 351 return EINVAL; 352 } 353 354 ch->ch_intr = intr; 355 ch->ch_intrarg = intrarg; 356 ch->ch_start_phys = ch->ch_cur_phys = pstart; 357 ch->ch_end_phys = pstart + psize; 358 ch->ch_blksize = blksize; 359 360 /* Flush ADC FIFO */ 361 val = CODEC_READ(sc, AC_ADC_FIFOC(sc)); 362 CODEC_WRITE(sc, AC_ADC_FIFOC(sc), val | ADC_FIFOC_FIFO_FLUSH); 363 364 /* Clear ADC FIFO status */ 365 val = CODEC_READ(sc, AC_ADC_FIFOS(sc)); 366 CODEC_WRITE(sc, AC_ADC_FIFOS(sc), val); 367 368 /* Unmute input */ 369 if (sc->sc_cfg->mute) 370 sc->sc_cfg->mute(sc, 0, ch->ch_mode); 371 372 /* Configure ADC FIFO */ 373 CODEC_WRITE(sc, AC_ADC_FIFOC(sc), 374 __SHIFTIN(ADC_FS_48KHZ, ADC_FIFOC_FS) | 375 __SHIFTIN(RX_TRIG_LEVEL, ADC_FIFOC_RX_TRIG_LEVEL) | 376 ADC_FIFOC_EN_AD | ADC_FIFOC_RX_FIFO_MODE); 377 378 /* Enable ADC DRQ */ 379 val = CODEC_READ(sc, AC_ADC_FIFOC(sc)); 380 CODEC_WRITE(sc, AC_ADC_FIFOC(sc), val | ADC_FIFOC_DRQ_EN); 381 382 /* Start DMA transfer */ 383 error = sunxi_codec_transfer(ch); 384 if (error != 0) { 385 aprint_error_dev(sc->sc_dev, 386 "failed to start DMA transfer: %d\n", error); 387 return error; 388 } 389 390 return 0; 391 } 392 393 static int 394 sunxi_codec_halt_output(void *priv) 395 { 396 struct sunxi_codec_softc * const sc = priv; 397 struct sunxi_codec_chan *ch = &sc->sc_pchan; 398 uint32_t val; 399 400 /* Disable DMA channel */ 401 fdtbus_dma_halt(ch->ch_dma); 402 403 /* flush fifo */ 404 val = CODEC_READ(sc, AC_DAC_FIFOC(sc)); 405 CODEC_WRITE(sc, AC_DAC_FIFOC(sc), val | DAC_FIFOC_FIFO_FLUSH); 406 while (val & DAC_FIFOC_FIFO_FLUSH) 407 val = CODEC_READ(sc, AC_DAC_FIFOC(sc)); 408 409 /* Mute output */ 410 if (sc->sc_cfg->mute) 411 sc->sc_cfg->mute(sc, 1, ch->ch_mode); 412 413 /* Disable DAC DRQ */ 414 val = CODEC_READ(sc, AC_DAC_FIFOC(sc)); 415 CODEC_WRITE(sc, AC_DAC_FIFOC(sc), val & ~DAC_FIFOC_DRQ_EN); 416 417 ch->ch_intr = NULL; 418 ch->ch_intrarg = NULL; 419 420 return 0; 421 } 422 423 static int 424 sunxi_codec_halt_input(void *priv) 425 { 426 struct sunxi_codec_softc * const sc = priv; 427 struct sunxi_codec_chan *ch = &sc->sc_rchan; 428 uint32_t val; 429 430 /* Mute output */ 431 if (sc->sc_cfg->mute) 432 sc->sc_cfg->mute(sc, 1, ch->ch_mode); 433 434 /* flush fifo */ 435 val = CODEC_READ(sc, AC_ADC_FIFOC(sc)); 436 CODEC_WRITE(sc, AC_ADC_FIFOC(sc), val | ADC_FIFOC_FIFO_FLUSH); 437 while (val & ADC_FIFOC_FIFO_FLUSH) 438 val = CODEC_READ(sc, AC_ADC_FIFOC(sc)); 439 440 /* Disable DMA channel */ 441 fdtbus_dma_halt(ch->ch_dma); 442 443 /* Disable ADC DRQ */ 444 val = CODEC_READ(sc, AC_ADC_FIFOC(sc)); 445 CODEC_WRITE(sc, AC_ADC_FIFOC(sc), val & ~ADC_FIFOC_DRQ_EN); 446 447 return 0; 448 } 449 450 static void 451 sunxi_codec_get_locks(void *priv, kmutex_t **intr, kmutex_t **thread) 452 { 453 struct sunxi_codec_softc * const sc = priv; 454 455 *intr = &sc->sc_intr_lock; 456 *thread = &sc->sc_lock; 457 } 458 459 static const struct audio_hw_if sunxi_codec_hw_if = { 460 .query_format = sunxi_codec_query_format, 461 .set_format = sunxi_codec_set_format, 462 .allocm = sunxi_codec_allocm, 463 .freem = sunxi_codec_freem, 464 .getdev = sunxi_codec_getdev, 465 .set_port = sunxi_codec_set_port, 466 .get_port = sunxi_codec_get_port, 467 .query_devinfo = sunxi_codec_query_devinfo, 468 .get_props = sunxi_codec_get_props, 469 .trigger_output = sunxi_codec_trigger_output, 470 .trigger_input = sunxi_codec_trigger_input, 471 .halt_output = sunxi_codec_halt_output, 472 .halt_input = sunxi_codec_halt_input, 473 .get_locks = sunxi_codec_get_locks, 474 }; 475 476 static void 477 sunxi_codec_dmaintr(void *priv) 478 { 479 struct sunxi_codec_chan * const ch = priv; 480 struct sunxi_codec_softc * const sc = ch->ch_sc; 481 482 mutex_enter(&sc->sc_intr_lock); 483 ch->ch_cur_phys += ch->ch_blksize; 484 if (ch->ch_cur_phys >= ch->ch_end_phys) 485 ch->ch_cur_phys = ch->ch_start_phys; 486 487 if (ch->ch_intr) { 488 ch->ch_intr(ch->ch_intrarg); 489 sunxi_codec_transfer(ch); 490 } 491 mutex_exit(&sc->sc_intr_lock); 492 } 493 494 static int 495 sunxi_codec_chan_init(struct sunxi_codec_softc *sc, 496 struct sunxi_codec_chan *ch, u_int mode, const char *dmaname) 497 { 498 ch->ch_sc = sc; 499 ch->ch_mode = mode; 500 ch->ch_dma = fdtbus_dma_get(sc->sc_phandle, dmaname, sunxi_codec_dmaintr, ch); 501 if (ch->ch_dma == NULL) { 502 aprint_error(": couldn't get dma channel \"%s\"\n", dmaname); 503 return ENXIO; 504 } 505 506 if (mode == AUMODE_PLAY) { 507 ch->ch_req.dreq_dir = FDT_DMA_WRITE; 508 ch->ch_req.dreq_dev_phys = 509 sc->sc_baseaddr + AC_DAC_TXDATA(sc); 510 } else { 511 ch->ch_req.dreq_dir = FDT_DMA_READ; 512 ch->ch_req.dreq_dev_phys = 513 sc->sc_baseaddr + AC_ADC_RXDATA(sc); 514 } 515 ch->ch_req.dreq_mem_opt.opt_bus_width = 16; 516 ch->ch_req.dreq_mem_opt.opt_burst_len = 4; 517 ch->ch_req.dreq_dev_opt.opt_bus_width = 16; 518 ch->ch_req.dreq_dev_opt.opt_burst_len = 4; 519 520 return 0; 521 } 522 523 static int 524 sunxi_codec_clock_init(int phandle) 525 { 526 struct fdtbus_reset *rst; 527 struct clk *clk; 528 int error; 529 530 /* Set codec clock to 24.576MHz, suitable for 48 kHz sampling rates */ 531 clk = fdtbus_clock_get(phandle, "codec"); 532 if (clk == NULL) { 533 aprint_error(": couldn't find codec clock\n"); 534 return ENXIO; 535 } 536 error = clk_set_rate(clk, 24576000); 537 if (error != 0) { 538 aprint_error(": couldn't set codec clock rate: %d\n", error); 539 return error; 540 } 541 error = clk_enable(clk); 542 if (error != 0) { 543 aprint_error(": couldn't enable codec clock: %d\n", error); 544 return error; 545 } 546 547 /* Enable APB clock */ 548 clk = fdtbus_clock_get(phandle, "apb"); 549 if (clk == NULL) { 550 aprint_error(": couldn't find apb clock\n"); 551 return ENXIO; 552 } 553 error = clk_enable(clk); 554 if (error != 0) { 555 aprint_error(": couldn't enable apb clock: %d\n", error); 556 return error; 557 } 558 559 /* De-assert reset */ 560 rst = fdtbus_reset_get_index(phandle, 0); 561 if (rst != NULL) { 562 error = fdtbus_reset_deassert(rst); 563 if (error != 0) { 564 aprint_error(": couldn't de-assert reset: %d\n", error); 565 return error; 566 } 567 } 568 569 return 0; 570 } 571 572 static int 573 sunxi_codec_match(device_t parent, cfdata_t cf, void *aux) 574 { 575 struct fdt_attach_args * const faa = aux; 576 577 return of_compatible_match(faa->faa_phandle, compat_data); 578 } 579 580 static void 581 sunxi_codec_attach(device_t parent, device_t self, void *aux) 582 { 583 struct sunxi_codec_softc * const sc = device_private(self); 584 struct fdt_attach_args * const faa = aux; 585 const int phandle = faa->faa_phandle; 586 bus_addr_t addr; 587 bus_size_t size; 588 uint32_t val; 589 590 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 591 aprint_error(": couldn't get registers\n"); 592 return; 593 } 594 595 if (sunxi_codec_clock_init(phandle) != 0) 596 return; 597 598 sc->sc_dev = self; 599 sc->sc_phandle = phandle; 600 sc->sc_baseaddr = addr; 601 sc->sc_bst = faa->faa_bst; 602 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 603 aprint_error(": couldn't map registers\n"); 604 return; 605 } 606 sc->sc_dmat = faa->faa_dmat; 607 LIST_INIT(&sc->sc_dmalist); 608 sc->sc_cfg = of_compatible_lookup(phandle, compat_data)->data; 609 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE); 610 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 611 612 if (sunxi_codec_chan_init(sc, &sc->sc_pchan, AUMODE_PLAY, "tx") != 0 || 613 sunxi_codec_chan_init(sc, &sc->sc_rchan, AUMODE_RECORD, "rx") != 0) { 614 aprint_error(": couldn't setup channels\n"); 615 return; 616 } 617 618 /* Optional PA mute GPIO */ 619 sc->sc_pin_pa = fdtbus_gpio_acquire(phandle, "allwinner,pa-gpios", GPIO_PIN_OUTPUT); 620 621 aprint_naive("\n"); 622 aprint_normal(": %s\n", sc->sc_cfg->name); 623 624 /* Enable DAC */ 625 val = CODEC_READ(sc, AC_DAC_DPC(sc)); 626 val |= DAC_DPC_EN_DA; 627 CODEC_WRITE(sc, AC_DAC_DPC(sc), val); 628 629 /* Initialize codec */ 630 if (sc->sc_cfg->init(sc) != 0) { 631 aprint_error_dev(self, "couldn't initialize codec\n"); 632 return; 633 } 634 635 sc->sc_format.mode = AUMODE_PLAY|AUMODE_RECORD; 636 sc->sc_format.encoding = AUDIO_ENCODING_SLINEAR_LE; 637 sc->sc_format.validbits = 16; 638 sc->sc_format.precision = 16; 639 sc->sc_format.channels = 2; 640 sc->sc_format.channel_mask = AUFMT_STEREO; 641 sc->sc_format.frequency_type = 1; 642 sc->sc_format.frequency[0] = 48000; 643 644 audio_attach_mi(&sunxi_codec_hw_if, sc, self); 645 } 646 647 CFATTACH_DECL_NEW(sunxi_codec, sizeof(struct sunxi_codec_softc), 648 sunxi_codec_match, sunxi_codec_attach, NULL, NULL); 649 650 #ifdef DDB 651 void sunxicodec_dump(void); 652 653 void 654 sunxicodec_dump(void) 655 { 656 struct sunxi_codec_softc *sc; 657 device_t dev; 658 659 dev = device_find_by_driver_unit("sunxicodec", 0); 660 if (dev == NULL) 661 return; 662 sc = device_private(dev); 663 664 device_printf(dev, "AC_DAC_DPC: %08x\n", CODEC_READ(sc, AC_DAC_DPC(sc))); 665 device_printf(dev, "AC_DAC_FIFOC: %08x\n", CODEC_READ(sc, AC_DAC_FIFOC(sc))); 666 device_printf(dev, "AC_DAC_FIFOS: %08x\n", CODEC_READ(sc, AC_DAC_FIFOS(sc))); 667 device_printf(dev, "AC_ADC_FIFOC: %08x\n", CODEC_READ(sc, AC_ADC_FIFOC(sc))); 668 device_printf(dev, "AC_ADC_FIFOS: %08x\n", CODEC_READ(sc, AC_ADC_FIFOS(sc))); 669 device_printf(dev, "AC_DAC_CNT: %08x\n", CODEC_READ(sc, AC_DAC_CNT(sc))); 670 device_printf(dev, "AC_ADC_CNT: %08x\n", CODEC_READ(sc, AC_ADC_CNT(sc))); 671 } 672 #endif 673
Indexes created Tue Sep 23 14:10:03 GMT 2025