sunxi_codec.c revision 1.2
1 /* $NetBSD: sunxi_codec.c,v 1.2 2017/08/27 16:05:26 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2014-2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_ddb.h" 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: sunxi_codec.c,v 1.2 2017/08/27 16:05:26 jmcneill Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/cpu.h> 37 #include <sys/device.h> 38 #include <sys/kmem.h> 39 #include <sys/gpio.h> 40 41 #include <sys/audioio.h> 42 #include <dev/audio_if.h> 43 #include <dev/auconv.h> 44 45 #include <dev/fdt/fdtvar.h> 46 47 #include <arm/sunxi/sunxi_codec.h> 48 49 #define TX_TRIG_LEVEL 0xf 50 #define RX_TRIG_LEVEL 0x7 51 #define DRQ_CLR_CNT 0x3 52 53 #define AC_DAC_DPC(_sc) ((_sc)->sc_cfg->DPC) 54 #define DAC_DPC_EN_DA 0x80000000 55 #define AC_DAC_FIFOC(_sc) ((_sc)->sc_cfg->DAC_FIFOC) 56 #define DAC_FIFOC_FS __BITS(31,29) 57 #define DAC_FS_48KHZ 0 58 #define DAC_FS_32KHZ 1 59 #define DAC_FS_24KHZ 2 60 #define DAC_FS_16KHZ 3 61 #define DAC_FS_12KHZ 4 62 #define DAC_FS_8KHZ 5 63 #define DAC_FS_192KHZ 6 64 #define DAC_FS_96KHZ 7 65 #define DAC_FIFOC_FIFO_MODE __BITS(25,24) 66 #define FIFO_MODE_24_31_8 0 67 #define FIFO_MODE_16_31_16 0 68 #define FIFO_MODE_16_15_0 1 69 #define DAC_FIFOC_DRQ_CLR_CNT __BITS(22,21) 70 #define DAC_FIFOC_TX_TRIG_LEVEL __BITS(14,8) 71 #define DAC_FIFOC_MONO_EN __BIT(6) 72 #define DAC_FIFOC_TX_BITS __BIT(5) 73 #define DAC_FIFOC_DRQ_EN __BIT(4) 74 #define DAC_FIFOC_FIFO_FLUSH __BIT(0) 75 #define AC_DAC_FIFOS(_sc) ((_sc)->sc_cfg->DAC_FIFOS) 76 #define AC_DAC_TXDATA(_sc) ((_sc)->sc_cfg->DAC_TXDATA) 77 #define AC_ADC_FIFOC(_sc) ((_sc)->sc_cfg->ADC_FIFOC) 78 #define ADC_FIFOC_FS __BITS(31,29) 79 #define ADC_FS_48KHZ 0 80 #define ADC_FIFOC_EN_AD __BIT(28) 81 #define ADC_FIFOC_RX_FIFO_MODE __BIT(24) 82 #define ADC_FIFOC_RX_TRIG_LEVEL __BITS(12,8) 83 #define ADC_FIFOC_MONO_EN __BIT(7) 84 #define ADC_FIFOC_RX_BITS __BIT(6) 85 #define ADC_FIFOC_DRQ_EN __BIT(4) 86 #define ADC_FIFOC_FIFO_FLUSH __BIT(0) 87 #define AC_ADC_FIFOS(_sc) ((_sc)->sc_cfg->ADC_FIFOS) 88 #define AC_ADC_RXDATA(_sc) ((_sc)->sc_cfg->ADC_RXDATA) 89 #define AC_DAC_CNT(_sc) ((_sc)->sc_cfg->DAC_CNT) 90 #define AC_ADC_CNT(_sc) ((_sc)->sc_cfg->ADC_CNT) 91 92 static const struct of_compat_data compat_data[] = { 93 A10_CODEC_COMPATDATA, 94 H3_CODEC_COMPATDATA, 95 { NULL } 96 }; 97 98 #define CODEC_READ(sc, reg) \ 99 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 100 #define CODEC_WRITE(sc, reg, val) \ 101 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 102 103 static int 104 sunxi_codec_allocdma(struct sunxi_codec_softc *sc, size_t size, 105 size_t align, struct sunxi_codec_dma *dma) 106 { 107 int error; 108 109 dma->dma_size = size; 110 error = bus_dmamem_alloc(sc->sc_dmat, dma->dma_size, align, 0, 111 dma->dma_segs, 1, &dma->dma_nsegs, BUS_DMA_WAITOK); 112 if (error) 113 return error; 114 115 error = bus_dmamem_map(sc->sc_dmat, dma->dma_segs, dma->dma_nsegs, 116 dma->dma_size, &dma->dma_addr, BUS_DMA_WAITOK | BUS_DMA_COHERENT); 117 if (error) 118 goto free; 119 120 error = bus_dmamap_create(sc->sc_dmat, dma->dma_size, dma->dma_nsegs, 121 dma->dma_size, 0, BUS_DMA_WAITOK, &dma->dma_map); 122 if (error) 123 goto unmap; 124 125 error = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_addr, 126 dma->dma_size, NULL, BUS_DMA_WAITOK); 127 if (error) 128 goto destroy; 129 130 return 0; 131 132 destroy: 133 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 134 unmap: 135 bus_dmamem_unmap(sc->sc_dmat, dma->dma_addr, dma->dma_size); 136 free: 137 bus_dmamem_free(sc->sc_dmat, dma->dma_segs, dma->dma_nsegs); 138 139 return error; 140 } 141 142 static void 143 sunxi_codec_freedma(struct sunxi_codec_softc *sc, struct sunxi_codec_dma *dma) 144 { 145 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 146 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 147 bus_dmamem_unmap(sc->sc_dmat, dma->dma_addr, dma->dma_size); 148 bus_dmamem_free(sc->sc_dmat, dma->dma_segs, dma->dma_nsegs); 149 } 150 151 static int 152 sunxi_codec_transfer(struct sunxi_codec_chan *ch) 153 { 154 bus_dma_segment_t seg; 155 156 seg.ds_addr = ch->ch_cur_phys; 157 seg.ds_len = ch->ch_blksize; 158 ch->ch_req.dreq_segs = &seg; 159 ch->ch_req.dreq_nsegs = 1; 160 161 return fdtbus_dma_transfer(ch->ch_dma, &ch->ch_req); 162 } 163 164 static int 165 sunxi_codec_open(void *priv, int flags) 166 { 167 return 0; 168 } 169 170 static void 171 sunxi_codec_close(void *priv) 172 { 173 } 174 175 static int 176 sunxi_codec_drain(void *priv) 177 { 178 struct sunxi_codec_softc * const sc = priv; 179 uint32_t val; 180 181 val = CODEC_READ(sc, AC_DAC_FIFOC(sc)); 182 CODEC_WRITE(sc, AC_DAC_FIFOC(sc), val | DAC_FIFOC_FIFO_FLUSH); 183 184 val = CODEC_READ(sc, AC_ADC_FIFOC(sc)); 185 CODEC_WRITE(sc, AC_ADC_FIFOC(sc), val | ADC_FIFOC_FIFO_FLUSH); 186 187 return 0; 188 } 189 190 static int 191 sunxi_codec_query_encoding(void *priv, struct audio_encoding *ae) 192 { 193 struct sunxi_codec_softc * const sc = priv; 194 195 return auconv_query_encoding(sc->sc_encodings, ae); 196 } 197 198 static int 199 sunxi_codec_set_params(void *priv, int setmode, int usemode, 200 audio_params_t *play, audio_params_t *rec, 201 stream_filter_list_t *pfil, stream_filter_list_t *rfil) 202 { 203 struct sunxi_codec_softc * const sc = priv; 204 int index; 205 206 if (play && (setmode & AUMODE_PLAY)) { 207 index = auconv_set_converter(&sc->sc_format, 1, 208 AUMODE_PLAY, play, true, pfil); 209 if (index < 0) 210 return EINVAL; 211 sc->sc_pchan.ch_params = pfil->req_size > 0 ? 212 pfil->filters[0].param : *play; 213 } 214 if (rec && (setmode & AUMODE_RECORD)) { 215 index = auconv_set_converter(&sc->sc_format, 1, 216 AUMODE_RECORD, rec, true, rfil); 217 if (index < 0) 218 return EINVAL; 219 sc->sc_rchan.ch_params = rfil->req_size > 0 ? 220 rfil->filters[0].param : *rec; 221 } 222 223 return 0; 224 } 225 226 static int 227 sunxi_codec_set_port(void *priv, mixer_ctrl_t *mc) 228 { 229 struct sunxi_codec_softc * const sc = priv; 230 231 return sc->sc_cfg->set_port(sc, mc); 232 } 233 234 static int 235 sunxi_codec_get_port(void *priv, mixer_ctrl_t *mc) 236 { 237 struct sunxi_codec_softc * const sc = priv; 238 239 return sc->sc_cfg->get_port(sc, mc); 240 } 241 242 static int 243 sunxi_codec_query_devinfo(void *priv, mixer_devinfo_t *di) 244 { 245 struct sunxi_codec_softc * const sc = priv; 246 247 return sc->sc_cfg->query_devinfo(sc, di); 248 } 249 250 static void * 251 sunxi_codec_allocm(void *priv, int dir, size_t size) 252 { 253 struct sunxi_codec_softc * const sc = priv; 254 struct sunxi_codec_dma *dma; 255 int error; 256 257 dma = kmem_alloc(sizeof(*dma), KM_SLEEP); 258 259 error = sunxi_codec_allocdma(sc, size, 16, dma); 260 if (error) { 261 kmem_free(dma, sizeof(*dma)); 262 device_printf(sc->sc_dev, "couldn't allocate DMA memory (%d)\n", 263 error); 264 return NULL; 265 } 266 267 LIST_INSERT_HEAD(&sc->sc_dmalist, dma, dma_list); 268 269 return dma->dma_addr; 270 } 271 272 static void 273 sunxi_codec_freem(void *priv, void *addr, size_t size) 274 { 275 struct sunxi_codec_softc * const sc = priv; 276 struct sunxi_codec_dma *dma; 277 278 LIST_FOREACH(dma, &sc->sc_dmalist, dma_list) 279 if (dma->dma_addr == addr) { 280 sunxi_codec_freedma(sc, dma); 281 LIST_REMOVE(dma, dma_list); 282 kmem_free(dma, sizeof(*dma)); 283 break; 284 } 285 } 286 287 static paddr_t 288 sunxi_codec_mappage(void *priv, void *addr, off_t off, int prot) 289 { 290 struct sunxi_codec_softc * const sc = priv; 291 struct sunxi_codec_dma *dma; 292 293 if (off < 0) 294 return -1; 295 296 LIST_FOREACH(dma, &sc->sc_dmalist, dma_list) 297 if (dma->dma_addr == addr) { 298 return bus_dmamem_mmap(sc->sc_dmat, dma->dma_segs, 299 dma->dma_nsegs, off, prot, BUS_DMA_WAITOK); 300 } 301 302 return -1; 303 } 304 305 static int 306 sunxi_codec_getdev(void *priv, struct audio_device *adev) 307 { 308 struct sunxi_codec_softc * const sc = priv; 309 310 snprintf(adev->name, sizeof(adev->name), "Allwinner"); 311 snprintf(adev->version, sizeof(adev->version), "%s", 312 sc->sc_cfg->name); 313 snprintf(adev->config, sizeof(adev->config), "sunxicodec"); 314 315 return 0; 316 } 317 318 static int 319 sunxi_codec_get_props(void *priv) 320 { 321 return AUDIO_PROP_PLAYBACK|AUDIO_PROP_CAPTURE| 322 AUDIO_PROP_INDEPENDENT|AUDIO_PROP_MMAP| 323 AUDIO_PROP_FULLDUPLEX; 324 } 325 326 static int 327 sunxi_codec_round_blocksize(void *priv, int bs, int mode, 328 const audio_params_t *params) 329 { 330 bs &= ~3; 331 if (bs == 0) 332 bs = 4; 333 return bs; 334 } 335 336 static size_t 337 sunxi_codec_round_buffersize(void *priv, int dir, size_t bufsize) 338 { 339 return bufsize; 340 } 341 342 static int 343 sunxi_codec_trigger_output(void *priv, void *start, void *end, int blksize, 344 void (*intr)(void *), void *intrarg, const audio_params_t *params) 345 { 346 struct sunxi_codec_softc * const sc = priv; 347 struct sunxi_codec_chan *ch = &sc->sc_pchan; 348 struct sunxi_codec_dma *dma; 349 bus_addr_t pstart; 350 bus_size_t psize; 351 uint32_t val; 352 int error; 353 354 pstart = 0; 355 psize = (uintptr_t)end - (uintptr_t)start; 356 357 LIST_FOREACH(dma, &sc->sc_dmalist, dma_list) 358 if (dma->dma_addr == start) { 359 pstart = dma->dma_map->dm_segs[0].ds_addr; 360 break; 361 } 362 if (pstart == 0) { 363 device_printf(sc->sc_dev, "bad addr %p\n", start); 364 return EINVAL; 365 } 366 367 ch->ch_intr = intr; 368 ch->ch_intrarg = intrarg; 369 ch->ch_start_phys = ch->ch_cur_phys = pstart; 370 ch->ch_end_phys = pstart + psize; 371 ch->ch_blksize = blksize; 372 373 /* Flush DAC FIFO */ 374 val = CODEC_READ(sc, AC_DAC_FIFOC(sc)); 375 CODEC_WRITE(sc, AC_DAC_FIFOC(sc), val | DAC_FIFOC_FIFO_FLUSH); 376 377 /* Clear DAC FIFO status */ 378 val = CODEC_READ(sc, AC_DAC_FIFOS(sc)); 379 CODEC_WRITE(sc, AC_DAC_FIFOS(sc), val); 380 381 /* Unmute output */ 382 if (sc->sc_cfg->mute) 383 sc->sc_cfg->mute(sc, 0, ch->ch_mode); 384 385 /* Configure DAC FIFO */ 386 CODEC_WRITE(sc, AC_DAC_FIFOC(sc), 387 __SHIFTIN(DAC_FS_48KHZ, DAC_FIFOC_FS) | 388 __SHIFTIN(FIFO_MODE_16_15_0, DAC_FIFOC_FIFO_MODE) | 389 __SHIFTIN(DRQ_CLR_CNT, DAC_FIFOC_DRQ_CLR_CNT) | 390 __SHIFTIN(TX_TRIG_LEVEL, DAC_FIFOC_TX_TRIG_LEVEL)); 391 392 /* Enable DAC DRQ */ 393 val = CODEC_READ(sc, AC_DAC_FIFOC(sc)); 394 CODEC_WRITE(sc, AC_DAC_FIFOC(sc), val | DAC_FIFOC_DRQ_EN); 395 396 /* Start DMA transfer */ 397 error = sunxi_codec_transfer(ch); 398 if (error != 0) { 399 aprint_error_dev(sc->sc_dev, 400 "failed to start DMA transfer: %d\n", error); 401 return error; 402 } 403 404 return 0; 405 } 406 407 static int 408 sunxi_codec_trigger_input(void *priv, void *start, void *end, int blksize, 409 void (*intr)(void *), void *intrarg, const audio_params_t *params) 410 { 411 struct sunxi_codec_softc * const sc = priv; 412 struct sunxi_codec_chan *ch = &sc->sc_rchan; 413 struct sunxi_codec_dma *dma; 414 bus_addr_t pstart; 415 bus_size_t psize; 416 uint32_t val; 417 int error; 418 419 pstart = 0; 420 psize = (uintptr_t)end - (uintptr_t)start; 421 422 LIST_FOREACH(dma, &sc->sc_dmalist, dma_list) 423 if (dma->dma_addr == start) { 424 pstart = dma->dma_map->dm_segs[0].ds_addr; 425 break; 426 } 427 if (pstart == 0) { 428 device_printf(sc->sc_dev, "bad addr %p\n", start); 429 return EINVAL; 430 } 431 432 ch->ch_intr = intr; 433 ch->ch_intrarg = intrarg; 434 ch->ch_start_phys = ch->ch_cur_phys = pstart; 435 ch->ch_end_phys = pstart + psize; 436 ch->ch_blksize = blksize; 437 438 /* Flush ADC FIFO */ 439 val = CODEC_READ(sc, AC_ADC_FIFOC(sc)); 440 CODEC_WRITE(sc, AC_ADC_FIFOC(sc), val | ADC_FIFOC_FIFO_FLUSH); 441 442 /* Clear ADC FIFO status */ 443 val = CODEC_READ(sc, AC_ADC_FIFOS(sc)); 444 CODEC_WRITE(sc, AC_ADC_FIFOS(sc), val); 445 446 /* Unmute input */ 447 if (sc->sc_cfg->mute) 448 sc->sc_cfg->mute(sc, 0, ch->ch_mode); 449 450 /* Configure ADC FIFO */ 451 CODEC_WRITE(sc, AC_ADC_FIFOC(sc), 452 __SHIFTIN(ADC_FS_48KHZ, ADC_FIFOC_FS) | 453 __SHIFTIN(RX_TRIG_LEVEL, ADC_FIFOC_RX_TRIG_LEVEL) | 454 ADC_FIFOC_EN_AD | ADC_FIFOC_RX_FIFO_MODE); 455 456 /* Enable ADC DRQ */ 457 val = CODEC_READ(sc, AC_ADC_FIFOC(sc)); 458 CODEC_WRITE(sc, AC_ADC_FIFOC(sc), val | ADC_FIFOC_DRQ_EN); 459 460 /* Start DMA transfer */ 461 error = sunxi_codec_transfer(ch); 462 if (error != 0) { 463 aprint_error_dev(sc->sc_dev, 464 "failed to start DMA transfer: %d\n", error); 465 return error; 466 } 467 468 return 0; 469 } 470 471 static int 472 sunxi_codec_halt_output(void *priv) 473 { 474 struct sunxi_codec_softc * const sc = priv; 475 struct sunxi_codec_chan *ch = &sc->sc_pchan; 476 uint32_t val; 477 478 /* Disable DMA channel */ 479 fdtbus_dma_halt(ch->ch_dma); 480 481 /* Mute output */ 482 if (sc->sc_cfg->mute) 483 sc->sc_cfg->mute(sc, 1, ch->ch_mode); 484 485 /* Disable DAC DRQ */ 486 val = CODEC_READ(sc, AC_DAC_FIFOC(sc)); 487 CODEC_WRITE(sc, AC_DAC_FIFOC(sc), val & ~DAC_FIFOC_DRQ_EN); 488 489 ch->ch_intr = NULL; 490 ch->ch_intrarg = NULL; 491 492 return 0; 493 } 494 495 static int 496 sunxi_codec_halt_input(void *priv) 497 { 498 struct sunxi_codec_softc * const sc = priv; 499 struct sunxi_codec_chan *ch = &sc->sc_rchan; 500 uint32_t val; 501 502 /* Disable DMA channel */ 503 fdtbus_dma_halt(ch->ch_dma); 504 505 /* Mute output */ 506 if (sc->sc_cfg->mute) 507 sc->sc_cfg->mute(sc, 1, ch->ch_mode); 508 509 /* Disable ADC DRQ */ 510 val = CODEC_READ(sc, AC_ADC_FIFOC(sc)); 511 CODEC_WRITE(sc, AC_ADC_FIFOC(sc), val & ~ADC_FIFOC_DRQ_EN); 512 513 return 0; 514 } 515 516 static void 517 sunxi_codec_get_locks(void *priv, kmutex_t **intr, kmutex_t **thread) 518 { 519 struct sunxi_codec_softc * const sc = priv; 520 521 *intr = &sc->sc_intr_lock; 522 *thread = &sc->sc_lock; 523 } 524 525 static const struct audio_hw_if sunxi_codec_hw_if = { 526 .open = sunxi_codec_open, 527 .close = sunxi_codec_close, 528 .drain = sunxi_codec_drain, 529 .query_encoding = sunxi_codec_query_encoding, 530 .set_params = sunxi_codec_set_params, 531 .allocm = sunxi_codec_allocm, 532 .freem = sunxi_codec_freem, 533 .mappage = sunxi_codec_mappage, 534 .getdev = sunxi_codec_getdev, 535 .set_port = sunxi_codec_set_port, 536 .get_port = sunxi_codec_get_port, 537 .query_devinfo = sunxi_codec_query_devinfo, 538 .get_props = sunxi_codec_get_props, 539 .round_blocksize = sunxi_codec_round_blocksize, 540 .round_buffersize = sunxi_codec_round_buffersize, 541 .trigger_output = sunxi_codec_trigger_output, 542 .trigger_input = sunxi_codec_trigger_input, 543 .halt_output = sunxi_codec_halt_output, 544 .halt_input = sunxi_codec_halt_input, 545 .get_locks = sunxi_codec_get_locks, 546 }; 547 548 static void 549 sunxi_codec_dmaintr(void *priv) 550 { 551 struct sunxi_codec_chan * const ch = priv; 552 553 ch->ch_cur_phys += ch->ch_blksize; 554 if (ch->ch_cur_phys >= ch->ch_end_phys) 555 ch->ch_cur_phys = ch->ch_start_phys; 556 557 if (ch->ch_intr) { 558 ch->ch_intr(ch->ch_intrarg); 559 sunxi_codec_transfer(ch); 560 } 561 } 562 563 static int 564 sunxi_codec_chan_init(struct sunxi_codec_softc *sc, 565 struct sunxi_codec_chan *ch, u_int mode, const char *dmaname) 566 { 567 ch->ch_sc = sc; 568 ch->ch_mode = mode; 569 ch->ch_dma = fdtbus_dma_get(sc->sc_phandle, dmaname, sunxi_codec_dmaintr, ch); 570 if (ch->ch_dma == NULL) { 571 aprint_error(": couldn't get dma channel \"%s\"\n", dmaname); 572 return ENXIO; 573 } 574 575 if (mode == AUMODE_PLAY) { 576 ch->ch_req.dreq_dir = FDT_DMA_WRITE; 577 ch->ch_req.dreq_dev_phys = 578 sc->sc_baseaddr + AC_DAC_TXDATA(sc); 579 } else { 580 ch->ch_req.dreq_dir = FDT_DMA_READ; 581 ch->ch_req.dreq_dev_phys = 582 sc->sc_baseaddr + AC_ADC_RXDATA(sc); 583 } 584 ch->ch_req.dreq_mem_opt.opt_bus_width = 16; 585 ch->ch_req.dreq_mem_opt.opt_burst_len = 4; 586 ch->ch_req.dreq_dev_opt.opt_bus_width = 16; 587 ch->ch_req.dreq_dev_opt.opt_burst_len = 4; 588 589 return 0; 590 } 591 592 static int 593 sunxi_codec_clock_init(int phandle) 594 { 595 struct fdtbus_reset *rst; 596 struct clk *clk; 597 int error; 598 599 /* Set codec clock to 24.576MHz, suitable for 48 kHz sampling rates */ 600 clk = fdtbus_clock_get(phandle, "codec"); 601 if (clk == NULL) { 602 aprint_error(": couldn't find codec clock\n"); 603 return ENXIO; 604 } 605 error = clk_set_rate(clk, 24576000); 606 if (error != 0) { 607 aprint_error(": couldn't set codec clock rate: %d\n", error); 608 return error; 609 } 610 error = clk_enable(clk); 611 if (error != 0) { 612 aprint_error(": couldn't enable codec clock: %d\n", error); 613 return error; 614 } 615 616 /* Enable APB clock */ 617 clk = fdtbus_clock_get(phandle, "apb"); 618 if (clk == NULL) { 619 aprint_error(": couldn't find apb clock\n"); 620 return ENXIO; 621 } 622 error = clk_enable(clk); 623 if (error != 0) { 624 aprint_error(": couldn't enable apb clock: %d\n", error); 625 return error; 626 } 627 628 /* De-assert reset */ 629 rst = fdtbus_reset_get_index(phandle, 0); 630 if (rst != NULL) { 631 error = fdtbus_reset_deassert(rst); 632 if (error != 0) { 633 aprint_error(": couldn't de-assert reset: %d\n", error); 634 return error; 635 } 636 } 637 638 return 0; 639 } 640 641 static int 642 sunxi_codec_match(device_t parent, cfdata_t cf, void *aux) 643 { 644 struct fdt_attach_args * const faa = aux; 645 646 return of_match_compat_data(faa->faa_phandle, compat_data); 647 } 648 649 static void 650 sunxi_codec_attach(device_t parent, device_t self, void *aux) 651 { 652 struct sunxi_codec_softc * const sc = device_private(self); 653 struct fdt_attach_args * const faa = aux; 654 const int phandle = faa->faa_phandle; 655 bus_addr_t addr; 656 bus_size_t size; 657 uint32_t val; 658 int error; 659 660 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 661 aprint_error(": couldn't get registers\n"); 662 return; 663 } 664 665 if (sunxi_codec_clock_init(phandle) != 0) 666 return; 667 668 sc->sc_dev = self; 669 sc->sc_phandle = phandle; 670 sc->sc_baseaddr = addr; 671 sc->sc_bst = faa->faa_bst; 672 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 673 aprint_error(": couldn't map registers\n"); 674 return; 675 } 676 sc->sc_dmat = faa->faa_dmat; 677 LIST_INIT(&sc->sc_dmalist); 678 sc->sc_cfg = (void *)of_search_compatible(phandle, compat_data)->data; 679 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE); 680 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 681 682 if (sunxi_codec_chan_init(sc, &sc->sc_pchan, AUMODE_PLAY, "tx") != 0 || 683 sunxi_codec_chan_init(sc, &sc->sc_rchan, AUMODE_RECORD, "rx") != 0) { 684 aprint_error(": couldn't setup channels\n"); 685 return; 686 } 687 688 /* Optional PA mute GPIO */ 689 sc->sc_pin_pa = fdtbus_gpio_acquire(phandle, "allwinner,pa-gpios", GPIO_PIN_OUTPUT); 690 if (sc->sc_pin_pa != NULL) 691 fdtbus_gpio_write(sc->sc_pin_pa, 1); 692 693 aprint_naive("\n"); 694 aprint_normal(": %s\n", sc->sc_cfg->name); 695 696 /* Enable DAC */ 697 val = CODEC_READ(sc, AC_DAC_DPC(sc)); 698 val |= DAC_DPC_EN_DA; 699 CODEC_WRITE(sc, AC_DAC_DPC(sc), val); 700 701 /* Initialize codec */ 702 if (sc->sc_cfg->init(sc) != 0) { 703 aprint_error_dev(self, "couldn't initialize codec\n"); 704 return; 705 } 706 707 sc->sc_format.mode = AUMODE_PLAY|AUMODE_RECORD; 708 sc->sc_format.encoding = AUDIO_ENCODING_SLINEAR_LE; 709 sc->sc_format.validbits = 16; 710 sc->sc_format.precision = 16; 711 sc->sc_format.channels = 2; 712 sc->sc_format.channel_mask = AUFMT_STEREO; 713 sc->sc_format.frequency_type = 0; 714 sc->sc_format.frequency[0] = sc->sc_format.frequency[1] = 48000; 715 716 error = auconv_create_encodings(&sc->sc_format, 1, &sc->sc_encodings); 717 if (error) { 718 aprint_error_dev(self, "couldn't create encodings\n"); 719 return; 720 } 721 722 audio_attach_mi(&sunxi_codec_hw_if, sc, self); 723 } 724 725 CFATTACH_DECL_NEW(sunxi_codec, sizeof(struct sunxi_codec_softc), 726 sunxi_codec_match, sunxi_codec_attach, NULL, NULL); 727 728 #ifdef DDB 729 void sunxicodec_dump(void); 730 731 void 732 sunxicodec_dump(void) 733 { 734 struct sunxi_codec_softc *sc; 735 device_t dev; 736 737 dev = device_find_by_driver_unit("sunxicodec", 0); 738 if (dev == NULL) 739 return; 740 sc = device_private(dev); 741 742 device_printf(dev, "AC_DAC_DPC: %08x\n", CODEC_READ(sc, AC_DAC_DPC(sc))); 743 device_printf(dev, "AC_DAC_FIFOC: %08x\n", CODEC_READ(sc, AC_DAC_FIFOC(sc))); 744 device_printf(dev, "AC_DAC_FIFOS: %08x\n", CODEC_READ(sc, AC_DAC_FIFOS(sc))); 745 device_printf(dev, "AC_ADC_FIFOC: %08x\n", CODEC_READ(sc, AC_ADC_FIFOC(sc))); 746 device_printf(dev, "AC_ADC_FIFOS: %08x\n", CODEC_READ(sc, AC_ADC_FIFOS(sc))); 747 device_printf(dev, "AC_DAC_CNT: %08x\n", CODEC_READ(sc, AC_DAC_CNT(sc))); 748 device_printf(dev, "AC_ADC_CNT: %08x\n", CODEC_READ(sc, AC_ADC_CNT(sc))); 749 } 750 #endif 751
Indexes created Thu Sep 25 08:09:54 GMT 2025