sunxi_codec.c revision 1.2.2.2
1 /* $NetBSD: sunxi_codec.c,v 1.2.2.2 2017/08/28 17:51:32 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2014-2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_ddb.h" 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: sunxi_codec.c,v 1.2.2.2 2017/08/28 17:51:32 skrll Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/cpu.h> 37 #include <sys/device.h> 38 #include <sys/kmem.h> 39 #include <sys/gpio.h> 40 41 #include <sys/audioio.h> 42 #include <dev/audio_if.h> 43 #include <dev/auconv.h> 44 45 #include <dev/fdt/fdtvar.h> 46 47 #include <arm/sunxi/sunxi_codec.h> 48 49 #define TX_TRIG_LEVEL 0xf 50 #define RX_TRIG_LEVEL 0x7 51 #define DRQ_CLR_CNT 0x3 52 53 #define AC_DAC_DPC(_sc) ((_sc)->sc_cfg->DPC) 54 #define DAC_DPC_EN_DA 0x80000000 55 #define AC_DAC_FIFOC(_sc) ((_sc)->sc_cfg->DAC_FIFOC) 56 #define DAC_FIFOC_FS __BITS(31,29) 57 #define DAC_FS_48KHZ 0 58 #define DAC_FS_32KHZ 1 59 #define DAC_FS_24KHZ 2 60 #define DAC_FS_16KHZ 3 61 #define DAC_FS_12KHZ 4 62 #define DAC_FS_8KHZ 5 63 #define DAC_FS_192KHZ 6 64 #define DAC_FS_96KHZ 7 65 #define DAC_FIFOC_FIFO_MODE __BITS(25,24) 66 #define FIFO_MODE_24_31_8 0 67 #define FIFO_MODE_16_31_16 0 68 #define FIFO_MODE_16_15_0 1 69 #define DAC_FIFOC_DRQ_CLR_CNT __BITS(22,21) 70 #define DAC_FIFOC_TX_TRIG_LEVEL __BITS(14,8) 71 #define DAC_FIFOC_MONO_EN __BIT(6) 72 #define DAC_FIFOC_TX_BITS __BIT(5) 73 #define DAC_FIFOC_DRQ_EN __BIT(4) 74 #define DAC_FIFOC_FIFO_FLUSH __BIT(0) 75 #define AC_DAC_FIFOS(_sc) ((_sc)->sc_cfg->DAC_FIFOS) 76 #define AC_DAC_TXDATA(_sc) ((_sc)->sc_cfg->DAC_TXDATA) 77 #define AC_ADC_FIFOC(_sc) ((_sc)->sc_cfg->ADC_FIFOC) 78 #define ADC_FIFOC_FS __BITS(31,29) 79 #define ADC_FS_48KHZ 0 80 #define ADC_FIFOC_EN_AD __BIT(28) 81 #define ADC_FIFOC_RX_FIFO_MODE __BIT(24) 82 #define ADC_FIFOC_RX_TRIG_LEVEL __BITS(12,8) 83 #define ADC_FIFOC_MONO_EN __BIT(7) 84 #define ADC_FIFOC_RX_BITS __BIT(6) 85 #define ADC_FIFOC_DRQ_EN __BIT(4) 86 #define ADC_FIFOC_FIFO_FLUSH __BIT(0) 87 #define AC_ADC_FIFOS(_sc) ((_sc)->sc_cfg->ADC_FIFOS) 88 #define AC_ADC_RXDATA(_sc) ((_sc)->sc_cfg->ADC_RXDATA) 89 #define AC_DAC_CNT(_sc) ((_sc)->sc_cfg->DAC_CNT) 90 #define AC_ADC_CNT(_sc) ((_sc)->sc_cfg->ADC_CNT) 91 92 static const struct of_compat_data compat_data[] = { 93 H3_CODEC_COMPATDATA, 94 { NULL } 95 }; 96 97 #define CODEC_READ(sc, reg) \ 98 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 99 #define CODEC_WRITE(sc, reg, val) \ 100 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 101 102 static int 103 sunxi_codec_allocdma(struct sunxi_codec_softc *sc, size_t size, 104 size_t align, struct sunxi_codec_dma *dma) 105 { 106 int error; 107 108 dma->dma_size = size; 109 error = bus_dmamem_alloc(sc->sc_dmat, dma->dma_size, align, 0, 110 dma->dma_segs, 1, &dma->dma_nsegs, BUS_DMA_WAITOK); 111 if (error) 112 return error; 113 114 error = bus_dmamem_map(sc->sc_dmat, dma->dma_segs, dma->dma_nsegs, 115 dma->dma_size, &dma->dma_addr, BUS_DMA_WAITOK | BUS_DMA_COHERENT); 116 if (error) 117 goto free; 118 119 error = bus_dmamap_create(sc->sc_dmat, dma->dma_size, dma->dma_nsegs, 120 dma->dma_size, 0, BUS_DMA_WAITOK, &dma->dma_map); 121 if (error) 122 goto unmap; 123 124 error = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_addr, 125 dma->dma_size, NULL, BUS_DMA_WAITOK); 126 if (error) 127 goto destroy; 128 129 return 0; 130 131 destroy: 132 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 133 unmap: 134 bus_dmamem_unmap(sc->sc_dmat, dma->dma_addr, dma->dma_size); 135 free: 136 bus_dmamem_free(sc->sc_dmat, dma->dma_segs, dma->dma_nsegs); 137 138 return error; 139 } 140 141 static void 142 sunxi_codec_freedma(struct sunxi_codec_softc *sc, struct sunxi_codec_dma *dma) 143 { 144 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 145 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 146 bus_dmamem_unmap(sc->sc_dmat, dma->dma_addr, dma->dma_size); 147 bus_dmamem_free(sc->sc_dmat, dma->dma_segs, dma->dma_nsegs); 148 } 149 150 static int 151 sunxi_codec_transfer(struct sunxi_codec_chan *ch) 152 { 153 bus_dma_segment_t seg; 154 155 seg.ds_addr = ch->ch_cur_phys; 156 seg.ds_len = ch->ch_blksize; 157 ch->ch_req.dreq_segs = &seg; 158 ch->ch_req.dreq_nsegs = 1; 159 160 return fdtbus_dma_transfer(ch->ch_dma, &ch->ch_req); 161 } 162 163 static int 164 sunxi_codec_open(void *priv, int flags) 165 { 166 return 0; 167 } 168 169 static void 170 sunxi_codec_close(void *priv) 171 { 172 } 173 174 static int 175 sunxi_codec_drain(void *priv) 176 { 177 struct sunxi_codec_softc * const sc = priv; 178 uint32_t val; 179 180 val = CODEC_READ(sc, AC_DAC_FIFOC(sc)); 181 CODEC_WRITE(sc, AC_DAC_FIFOC(sc), val | DAC_FIFOC_FIFO_FLUSH); 182 183 val = CODEC_READ(sc, AC_ADC_FIFOC(sc)); 184 CODEC_WRITE(sc, AC_ADC_FIFOC(sc), val | ADC_FIFOC_FIFO_FLUSH); 185 186 return 0; 187 } 188 189 static int 190 sunxi_codec_query_encoding(void *priv, struct audio_encoding *ae) 191 { 192 struct sunxi_codec_softc * const sc = priv; 193 194 return auconv_query_encoding(sc->sc_encodings, ae); 195 } 196 197 static int 198 sunxi_codec_set_params(void *priv, int setmode, int usemode, 199 audio_params_t *play, audio_params_t *rec, 200 stream_filter_list_t *pfil, stream_filter_list_t *rfil) 201 { 202 struct sunxi_codec_softc * const sc = priv; 203 int index; 204 205 if (play && (setmode & AUMODE_PLAY)) { 206 index = auconv_set_converter(&sc->sc_format, 1, 207 AUMODE_PLAY, play, true, pfil); 208 if (index < 0) 209 return EINVAL; 210 sc->sc_pchan.ch_params = pfil->req_size > 0 ? 211 pfil->filters[0].param : *play; 212 } 213 if (rec && (setmode & AUMODE_RECORD)) { 214 index = auconv_set_converter(&sc->sc_format, 1, 215 AUMODE_RECORD, rec, true, rfil); 216 if (index < 0) 217 return EINVAL; 218 sc->sc_rchan.ch_params = rfil->req_size > 0 ? 219 rfil->filters[0].param : *rec; 220 } 221 222 return 0; 223 } 224 225 static int 226 sunxi_codec_set_port(void *priv, mixer_ctrl_t *mc) 227 { 228 struct sunxi_codec_softc * const sc = priv; 229 230 return sc->sc_cfg->set_port(sc, mc); 231 } 232 233 static int 234 sunxi_codec_get_port(void *priv, mixer_ctrl_t *mc) 235 { 236 struct sunxi_codec_softc * const sc = priv; 237 238 return sc->sc_cfg->get_port(sc, mc); 239 } 240 241 static int 242 sunxi_codec_query_devinfo(void *priv, mixer_devinfo_t *di) 243 { 244 struct sunxi_codec_softc * const sc = priv; 245 246 return sc->sc_cfg->query_devinfo(sc, di); 247 } 248 249 static void * 250 sunxi_codec_allocm(void *priv, int dir, size_t size) 251 { 252 struct sunxi_codec_softc * const sc = priv; 253 struct sunxi_codec_dma *dma; 254 int error; 255 256 dma = kmem_alloc(sizeof(*dma), KM_SLEEP); 257 258 error = sunxi_codec_allocdma(sc, size, 16, dma); 259 if (error) { 260 kmem_free(dma, sizeof(*dma)); 261 device_printf(sc->sc_dev, "couldn't allocate DMA memory (%d)\n", 262 error); 263 return NULL; 264 } 265 266 LIST_INSERT_HEAD(&sc->sc_dmalist, dma, dma_list); 267 268 return dma->dma_addr; 269 } 270 271 static void 272 sunxi_codec_freem(void *priv, void *addr, size_t size) 273 { 274 struct sunxi_codec_softc * const sc = priv; 275 struct sunxi_codec_dma *dma; 276 277 LIST_FOREACH(dma, &sc->sc_dmalist, dma_list) 278 if (dma->dma_addr == addr) { 279 sunxi_codec_freedma(sc, dma); 280 LIST_REMOVE(dma, dma_list); 281 kmem_free(dma, sizeof(*dma)); 282 break; 283 } 284 } 285 286 static paddr_t 287 sunxi_codec_mappage(void *priv, void *addr, off_t off, int prot) 288 { 289 struct sunxi_codec_softc * const sc = priv; 290 struct sunxi_codec_dma *dma; 291 292 if (off < 0) 293 return -1; 294 295 LIST_FOREACH(dma, &sc->sc_dmalist, dma_list) 296 if (dma->dma_addr == addr) { 297 return bus_dmamem_mmap(sc->sc_dmat, dma->dma_segs, 298 dma->dma_nsegs, off, prot, BUS_DMA_WAITOK); 299 } 300 301 return -1; 302 } 303 304 static int 305 sunxi_codec_getdev(void *priv, struct audio_device *adev) 306 { 307 struct sunxi_codec_softc * const sc = priv; 308 309 snprintf(adev->name, sizeof(adev->name), "Allwinner"); 310 snprintf(adev->version, sizeof(adev->version), "%s", 311 sc->sc_cfg->name); 312 snprintf(adev->config, sizeof(adev->config), "sunxicodec"); 313 314 return 0; 315 } 316 317 static int 318 sunxi_codec_get_props(void *priv) 319 { 320 return AUDIO_PROP_PLAYBACK|AUDIO_PROP_CAPTURE| 321 AUDIO_PROP_INDEPENDENT|AUDIO_PROP_MMAP| 322 AUDIO_PROP_FULLDUPLEX; 323 } 324 325 static int 326 sunxi_codec_round_blocksize(void *priv, int bs, int mode, 327 const audio_params_t *params) 328 { 329 bs &= ~3; 330 if (bs == 0) 331 bs = 4; 332 return bs; 333 } 334 335 static size_t 336 sunxi_codec_round_buffersize(void *priv, int dir, size_t bufsize) 337 { 338 return bufsize; 339 } 340 341 static int 342 sunxi_codec_trigger_output(void *priv, void *start, void *end, int blksize, 343 void (*intr)(void *), void *intrarg, const audio_params_t *params) 344 { 345 struct sunxi_codec_softc * const sc = priv; 346 struct sunxi_codec_chan *ch = &sc->sc_pchan; 347 struct sunxi_codec_dma *dma; 348 bus_addr_t pstart; 349 bus_size_t psize; 350 uint32_t val; 351 int error; 352 353 pstart = 0; 354 psize = (uintptr_t)end - (uintptr_t)start; 355 356 LIST_FOREACH(dma, &sc->sc_dmalist, dma_list) 357 if (dma->dma_addr == start) { 358 pstart = dma->dma_map->dm_segs[0].ds_addr; 359 break; 360 } 361 if (pstart == 0) { 362 device_printf(sc->sc_dev, "bad addr %p\n", start); 363 return EINVAL; 364 } 365 366 ch->ch_intr = intr; 367 ch->ch_intrarg = intrarg; 368 ch->ch_start_phys = ch->ch_cur_phys = pstart; 369 ch->ch_end_phys = pstart + psize; 370 ch->ch_blksize = blksize; 371 372 /* Flush DAC FIFO */ 373 val = CODEC_READ(sc, AC_DAC_FIFOC(sc)); 374 CODEC_WRITE(sc, AC_DAC_FIFOC(sc), val | DAC_FIFOC_FIFO_FLUSH); 375 376 /* Clear DAC FIFO status */ 377 val = CODEC_READ(sc, AC_DAC_FIFOS(sc)); 378 CODEC_WRITE(sc, AC_DAC_FIFOS(sc), val); 379 380 /* Unmute output */ 381 if (sc->sc_cfg->mute) 382 sc->sc_cfg->mute(sc, 0, ch->ch_mode); 383 384 /* Configure DAC FIFO */ 385 CODEC_WRITE(sc, AC_DAC_FIFOC(sc), 386 __SHIFTIN(DAC_FS_48KHZ, DAC_FIFOC_FS) | 387 __SHIFTIN(FIFO_MODE_16_15_0, DAC_FIFOC_FIFO_MODE) | 388 __SHIFTIN(DRQ_CLR_CNT, DAC_FIFOC_DRQ_CLR_CNT) | 389 __SHIFTIN(TX_TRIG_LEVEL, DAC_FIFOC_TX_TRIG_LEVEL)); 390 391 /* Enable DAC DRQ */ 392 val = CODEC_READ(sc, AC_DAC_FIFOC(sc)); 393 CODEC_WRITE(sc, AC_DAC_FIFOC(sc), val | DAC_FIFOC_DRQ_EN); 394 395 /* Start DMA transfer */ 396 error = sunxi_codec_transfer(ch); 397 if (error != 0) { 398 aprint_error_dev(sc->sc_dev, 399 "failed to start DMA transfer: %d\n", error); 400 return error; 401 } 402 403 return 0; 404 } 405 406 static int 407 sunxi_codec_trigger_input(void *priv, void *start, void *end, int blksize, 408 void (*intr)(void *), void *intrarg, const audio_params_t *params) 409 { 410 struct sunxi_codec_softc * const sc = priv; 411 struct sunxi_codec_chan *ch = &sc->sc_rchan; 412 struct sunxi_codec_dma *dma; 413 bus_addr_t pstart; 414 bus_size_t psize; 415 uint32_t val; 416 int error; 417 418 pstart = 0; 419 psize = (uintptr_t)end - (uintptr_t)start; 420 421 LIST_FOREACH(dma, &sc->sc_dmalist, dma_list) 422 if (dma->dma_addr == start) { 423 pstart = dma->dma_map->dm_segs[0].ds_addr; 424 break; 425 } 426 if (pstart == 0) { 427 device_printf(sc->sc_dev, "bad addr %p\n", start); 428 return EINVAL; 429 } 430 431 ch->ch_intr = intr; 432 ch->ch_intrarg = intrarg; 433 ch->ch_start_phys = ch->ch_cur_phys = pstart; 434 ch->ch_end_phys = pstart + psize; 435 ch->ch_blksize = blksize; 436 437 /* Flush ADC FIFO */ 438 val = CODEC_READ(sc, AC_ADC_FIFOC(sc)); 439 CODEC_WRITE(sc, AC_ADC_FIFOC(sc), val | ADC_FIFOC_FIFO_FLUSH); 440 441 /* Clear ADC FIFO status */ 442 val = CODEC_READ(sc, AC_ADC_FIFOS(sc)); 443 CODEC_WRITE(sc, AC_ADC_FIFOS(sc), val); 444 445 /* Unmute input */ 446 if (sc->sc_cfg->mute) 447 sc->sc_cfg->mute(sc, 0, ch->ch_mode); 448 449 /* Configure ADC FIFO */ 450 CODEC_WRITE(sc, AC_ADC_FIFOC(sc), 451 __SHIFTIN(ADC_FS_48KHZ, ADC_FIFOC_FS) | 452 __SHIFTIN(RX_TRIG_LEVEL, ADC_FIFOC_RX_TRIG_LEVEL) | 453 ADC_FIFOC_EN_AD | ADC_FIFOC_RX_FIFO_MODE); 454 455 /* Enable ADC DRQ */ 456 val = CODEC_READ(sc, AC_ADC_FIFOC(sc)); 457 CODEC_WRITE(sc, AC_ADC_FIFOC(sc), val | ADC_FIFOC_DRQ_EN); 458 459 /* Start DMA transfer */ 460 error = sunxi_codec_transfer(ch); 461 if (error != 0) { 462 aprint_error_dev(sc->sc_dev, 463 "failed to start DMA transfer: %d\n", error); 464 return error; 465 } 466 467 return 0; 468 } 469 470 static int 471 sunxi_codec_halt_output(void *priv) 472 { 473 struct sunxi_codec_softc * const sc = priv; 474 struct sunxi_codec_chan *ch = &sc->sc_pchan; 475 uint32_t val; 476 477 /* Disable DMA channel */ 478 fdtbus_dma_halt(ch->ch_dma); 479 480 /* Mute output */ 481 if (sc->sc_cfg->mute) 482 sc->sc_cfg->mute(sc, 1, ch->ch_mode); 483 484 /* Disable DAC DRQ */ 485 val = CODEC_READ(sc, AC_DAC_FIFOC(sc)); 486 CODEC_WRITE(sc, AC_DAC_FIFOC(sc), val & ~DAC_FIFOC_DRQ_EN); 487 488 ch->ch_intr = NULL; 489 ch->ch_intrarg = NULL; 490 491 return 0; 492 } 493 494 static int 495 sunxi_codec_halt_input(void *priv) 496 { 497 struct sunxi_codec_softc * const sc = priv; 498 struct sunxi_codec_chan *ch = &sc->sc_rchan; 499 uint32_t val; 500 501 /* Disable DMA channel */ 502 fdtbus_dma_halt(ch->ch_dma); 503 504 /* Mute output */ 505 if (sc->sc_cfg->mute) 506 sc->sc_cfg->mute(sc, 1, ch->ch_mode); 507 508 /* Disable ADC DRQ */ 509 val = CODEC_READ(sc, AC_ADC_FIFOC(sc)); 510 CODEC_WRITE(sc, AC_ADC_FIFOC(sc), val & ~ADC_FIFOC_DRQ_EN); 511 512 return 0; 513 } 514 515 static void 516 sunxi_codec_get_locks(void *priv, kmutex_t **intr, kmutex_t **thread) 517 { 518 struct sunxi_codec_softc * const sc = priv; 519 520 *intr = &sc->sc_intr_lock; 521 *thread = &sc->sc_lock; 522 } 523 524 static const struct audio_hw_if sunxi_codec_hw_if = { 525 .open = sunxi_codec_open, 526 .close = sunxi_codec_close, 527 .drain = sunxi_codec_drain, 528 .query_encoding = sunxi_codec_query_encoding, 529 .set_params = sunxi_codec_set_params, 530 .allocm = sunxi_codec_allocm, 531 .freem = sunxi_codec_freem, 532 .mappage = sunxi_codec_mappage, 533 .getdev = sunxi_codec_getdev, 534 .set_port = sunxi_codec_set_port, 535 .get_port = sunxi_codec_get_port, 536 .query_devinfo = sunxi_codec_query_devinfo, 537 .get_props = sunxi_codec_get_props, 538 .round_blocksize = sunxi_codec_round_blocksize, 539 .round_buffersize = sunxi_codec_round_buffersize, 540 .trigger_output = sunxi_codec_trigger_output, 541 .trigger_input = sunxi_codec_trigger_input, 542 .halt_output = sunxi_codec_halt_output, 543 .halt_input = sunxi_codec_halt_input, 544 .get_locks = sunxi_codec_get_locks, 545 }; 546 547 static void 548 sunxi_codec_dmaintr(void *priv) 549 { 550 struct sunxi_codec_chan * const ch = priv; 551 552 ch->ch_cur_phys += ch->ch_blksize; 553 if (ch->ch_cur_phys >= ch->ch_end_phys) 554 ch->ch_cur_phys = ch->ch_start_phys; 555 556 if (ch->ch_intr) { 557 ch->ch_intr(ch->ch_intrarg); 558 sunxi_codec_transfer(ch); 559 } 560 } 561 562 static int 563 sunxi_codec_chan_init(struct sunxi_codec_softc *sc, 564 struct sunxi_codec_chan *ch, u_int mode, const char *dmaname) 565 { 566 ch->ch_sc = sc; 567 ch->ch_mode = mode; 568 ch->ch_dma = fdtbus_dma_get(sc->sc_phandle, dmaname, sunxi_codec_dmaintr, ch); 569 if (ch->ch_dma == NULL) { 570 aprint_error(": couldn't get dma channel \"%s\"\n", dmaname); 571 return ENXIO; 572 } 573 574 if (mode == AUMODE_PLAY) { 575 ch->ch_req.dreq_dir = FDT_DMA_WRITE; 576 ch->ch_req.dreq_dev_phys = 577 sc->sc_baseaddr + AC_DAC_TXDATA(sc); 578 } else { 579 ch->ch_req.dreq_dir = FDT_DMA_READ; 580 ch->ch_req.dreq_dev_phys = 581 sc->sc_baseaddr + AC_ADC_RXDATA(sc); 582 } 583 ch->ch_req.dreq_mem_opt.opt_bus_width = 16; 584 ch->ch_req.dreq_mem_opt.opt_burst_len = 4; 585 ch->ch_req.dreq_dev_opt.opt_bus_width = 16; 586 ch->ch_req.dreq_dev_opt.opt_burst_len = 4; 587 588 return 0; 589 } 590 591 static int 592 sunxi_codec_clock_init(int phandle) 593 { 594 struct fdtbus_reset *rst; 595 struct clk *clk; 596 int error; 597 598 /* Set codec clock to 24.576MHz, suitable for 48 kHz sampling rates */ 599 clk = fdtbus_clock_get(phandle, "codec"); 600 if (clk == NULL) { 601 aprint_error(": couldn't find codec clock\n"); 602 return ENXIO; 603 } 604 error = clk_set_rate(clk, 24576000); 605 if (error != 0) { 606 aprint_error(": couldn't set codec clock rate: %d\n", error); 607 return error; 608 } 609 error = clk_enable(clk); 610 if (error != 0) { 611 aprint_error(": couldn't enable codec clock: %d\n", error); 612 return error; 613 } 614 615 /* Enable APB clock */ 616 clk = fdtbus_clock_get(phandle, "apb"); 617 if (clk == NULL) { 618 aprint_error(": couldn't find apb clock\n"); 619 return ENXIO; 620 } 621 error = clk_enable(clk); 622 if (error != 0) { 623 aprint_error(": couldn't enable apb clock: %d\n", error); 624 return error; 625 } 626 627 /* De-assert reset */ 628 rst = fdtbus_reset_get_index(phandle, 0); 629 if (rst == NULL) { 630 aprint_error(": couldn't find reset\n"); 631 return ENXIO; 632 } 633 error = fdtbus_reset_deassert(rst); 634 if (error != 0) { 635 aprint_error(": couldn't de-assert reset: %d\n", error); 636 return error; 637 } 638 639 return 0; 640 } 641 642 static int 643 sunxi_codec_match(device_t parent, cfdata_t cf, void *aux) 644 { 645 struct fdt_attach_args * const faa = aux; 646 647 return of_match_compat_data(faa->faa_phandle, compat_data); 648 } 649 650 static void 651 sunxi_codec_attach(device_t parent, device_t self, void *aux) 652 { 653 struct sunxi_codec_softc * const sc = device_private(self); 654 struct fdt_attach_args * const faa = aux; 655 const int phandle = faa->faa_phandle; 656 bus_addr_t addr; 657 bus_size_t size; 658 uint32_t val; 659 int error; 660 661 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 662 aprint_error(": couldn't get registers\n"); 663 return; 664 } 665 666 if (sunxi_codec_clock_init(phandle) != 0) 667 return; 668 669 sc->sc_dev = self; 670 sc->sc_phandle = phandle; 671 sc->sc_baseaddr = addr; 672 sc->sc_bst = faa->faa_bst; 673 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 674 aprint_error(": couldn't map registers\n"); 675 return; 676 } 677 sc->sc_dmat = faa->faa_dmat; 678 LIST_INIT(&sc->sc_dmalist); 679 sc->sc_cfg = (void *)of_search_compatible(phandle, compat_data)->data; 680 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE); 681 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 682 683 if (sunxi_codec_chan_init(sc, &sc->sc_pchan, AUMODE_PLAY, "tx") != 0 || 684 sunxi_codec_chan_init(sc, &sc->sc_rchan, AUMODE_RECORD, "rx") != 0) { 685 aprint_error(": couldn't setup channels\n"); 686 return; 687 } 688 689 /* Optional PA mute GPIO */ 690 sc->sc_pin_pa = fdtbus_gpio_acquire(phandle, "allwinner,pa-gpios", GPIO_PIN_OUTPUT); 691 if (sc->sc_pin_pa != NULL) 692 fdtbus_gpio_write(sc->sc_pin_pa, 1); 693 694 aprint_naive("\n"); 695 aprint_normal(": %s\n", sc->sc_cfg->name); 696 697 /* Enable DAC */ 698 val = CODEC_READ(sc, AC_DAC_DPC(sc)); 699 val |= DAC_DPC_EN_DA; 700 CODEC_WRITE(sc, AC_DAC_DPC(sc), val); 701 702 /* Initialize codec */ 703 if (sc->sc_cfg->init(sc) != 0) { 704 aprint_error_dev(self, "couldn't initialize codec\n"); 705 return; 706 } 707 708 sc->sc_format.mode = AUMODE_PLAY|AUMODE_RECORD; 709 sc->sc_format.encoding = AUDIO_ENCODING_SLINEAR_LE; 710 sc->sc_format.validbits = 16; 711 sc->sc_format.precision = 16; 712 sc->sc_format.channels = 2; 713 sc->sc_format.channel_mask = AUFMT_STEREO; 714 sc->sc_format.frequency_type = 0; 715 sc->sc_format.frequency[0] = sc->sc_format.frequency[1] = 48000; 716 717 error = auconv_create_encodings(&sc->sc_format, 1, &sc->sc_encodings); 718 if (error) { 719 aprint_error_dev(self, "couldn't create encodings\n"); 720 return; 721 } 722 723 audio_attach_mi(&sunxi_codec_hw_if, sc, self); 724 } 725 726 CFATTACH_DECL_NEW(sunxi_codec, sizeof(struct sunxi_codec_softc), 727 sunxi_codec_match, sunxi_codec_attach, NULL, NULL); 728 729 #ifdef DDB 730 void sunxicodec_dump(void); 731 732 void 733 sunxicodec_dump(void) 734 { 735 struct sunxi_codec_softc *sc; 736 device_t dev; 737 738 dev = device_find_by_driver_unit("sunxicodec", 0); 739 if (dev == NULL) 740 return; 741 sc = device_private(dev); 742 743 device_printf(dev, "AC_DAC_DPC: %08x\n", CODEC_READ(sc, AC_DAC_DPC(sc))); 744 device_printf(dev, "AC_DAC_FIFOC: %08x\n", CODEC_READ(sc, AC_DAC_FIFOC(sc))); 745 device_printf(dev, "AC_DAC_FIFOS: %08x\n", CODEC_READ(sc, AC_DAC_FIFOS(sc))); 746 device_printf(dev, "AC_ADC_FIFOC: %08x\n", CODEC_READ(sc, AC_ADC_FIFOC(sc))); 747 device_printf(dev, "AC_ADC_FIFOS: %08x\n", CODEC_READ(sc, AC_ADC_FIFOS(sc))); 748 device_printf(dev, "AC_DAC_CNT: %08x\n", CODEC_READ(sc, AC_DAC_CNT(sc))); 749 device_printf(dev, "AC_ADC_CNT: %08x\n", CODEC_READ(sc, AC_ADC_CNT(sc))); 750 } 751 #endif 752
Indexes created Fri Oct 17 03:10:13 GMT 2025