sunxi_codec.c revision 1.3
1 /* $NetBSD: sunxi_codec.c,v 1.3 2017/10/07 21:53:16 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2014-2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_ddb.h" 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: sunxi_codec.c,v 1.3 2017/10/07 21:53:16 jmcneill Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/cpu.h> 37 #include <sys/device.h> 38 #include <sys/kmem.h> 39 #include <sys/gpio.h> 40 41 #include <sys/audioio.h> 42 #include <dev/audio_if.h> 43 #include <dev/auconv.h> 44 45 #include <dev/fdt/fdtvar.h> 46 47 #include <arm/sunxi/sunxi_codec.h> 48 49 #define TX_TRIG_LEVEL 0xf 50 #define RX_TRIG_LEVEL 0x7 51 #define DRQ_CLR_CNT 0x3 52 53 #define AC_DAC_DPC(_sc) ((_sc)->sc_cfg->DPC) 54 #define DAC_DPC_EN_DA 0x80000000 55 #define AC_DAC_FIFOC(_sc) ((_sc)->sc_cfg->DAC_FIFOC) 56 #define DAC_FIFOC_FS __BITS(31,29) 57 #define DAC_FS_48KHZ 0 58 #define DAC_FS_32KHZ 1 59 #define DAC_FS_24KHZ 2 60 #define DAC_FS_16KHZ 3 61 #define DAC_FS_12KHZ 4 62 #define DAC_FS_8KHZ 5 63 #define DAC_FS_192KHZ 6 64 #define DAC_FS_96KHZ 7 65 #define DAC_FIFOC_FIFO_MODE __BITS(25,24) 66 #define FIFO_MODE_24_31_8 0 67 #define FIFO_MODE_16_31_16 0 68 #define FIFO_MODE_16_15_0 1 69 #define DAC_FIFOC_DRQ_CLR_CNT __BITS(22,21) 70 #define DAC_FIFOC_TX_TRIG_LEVEL __BITS(14,8) 71 #define DAC_FIFOC_MONO_EN __BIT(6) 72 #define DAC_FIFOC_TX_BITS __BIT(5) 73 #define DAC_FIFOC_DRQ_EN __BIT(4) 74 #define DAC_FIFOC_FIFO_FLUSH __BIT(0) 75 #define AC_DAC_FIFOS(_sc) ((_sc)->sc_cfg->DAC_FIFOS) 76 #define AC_DAC_TXDATA(_sc) ((_sc)->sc_cfg->DAC_TXDATA) 77 #define AC_ADC_FIFOC(_sc) ((_sc)->sc_cfg->ADC_FIFOC) 78 #define ADC_FIFOC_FS __BITS(31,29) 79 #define ADC_FS_48KHZ 0 80 #define ADC_FIFOC_EN_AD __BIT(28) 81 #define ADC_FIFOC_RX_FIFO_MODE __BIT(24) 82 #define ADC_FIFOC_RX_TRIG_LEVEL __BITS(12,8) 83 #define ADC_FIFOC_MONO_EN __BIT(7) 84 #define ADC_FIFOC_RX_BITS __BIT(6) 85 #define ADC_FIFOC_DRQ_EN __BIT(4) 86 #define ADC_FIFOC_FIFO_FLUSH __BIT(0) 87 #define AC_ADC_FIFOS(_sc) ((_sc)->sc_cfg->ADC_FIFOS) 88 #define AC_ADC_RXDATA(_sc) ((_sc)->sc_cfg->ADC_RXDATA) 89 #define AC_DAC_CNT(_sc) ((_sc)->sc_cfg->DAC_CNT) 90 #define AC_ADC_CNT(_sc) ((_sc)->sc_cfg->ADC_CNT) 91 92 static const struct of_compat_data compat_data[] = { 93 A10_CODEC_COMPATDATA, 94 A31_CODEC_COMPATDATA, 95 H3_CODEC_COMPATDATA, 96 { NULL } 97 }; 98 99 #define CODEC_READ(sc, reg) \ 100 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 101 #define CODEC_WRITE(sc, reg, val) \ 102 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 103 104 static int 105 sunxi_codec_allocdma(struct sunxi_codec_softc *sc, size_t size, 106 size_t align, struct sunxi_codec_dma *dma) 107 { 108 int error; 109 110 dma->dma_size = size; 111 error = bus_dmamem_alloc(sc->sc_dmat, dma->dma_size, align, 0, 112 dma->dma_segs, 1, &dma->dma_nsegs, BUS_DMA_WAITOK); 113 if (error) 114 return error; 115 116 error = bus_dmamem_map(sc->sc_dmat, dma->dma_segs, dma->dma_nsegs, 117 dma->dma_size, &dma->dma_addr, BUS_DMA_WAITOK | BUS_DMA_COHERENT); 118 if (error) 119 goto free; 120 121 error = bus_dmamap_create(sc->sc_dmat, dma->dma_size, dma->dma_nsegs, 122 dma->dma_size, 0, BUS_DMA_WAITOK, &dma->dma_map); 123 if (error) 124 goto unmap; 125 126 error = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_addr, 127 dma->dma_size, NULL, BUS_DMA_WAITOK); 128 if (error) 129 goto destroy; 130 131 return 0; 132 133 destroy: 134 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 135 unmap: 136 bus_dmamem_unmap(sc->sc_dmat, dma->dma_addr, dma->dma_size); 137 free: 138 bus_dmamem_free(sc->sc_dmat, dma->dma_segs, dma->dma_nsegs); 139 140 return error; 141 } 142 143 static void 144 sunxi_codec_freedma(struct sunxi_codec_softc *sc, struct sunxi_codec_dma *dma) 145 { 146 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 147 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 148 bus_dmamem_unmap(sc->sc_dmat, dma->dma_addr, dma->dma_size); 149 bus_dmamem_free(sc->sc_dmat, dma->dma_segs, dma->dma_nsegs); 150 } 151 152 static int 153 sunxi_codec_transfer(struct sunxi_codec_chan *ch) 154 { 155 bus_dma_segment_t seg; 156 157 seg.ds_addr = ch->ch_cur_phys; 158 seg.ds_len = ch->ch_blksize; 159 ch->ch_req.dreq_segs = &seg; 160 ch->ch_req.dreq_nsegs = 1; 161 162 return fdtbus_dma_transfer(ch->ch_dma, &ch->ch_req); 163 } 164 165 static int 166 sunxi_codec_open(void *priv, int flags) 167 { 168 return 0; 169 } 170 171 static void 172 sunxi_codec_close(void *priv) 173 { 174 } 175 176 static int 177 sunxi_codec_drain(void *priv) 178 { 179 struct sunxi_codec_softc * const sc = priv; 180 uint32_t val; 181 182 val = CODEC_READ(sc, AC_DAC_FIFOC(sc)); 183 CODEC_WRITE(sc, AC_DAC_FIFOC(sc), val | DAC_FIFOC_FIFO_FLUSH); 184 185 val = CODEC_READ(sc, AC_ADC_FIFOC(sc)); 186 CODEC_WRITE(sc, AC_ADC_FIFOC(sc), val | ADC_FIFOC_FIFO_FLUSH); 187 188 return 0; 189 } 190 191 static int 192 sunxi_codec_query_encoding(void *priv, struct audio_encoding *ae) 193 { 194 struct sunxi_codec_softc * const sc = priv; 195 196 return auconv_query_encoding(sc->sc_encodings, ae); 197 } 198 199 static int 200 sunxi_codec_set_params(void *priv, int setmode, int usemode, 201 audio_params_t *play, audio_params_t *rec, 202 stream_filter_list_t *pfil, stream_filter_list_t *rfil) 203 { 204 struct sunxi_codec_softc * const sc = priv; 205 int index; 206 207 if (play && (setmode & AUMODE_PLAY)) { 208 index = auconv_set_converter(&sc->sc_format, 1, 209 AUMODE_PLAY, play, true, pfil); 210 if (index < 0) 211 return EINVAL; 212 sc->sc_pchan.ch_params = pfil->req_size > 0 ? 213 pfil->filters[0].param : *play; 214 } 215 if (rec && (setmode & AUMODE_RECORD)) { 216 index = auconv_set_converter(&sc->sc_format, 1, 217 AUMODE_RECORD, rec, true, rfil); 218 if (index < 0) 219 return EINVAL; 220 sc->sc_rchan.ch_params = rfil->req_size > 0 ? 221 rfil->filters[0].param : *rec; 222 } 223 224 return 0; 225 } 226 227 static int 228 sunxi_codec_set_port(void *priv, mixer_ctrl_t *mc) 229 { 230 struct sunxi_codec_softc * const sc = priv; 231 232 return sc->sc_cfg->set_port(sc, mc); 233 } 234 235 static int 236 sunxi_codec_get_port(void *priv, mixer_ctrl_t *mc) 237 { 238 struct sunxi_codec_softc * const sc = priv; 239 240 return sc->sc_cfg->get_port(sc, mc); 241 } 242 243 static int 244 sunxi_codec_query_devinfo(void *priv, mixer_devinfo_t *di) 245 { 246 struct sunxi_codec_softc * const sc = priv; 247 248 return sc->sc_cfg->query_devinfo(sc, di); 249 } 250 251 static void * 252 sunxi_codec_allocm(void *priv, int dir, size_t size) 253 { 254 struct sunxi_codec_softc * const sc = priv; 255 struct sunxi_codec_dma *dma; 256 int error; 257 258 dma = kmem_alloc(sizeof(*dma), KM_SLEEP); 259 260 error = sunxi_codec_allocdma(sc, size, 16, dma); 261 if (error) { 262 kmem_free(dma, sizeof(*dma)); 263 device_printf(sc->sc_dev, "couldn't allocate DMA memory (%d)\n", 264 error); 265 return NULL; 266 } 267 268 LIST_INSERT_HEAD(&sc->sc_dmalist, dma, dma_list); 269 270 return dma->dma_addr; 271 } 272 273 static void 274 sunxi_codec_freem(void *priv, void *addr, size_t size) 275 { 276 struct sunxi_codec_softc * const sc = priv; 277 struct sunxi_codec_dma *dma; 278 279 LIST_FOREACH(dma, &sc->sc_dmalist, dma_list) 280 if (dma->dma_addr == addr) { 281 sunxi_codec_freedma(sc, dma); 282 LIST_REMOVE(dma, dma_list); 283 kmem_free(dma, sizeof(*dma)); 284 break; 285 } 286 } 287 288 static paddr_t 289 sunxi_codec_mappage(void *priv, void *addr, off_t off, int prot) 290 { 291 struct sunxi_codec_softc * const sc = priv; 292 struct sunxi_codec_dma *dma; 293 294 if (off < 0) 295 return -1; 296 297 LIST_FOREACH(dma, &sc->sc_dmalist, dma_list) 298 if (dma->dma_addr == addr) { 299 return bus_dmamem_mmap(sc->sc_dmat, dma->dma_segs, 300 dma->dma_nsegs, off, prot, BUS_DMA_WAITOK); 301 } 302 303 return -1; 304 } 305 306 static int 307 sunxi_codec_getdev(void *priv, struct audio_device *adev) 308 { 309 struct sunxi_codec_softc * const sc = priv; 310 311 snprintf(adev->name, sizeof(adev->name), "Allwinner"); 312 snprintf(adev->version, sizeof(adev->version), "%s", 313 sc->sc_cfg->name); 314 snprintf(adev->config, sizeof(adev->config), "sunxicodec"); 315 316 return 0; 317 } 318 319 static int 320 sunxi_codec_get_props(void *priv) 321 { 322 return AUDIO_PROP_PLAYBACK|AUDIO_PROP_CAPTURE| 323 AUDIO_PROP_INDEPENDENT|AUDIO_PROP_MMAP| 324 AUDIO_PROP_FULLDUPLEX; 325 } 326 327 static int 328 sunxi_codec_round_blocksize(void *priv, int bs, int mode, 329 const audio_params_t *params) 330 { 331 bs &= ~3; 332 if (bs == 0) 333 bs = 4; 334 return bs; 335 } 336 337 static size_t 338 sunxi_codec_round_buffersize(void *priv, int dir, size_t bufsize) 339 { 340 return bufsize; 341 } 342 343 static int 344 sunxi_codec_trigger_output(void *priv, void *start, void *end, int blksize, 345 void (*intr)(void *), void *intrarg, const audio_params_t *params) 346 { 347 struct sunxi_codec_softc * const sc = priv; 348 struct sunxi_codec_chan *ch = &sc->sc_pchan; 349 struct sunxi_codec_dma *dma; 350 bus_addr_t pstart; 351 bus_size_t psize; 352 uint32_t val; 353 int error; 354 355 pstart = 0; 356 psize = (uintptr_t)end - (uintptr_t)start; 357 358 LIST_FOREACH(dma, &sc->sc_dmalist, dma_list) 359 if (dma->dma_addr == start) { 360 pstart = dma->dma_map->dm_segs[0].ds_addr; 361 break; 362 } 363 if (pstart == 0) { 364 device_printf(sc->sc_dev, "bad addr %p\n", start); 365 return EINVAL; 366 } 367 368 ch->ch_intr = intr; 369 ch->ch_intrarg = intrarg; 370 ch->ch_start_phys = ch->ch_cur_phys = pstart; 371 ch->ch_end_phys = pstart + psize; 372 ch->ch_blksize = blksize; 373 374 /* Flush DAC FIFO */ 375 val = CODEC_READ(sc, AC_DAC_FIFOC(sc)); 376 CODEC_WRITE(sc, AC_DAC_FIFOC(sc), val | DAC_FIFOC_FIFO_FLUSH); 377 378 /* Clear DAC FIFO status */ 379 val = CODEC_READ(sc, AC_DAC_FIFOS(sc)); 380 CODEC_WRITE(sc, AC_DAC_FIFOS(sc), val); 381 382 /* Unmute output */ 383 if (sc->sc_cfg->mute) 384 sc->sc_cfg->mute(sc, 0, ch->ch_mode); 385 386 /* Configure DAC FIFO */ 387 CODEC_WRITE(sc, AC_DAC_FIFOC(sc), 388 __SHIFTIN(DAC_FS_48KHZ, DAC_FIFOC_FS) | 389 __SHIFTIN(FIFO_MODE_16_15_0, DAC_FIFOC_FIFO_MODE) | 390 __SHIFTIN(DRQ_CLR_CNT, DAC_FIFOC_DRQ_CLR_CNT) | 391 __SHIFTIN(TX_TRIG_LEVEL, DAC_FIFOC_TX_TRIG_LEVEL)); 392 393 /* Enable DAC DRQ */ 394 val = CODEC_READ(sc, AC_DAC_FIFOC(sc)); 395 CODEC_WRITE(sc, AC_DAC_FIFOC(sc), val | DAC_FIFOC_DRQ_EN); 396 397 /* Start DMA transfer */ 398 error = sunxi_codec_transfer(ch); 399 if (error != 0) { 400 aprint_error_dev(sc->sc_dev, 401 "failed to start DMA transfer: %d\n", error); 402 return error; 403 } 404 405 return 0; 406 } 407 408 static int 409 sunxi_codec_trigger_input(void *priv, void *start, void *end, int blksize, 410 void (*intr)(void *), void *intrarg, const audio_params_t *params) 411 { 412 struct sunxi_codec_softc * const sc = priv; 413 struct sunxi_codec_chan *ch = &sc->sc_rchan; 414 struct sunxi_codec_dma *dma; 415 bus_addr_t pstart; 416 bus_size_t psize; 417 uint32_t val; 418 int error; 419 420 pstart = 0; 421 psize = (uintptr_t)end - (uintptr_t)start; 422 423 LIST_FOREACH(dma, &sc->sc_dmalist, dma_list) 424 if (dma->dma_addr == start) { 425 pstart = dma->dma_map->dm_segs[0].ds_addr; 426 break; 427 } 428 if (pstart == 0) { 429 device_printf(sc->sc_dev, "bad addr %p\n", start); 430 return EINVAL; 431 } 432 433 ch->ch_intr = intr; 434 ch->ch_intrarg = intrarg; 435 ch->ch_start_phys = ch->ch_cur_phys = pstart; 436 ch->ch_end_phys = pstart + psize; 437 ch->ch_blksize = blksize; 438 439 /* Flush ADC FIFO */ 440 val = CODEC_READ(sc, AC_ADC_FIFOC(sc)); 441 CODEC_WRITE(sc, AC_ADC_FIFOC(sc), val | ADC_FIFOC_FIFO_FLUSH); 442 443 /* Clear ADC FIFO status */ 444 val = CODEC_READ(sc, AC_ADC_FIFOS(sc)); 445 CODEC_WRITE(sc, AC_ADC_FIFOS(sc), val); 446 447 /* Unmute input */ 448 if (sc->sc_cfg->mute) 449 sc->sc_cfg->mute(sc, 0, ch->ch_mode); 450 451 /* Configure ADC FIFO */ 452 CODEC_WRITE(sc, AC_ADC_FIFOC(sc), 453 __SHIFTIN(ADC_FS_48KHZ, ADC_FIFOC_FS) | 454 __SHIFTIN(RX_TRIG_LEVEL, ADC_FIFOC_RX_TRIG_LEVEL) | 455 ADC_FIFOC_EN_AD | ADC_FIFOC_RX_FIFO_MODE); 456 457 /* Enable ADC DRQ */ 458 val = CODEC_READ(sc, AC_ADC_FIFOC(sc)); 459 CODEC_WRITE(sc, AC_ADC_FIFOC(sc), val | ADC_FIFOC_DRQ_EN); 460 461 /* Start DMA transfer */ 462 error = sunxi_codec_transfer(ch); 463 if (error != 0) { 464 aprint_error_dev(sc->sc_dev, 465 "failed to start DMA transfer: %d\n", error); 466 return error; 467 } 468 469 return 0; 470 } 471 472 static int 473 sunxi_codec_halt_output(void *priv) 474 { 475 struct sunxi_codec_softc * const sc = priv; 476 struct sunxi_codec_chan *ch = &sc->sc_pchan; 477 uint32_t val; 478 479 /* Disable DMA channel */ 480 fdtbus_dma_halt(ch->ch_dma); 481 482 /* Mute output */ 483 if (sc->sc_cfg->mute) 484 sc->sc_cfg->mute(sc, 1, ch->ch_mode); 485 486 /* Disable DAC DRQ */ 487 val = CODEC_READ(sc, AC_DAC_FIFOC(sc)); 488 CODEC_WRITE(sc, AC_DAC_FIFOC(sc), val & ~DAC_FIFOC_DRQ_EN); 489 490 ch->ch_intr = NULL; 491 ch->ch_intrarg = NULL; 492 493 return 0; 494 } 495 496 static int 497 sunxi_codec_halt_input(void *priv) 498 { 499 struct sunxi_codec_softc * const sc = priv; 500 struct sunxi_codec_chan *ch = &sc->sc_rchan; 501 uint32_t val; 502 503 /* Disable DMA channel */ 504 fdtbus_dma_halt(ch->ch_dma); 505 506 /* Mute output */ 507 if (sc->sc_cfg->mute) 508 sc->sc_cfg->mute(sc, 1, ch->ch_mode); 509 510 /* Disable ADC DRQ */ 511 val = CODEC_READ(sc, AC_ADC_FIFOC(sc)); 512 CODEC_WRITE(sc, AC_ADC_FIFOC(sc), val & ~ADC_FIFOC_DRQ_EN); 513 514 return 0; 515 } 516 517 static void 518 sunxi_codec_get_locks(void *priv, kmutex_t **intr, kmutex_t **thread) 519 { 520 struct sunxi_codec_softc * const sc = priv; 521 522 *intr = &sc->sc_intr_lock; 523 *thread = &sc->sc_lock; 524 } 525 526 static const struct audio_hw_if sunxi_codec_hw_if = { 527 .open = sunxi_codec_open, 528 .close = sunxi_codec_close, 529 .drain = sunxi_codec_drain, 530 .query_encoding = sunxi_codec_query_encoding, 531 .set_params = sunxi_codec_set_params, 532 .allocm = sunxi_codec_allocm, 533 .freem = sunxi_codec_freem, 534 .mappage = sunxi_codec_mappage, 535 .getdev = sunxi_codec_getdev, 536 .set_port = sunxi_codec_set_port, 537 .get_port = sunxi_codec_get_port, 538 .query_devinfo = sunxi_codec_query_devinfo, 539 .get_props = sunxi_codec_get_props, 540 .round_blocksize = sunxi_codec_round_blocksize, 541 .round_buffersize = sunxi_codec_round_buffersize, 542 .trigger_output = sunxi_codec_trigger_output, 543 .trigger_input = sunxi_codec_trigger_input, 544 .halt_output = sunxi_codec_halt_output, 545 .halt_input = sunxi_codec_halt_input, 546 .get_locks = sunxi_codec_get_locks, 547 }; 548 549 static void 550 sunxi_codec_dmaintr(void *priv) 551 { 552 struct sunxi_codec_chan * const ch = priv; 553 554 ch->ch_cur_phys += ch->ch_blksize; 555 if (ch->ch_cur_phys >= ch->ch_end_phys) 556 ch->ch_cur_phys = ch->ch_start_phys; 557 558 if (ch->ch_intr) { 559 ch->ch_intr(ch->ch_intrarg); 560 sunxi_codec_transfer(ch); 561 } 562 } 563 564 static int 565 sunxi_codec_chan_init(struct sunxi_codec_softc *sc, 566 struct sunxi_codec_chan *ch, u_int mode, const char *dmaname) 567 { 568 ch->ch_sc = sc; 569 ch->ch_mode = mode; 570 ch->ch_dma = fdtbus_dma_get(sc->sc_phandle, dmaname, sunxi_codec_dmaintr, ch); 571 if (ch->ch_dma == NULL) { 572 aprint_error(": couldn't get dma channel \"%s\"\n", dmaname); 573 return ENXIO; 574 } 575 576 if (mode == AUMODE_PLAY) { 577 ch->ch_req.dreq_dir = FDT_DMA_WRITE; 578 ch->ch_req.dreq_dev_phys = 579 sc->sc_baseaddr + AC_DAC_TXDATA(sc); 580 } else { 581 ch->ch_req.dreq_dir = FDT_DMA_READ; 582 ch->ch_req.dreq_dev_phys = 583 sc->sc_baseaddr + AC_ADC_RXDATA(sc); 584 } 585 ch->ch_req.dreq_mem_opt.opt_bus_width = 16; 586 ch->ch_req.dreq_mem_opt.opt_burst_len = 4; 587 ch->ch_req.dreq_dev_opt.opt_bus_width = 16; 588 ch->ch_req.dreq_dev_opt.opt_burst_len = 4; 589 590 return 0; 591 } 592 593 static int 594 sunxi_codec_clock_init(int phandle) 595 { 596 struct fdtbus_reset *rst; 597 struct clk *clk; 598 int error; 599 600 /* Set codec clock to 24.576MHz, suitable for 48 kHz sampling rates */ 601 clk = fdtbus_clock_get(phandle, "codec"); 602 if (clk == NULL) { 603 aprint_error(": couldn't find codec clock\n"); 604 return ENXIO; 605 } 606 error = clk_set_rate(clk, 24576000); 607 if (error != 0) { 608 aprint_error(": couldn't set codec clock rate: %d\n", error); 609 return error; 610 } 611 error = clk_enable(clk); 612 if (error != 0) { 613 aprint_error(": couldn't enable codec clock: %d\n", error); 614 return error; 615 } 616 617 /* Enable APB clock */ 618 clk = fdtbus_clock_get(phandle, "apb"); 619 if (clk == NULL) { 620 aprint_error(": couldn't find apb clock\n"); 621 return ENXIO; 622 } 623 error = clk_enable(clk); 624 if (error != 0) { 625 aprint_error(": couldn't enable apb clock: %d\n", error); 626 return error; 627 } 628 629 /* De-assert reset */ 630 rst = fdtbus_reset_get_index(phandle, 0); 631 if (rst != NULL) { 632 error = fdtbus_reset_deassert(rst); 633 if (error != 0) { 634 aprint_error(": couldn't de-assert reset: %d\n", error); 635 return error; 636 } 637 } 638 639 return 0; 640 } 641 642 static int 643 sunxi_codec_match(device_t parent, cfdata_t cf, void *aux) 644 { 645 struct fdt_attach_args * const faa = aux; 646 647 return of_match_compat_data(faa->faa_phandle, compat_data); 648 } 649 650 static void 651 sunxi_codec_attach(device_t parent, device_t self, void *aux) 652 { 653 struct sunxi_codec_softc * const sc = device_private(self); 654 struct fdt_attach_args * const faa = aux; 655 const int phandle = faa->faa_phandle; 656 bus_addr_t addr; 657 bus_size_t size; 658 uint32_t val; 659 int error; 660 661 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 662 aprint_error(": couldn't get registers\n"); 663 return; 664 } 665 666 if (sunxi_codec_clock_init(phandle) != 0) 667 return; 668 669 sc->sc_dev = self; 670 sc->sc_phandle = phandle; 671 sc->sc_baseaddr = addr; 672 sc->sc_bst = faa->faa_bst; 673 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 674 aprint_error(": couldn't map registers\n"); 675 return; 676 } 677 sc->sc_dmat = faa->faa_dmat; 678 LIST_INIT(&sc->sc_dmalist); 679 sc->sc_cfg = (void *)of_search_compatible(phandle, compat_data)->data; 680 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE); 681 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 682 683 if (sunxi_codec_chan_init(sc, &sc->sc_pchan, AUMODE_PLAY, "tx") != 0 || 684 sunxi_codec_chan_init(sc, &sc->sc_rchan, AUMODE_RECORD, "rx") != 0) { 685 aprint_error(": couldn't setup channels\n"); 686 return; 687 } 688 689 /* Optional PA mute GPIO */ 690 sc->sc_pin_pa = fdtbus_gpio_acquire(phandle, "allwinner,pa-gpios", GPIO_PIN_OUTPUT); 691 if (sc->sc_pin_pa != NULL) 692 fdtbus_gpio_write(sc->sc_pin_pa, 1); 693 694 aprint_naive("\n"); 695 aprint_normal(": %s\n", sc->sc_cfg->name); 696 697 /* Enable DAC */ 698 val = CODEC_READ(sc, AC_DAC_DPC(sc)); 699 val |= DAC_DPC_EN_DA; 700 CODEC_WRITE(sc, AC_DAC_DPC(sc), val); 701 702 /* Initialize codec */ 703 if (sc->sc_cfg->init(sc) != 0) { 704 aprint_error_dev(self, "couldn't initialize codec\n"); 705 return; 706 } 707 708 sc->sc_format.mode = AUMODE_PLAY|AUMODE_RECORD; 709 sc->sc_format.encoding = AUDIO_ENCODING_SLINEAR_LE; 710 sc->sc_format.validbits = 16; 711 sc->sc_format.precision = 16; 712 sc->sc_format.channels = 2; 713 sc->sc_format.channel_mask = AUFMT_STEREO; 714 sc->sc_format.frequency_type = 0; 715 sc->sc_format.frequency[0] = sc->sc_format.frequency[1] = 48000; 716 717 error = auconv_create_encodings(&sc->sc_format, 1, &sc->sc_encodings); 718 if (error) { 719 aprint_error_dev(self, "couldn't create encodings\n"); 720 return; 721 } 722 723 audio_attach_mi(&sunxi_codec_hw_if, sc, self); 724 } 725 726 CFATTACH_DECL_NEW(sunxi_codec, sizeof(struct sunxi_codec_softc), 727 sunxi_codec_match, sunxi_codec_attach, NULL, NULL); 728 729 #ifdef DDB 730 void sunxicodec_dump(void); 731 732 void 733 sunxicodec_dump(void) 734 { 735 struct sunxi_codec_softc *sc; 736 device_t dev; 737 738 dev = device_find_by_driver_unit("sunxicodec", 0); 739 if (dev == NULL) 740 return; 741 sc = device_private(dev); 742 743 device_printf(dev, "AC_DAC_DPC: %08x\n", CODEC_READ(sc, AC_DAC_DPC(sc))); 744 device_printf(dev, "AC_DAC_FIFOC: %08x\n", CODEC_READ(sc, AC_DAC_FIFOC(sc))); 745 device_printf(dev, "AC_DAC_FIFOS: %08x\n", CODEC_READ(sc, AC_DAC_FIFOS(sc))); 746 device_printf(dev, "AC_ADC_FIFOC: %08x\n", CODEC_READ(sc, AC_ADC_FIFOC(sc))); 747 device_printf(dev, "AC_ADC_FIFOS: %08x\n", CODEC_READ(sc, AC_ADC_FIFOS(sc))); 748 device_printf(dev, "AC_DAC_CNT: %08x\n", CODEC_READ(sc, AC_DAC_CNT(sc))); 749 device_printf(dev, "AC_ADC_CNT: %08x\n", CODEC_READ(sc, AC_ADC_CNT(sc))); 750 } 751 #endif 752
Indexes created Wed Sep 24 05:09:52 GMT 2025