sunxi_codec.c revision 1.5
1 /* $NetBSD: sunxi_codec.c,v 1.5 2018/04/20 18:07:40 bouyer Exp $ */ 2 3 /*- 4 * Copyright (c) 2014-2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_ddb.h" 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: sunxi_codec.c,v 1.5 2018/04/20 18:07:40 bouyer Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/cpu.h> 37 #include <sys/device.h> 38 #include <sys/kmem.h> 39 #include <sys/gpio.h> 40 41 #include <sys/audioio.h> 42 #include <dev/audio_if.h> 43 #include <dev/auconv.h> 44 45 #include <dev/fdt/fdtvar.h> 46 47 #include <arm/sunxi/sunxi_codec.h> 48 49 #define TX_TRIG_LEVEL 0xf 50 #define RX_TRIG_LEVEL 0x7 51 #define DRQ_CLR_CNT 0x3 52 53 #define AC_DAC_DPC(_sc) ((_sc)->sc_cfg->DPC) 54 #define DAC_DPC_EN_DA 0x80000000 55 #define AC_DAC_FIFOC(_sc) ((_sc)->sc_cfg->DAC_FIFOC) 56 #define DAC_FIFOC_FS __BITS(31,29) 57 #define DAC_FS_48KHZ 0 58 #define DAC_FS_32KHZ 1 59 #define DAC_FS_24KHZ 2 60 #define DAC_FS_16KHZ 3 61 #define DAC_FS_12KHZ 4 62 #define DAC_FS_8KHZ 5 63 #define DAC_FS_192KHZ 6 64 #define DAC_FS_96KHZ 7 65 #define DAC_FIFOC_FIFO_MODE __BITS(25,24) 66 #define FIFO_MODE_24_31_8 0 67 #define FIFO_MODE_16_31_16 0 68 #define FIFO_MODE_16_15_0 1 69 #define DAC_FIFOC_DRQ_CLR_CNT __BITS(22,21) 70 #define DAC_FIFOC_TX_TRIG_LEVEL __BITS(14,8) 71 #define DAC_FIFOC_MONO_EN __BIT(6) 72 #define DAC_FIFOC_TX_BITS __BIT(5) 73 #define DAC_FIFOC_DRQ_EN __BIT(4) 74 #define DAC_FIFOC_FIFO_FLUSH __BIT(0) 75 #define AC_DAC_FIFOS(_sc) ((_sc)->sc_cfg->DAC_FIFOS) 76 #define AC_DAC_TXDATA(_sc) ((_sc)->sc_cfg->DAC_TXDATA) 77 #define AC_ADC_FIFOC(_sc) ((_sc)->sc_cfg->ADC_FIFOC) 78 #define ADC_FIFOC_FS __BITS(31,29) 79 #define ADC_FS_48KHZ 0 80 #define ADC_FIFOC_EN_AD __BIT(28) 81 #define ADC_FIFOC_RX_FIFO_MODE __BIT(24) 82 #define ADC_FIFOC_RX_TRIG_LEVEL __BITS(12,8) 83 #define ADC_FIFOC_MONO_EN __BIT(7) 84 #define ADC_FIFOC_RX_BITS __BIT(6) 85 #define ADC_FIFOC_DRQ_EN __BIT(4) 86 #define ADC_FIFOC_FIFO_FLUSH __BIT(0) 87 #define AC_ADC_FIFOS(_sc) ((_sc)->sc_cfg->ADC_FIFOS) 88 #define AC_ADC_RXDATA(_sc) ((_sc)->sc_cfg->ADC_RXDATA) 89 #define AC_DAC_CNT(_sc) ((_sc)->sc_cfg->DAC_CNT) 90 #define AC_ADC_CNT(_sc) ((_sc)->sc_cfg->ADC_CNT) 91 92 static const struct of_compat_data compat_data[] = { 93 A10_CODEC_COMPATDATA, 94 A31_CODEC_COMPATDATA, 95 H3_CODEC_COMPATDATA, 96 { NULL } 97 }; 98 99 #define CODEC_READ(sc, reg) \ 100 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 101 #define CODEC_WRITE(sc, reg, val) \ 102 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 103 104 static int 105 sunxi_codec_allocdma(struct sunxi_codec_softc *sc, size_t size, 106 size_t align, struct sunxi_codec_dma *dma) 107 { 108 int error; 109 110 dma->dma_size = size; 111 error = bus_dmamem_alloc(sc->sc_dmat, dma->dma_size, align, 0, 112 dma->dma_segs, 1, &dma->dma_nsegs, BUS_DMA_WAITOK); 113 if (error) 114 return error; 115 116 error = bus_dmamem_map(sc->sc_dmat, dma->dma_segs, dma->dma_nsegs, 117 dma->dma_size, &dma->dma_addr, BUS_DMA_WAITOK | BUS_DMA_COHERENT); 118 if (error) 119 goto free; 120 121 error = bus_dmamap_create(sc->sc_dmat, dma->dma_size, dma->dma_nsegs, 122 dma->dma_size, 0, BUS_DMA_WAITOK, &dma->dma_map); 123 if (error) 124 goto unmap; 125 126 error = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_addr, 127 dma->dma_size, NULL, BUS_DMA_WAITOK); 128 if (error) 129 goto destroy; 130 131 return 0; 132 133 destroy: 134 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 135 unmap: 136 bus_dmamem_unmap(sc->sc_dmat, dma->dma_addr, dma->dma_size); 137 free: 138 bus_dmamem_free(sc->sc_dmat, dma->dma_segs, dma->dma_nsegs); 139 140 return error; 141 } 142 143 static void 144 sunxi_codec_freedma(struct sunxi_codec_softc *sc, struct sunxi_codec_dma *dma) 145 { 146 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 147 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 148 bus_dmamem_unmap(sc->sc_dmat, dma->dma_addr, dma->dma_size); 149 bus_dmamem_free(sc->sc_dmat, dma->dma_segs, dma->dma_nsegs); 150 } 151 152 static int 153 sunxi_codec_transfer(struct sunxi_codec_chan *ch) 154 { 155 bus_dma_segment_t seg; 156 157 seg.ds_addr = ch->ch_cur_phys; 158 seg.ds_len = ch->ch_blksize; 159 ch->ch_req.dreq_segs = &seg; 160 ch->ch_req.dreq_nsegs = 1; 161 162 return fdtbus_dma_transfer(ch->ch_dma, &ch->ch_req); 163 } 164 165 static int 166 sunxi_codec_open(void *priv, int flags) 167 { 168 return 0; 169 } 170 171 static void 172 sunxi_codec_close(void *priv) 173 { 174 } 175 176 static int 177 sunxi_codec_query_encoding(void *priv, struct audio_encoding *ae) 178 { 179 struct sunxi_codec_softc * const sc = priv; 180 181 return auconv_query_encoding(sc->sc_encodings, ae); 182 } 183 184 static int 185 sunxi_codec_set_params(void *priv, int setmode, int usemode, 186 audio_params_t *play, audio_params_t *rec, 187 stream_filter_list_t *pfil, stream_filter_list_t *rfil) 188 { 189 struct sunxi_codec_softc * const sc = priv; 190 int index; 191 192 if (play && (setmode & AUMODE_PLAY)) { 193 index = auconv_set_converter(&sc->sc_format, 1, 194 AUMODE_PLAY, play, true, pfil); 195 if (index < 0) 196 return EINVAL; 197 sc->sc_pchan.ch_params = pfil->req_size > 0 ? 198 pfil->filters[0].param : *play; 199 } 200 if (rec && (setmode & AUMODE_RECORD)) { 201 index = auconv_set_converter(&sc->sc_format, 1, 202 AUMODE_RECORD, rec, true, rfil); 203 if (index < 0) 204 return EINVAL; 205 sc->sc_rchan.ch_params = rfil->req_size > 0 ? 206 rfil->filters[0].param : *rec; 207 } 208 209 return 0; 210 } 211 212 static int 213 sunxi_codec_set_port(void *priv, mixer_ctrl_t *mc) 214 { 215 struct sunxi_codec_softc * const sc = priv; 216 217 return sc->sc_cfg->set_port(sc, mc); 218 } 219 220 static int 221 sunxi_codec_get_port(void *priv, mixer_ctrl_t *mc) 222 { 223 struct sunxi_codec_softc * const sc = priv; 224 225 return sc->sc_cfg->get_port(sc, mc); 226 } 227 228 static int 229 sunxi_codec_query_devinfo(void *priv, mixer_devinfo_t *di) 230 { 231 struct sunxi_codec_softc * const sc = priv; 232 233 return sc->sc_cfg->query_devinfo(sc, di); 234 } 235 236 static void * 237 sunxi_codec_allocm(void *priv, int dir, size_t size) 238 { 239 struct sunxi_codec_softc * const sc = priv; 240 struct sunxi_codec_dma *dma; 241 int error; 242 243 dma = kmem_alloc(sizeof(*dma), KM_SLEEP); 244 245 error = sunxi_codec_allocdma(sc, size, 16, dma); 246 if (error) { 247 kmem_free(dma, sizeof(*dma)); 248 device_printf(sc->sc_dev, "couldn't allocate DMA memory (%d)\n", 249 error); 250 return NULL; 251 } 252 253 LIST_INSERT_HEAD(&sc->sc_dmalist, dma, dma_list); 254 255 return dma->dma_addr; 256 } 257 258 static void 259 sunxi_codec_freem(void *priv, void *addr, size_t size) 260 { 261 struct sunxi_codec_softc * const sc = priv; 262 struct sunxi_codec_dma *dma; 263 264 LIST_FOREACH(dma, &sc->sc_dmalist, dma_list) 265 if (dma->dma_addr == addr) { 266 sunxi_codec_freedma(sc, dma); 267 LIST_REMOVE(dma, dma_list); 268 kmem_free(dma, sizeof(*dma)); 269 break; 270 } 271 } 272 273 static paddr_t 274 sunxi_codec_mappage(void *priv, void *addr, off_t off, int prot) 275 { 276 struct sunxi_codec_softc * const sc = priv; 277 struct sunxi_codec_dma *dma; 278 279 if (off < 0) 280 return -1; 281 282 LIST_FOREACH(dma, &sc->sc_dmalist, dma_list) 283 if (dma->dma_addr == addr) { 284 return bus_dmamem_mmap(sc->sc_dmat, dma->dma_segs, 285 dma->dma_nsegs, off, prot, BUS_DMA_WAITOK); 286 } 287 288 return -1; 289 } 290 291 static int 292 sunxi_codec_getdev(void *priv, struct audio_device *adev) 293 { 294 struct sunxi_codec_softc * const sc = priv; 295 296 snprintf(adev->name, sizeof(adev->name), "Allwinner"); 297 snprintf(adev->version, sizeof(adev->version), "%s", 298 sc->sc_cfg->name); 299 snprintf(adev->config, sizeof(adev->config), "sunxicodec"); 300 301 return 0; 302 } 303 304 static int 305 sunxi_codec_get_props(void *priv) 306 { 307 return AUDIO_PROP_PLAYBACK|AUDIO_PROP_CAPTURE| 308 AUDIO_PROP_INDEPENDENT|AUDIO_PROP_MMAP| 309 AUDIO_PROP_FULLDUPLEX; 310 } 311 312 static int 313 sunxi_codec_round_blocksize(void *priv, int bs, int mode, 314 const audio_params_t *params) 315 { 316 bs &= ~3; 317 if (bs == 0) 318 bs = 4; 319 return bs; 320 } 321 322 static size_t 323 sunxi_codec_round_buffersize(void *priv, int dir, size_t bufsize) 324 { 325 return bufsize; 326 } 327 328 static int 329 sunxi_codec_trigger_output(void *priv, void *start, void *end, int blksize, 330 void (*intr)(void *), void *intrarg, const audio_params_t *params) 331 { 332 struct sunxi_codec_softc * const sc = priv; 333 struct sunxi_codec_chan *ch = &sc->sc_pchan; 334 struct sunxi_codec_dma *dma; 335 bus_addr_t pstart; 336 bus_size_t psize; 337 uint32_t val; 338 int error; 339 340 pstart = 0; 341 psize = (uintptr_t)end - (uintptr_t)start; 342 343 LIST_FOREACH(dma, &sc->sc_dmalist, dma_list) 344 if (dma->dma_addr == start) { 345 pstart = dma->dma_map->dm_segs[0].ds_addr; 346 break; 347 } 348 if (pstart == 0) { 349 device_printf(sc->sc_dev, "bad addr %p\n", start); 350 return EINVAL; 351 } 352 353 ch->ch_intr = intr; 354 ch->ch_intrarg = intrarg; 355 ch->ch_start_phys = ch->ch_cur_phys = pstart; 356 ch->ch_end_phys = pstart + psize; 357 ch->ch_blksize = blksize; 358 359 /* Flush DAC FIFO */ 360 val = CODEC_READ(sc, AC_DAC_FIFOC(sc)); 361 CODEC_WRITE(sc, AC_DAC_FIFOC(sc), val | DAC_FIFOC_FIFO_FLUSH); 362 363 /* Clear DAC FIFO status */ 364 val = CODEC_READ(sc, AC_DAC_FIFOS(sc)); 365 CODEC_WRITE(sc, AC_DAC_FIFOS(sc), val); 366 367 /* Unmute output */ 368 if (sc->sc_cfg->mute) 369 sc->sc_cfg->mute(sc, 0, ch->ch_mode); 370 371 /* Configure DAC FIFO */ 372 CODEC_WRITE(sc, AC_DAC_FIFOC(sc), 373 __SHIFTIN(DAC_FS_48KHZ, DAC_FIFOC_FS) | 374 __SHIFTIN(FIFO_MODE_16_15_0, DAC_FIFOC_FIFO_MODE) | 375 __SHIFTIN(DRQ_CLR_CNT, DAC_FIFOC_DRQ_CLR_CNT) | 376 __SHIFTIN(TX_TRIG_LEVEL, DAC_FIFOC_TX_TRIG_LEVEL)); 377 378 /* Enable DAC DRQ */ 379 val = CODEC_READ(sc, AC_DAC_FIFOC(sc)); 380 CODEC_WRITE(sc, AC_DAC_FIFOC(sc), val | DAC_FIFOC_DRQ_EN); 381 382 /* Start DMA transfer */ 383 error = sunxi_codec_transfer(ch); 384 if (error != 0) { 385 aprint_error_dev(sc->sc_dev, 386 "failed to start DMA transfer: %d\n", error); 387 return error; 388 } 389 390 return 0; 391 } 392 393 static int 394 sunxi_codec_trigger_input(void *priv, void *start, void *end, int blksize, 395 void (*intr)(void *), void *intrarg, const audio_params_t *params) 396 { 397 struct sunxi_codec_softc * const sc = priv; 398 struct sunxi_codec_chan *ch = &sc->sc_rchan; 399 struct sunxi_codec_dma *dma; 400 bus_addr_t pstart; 401 bus_size_t psize; 402 uint32_t val; 403 int error; 404 405 pstart = 0; 406 psize = (uintptr_t)end - (uintptr_t)start; 407 408 LIST_FOREACH(dma, &sc->sc_dmalist, dma_list) 409 if (dma->dma_addr == start) { 410 pstart = dma->dma_map->dm_segs[0].ds_addr; 411 break; 412 } 413 if (pstart == 0) { 414 device_printf(sc->sc_dev, "bad addr %p\n", start); 415 return EINVAL; 416 } 417 418 ch->ch_intr = intr; 419 ch->ch_intrarg = intrarg; 420 ch->ch_start_phys = ch->ch_cur_phys = pstart; 421 ch->ch_end_phys = pstart + psize; 422 ch->ch_blksize = blksize; 423 424 /* Flush ADC FIFO */ 425 val = CODEC_READ(sc, AC_ADC_FIFOC(sc)); 426 CODEC_WRITE(sc, AC_ADC_FIFOC(sc), val | ADC_FIFOC_FIFO_FLUSH); 427 428 /* Clear ADC FIFO status */ 429 val = CODEC_READ(sc, AC_ADC_FIFOS(sc)); 430 CODEC_WRITE(sc, AC_ADC_FIFOS(sc), val); 431 432 /* Unmute input */ 433 if (sc->sc_cfg->mute) 434 sc->sc_cfg->mute(sc, 0, ch->ch_mode); 435 436 /* Configure ADC FIFO */ 437 CODEC_WRITE(sc, AC_ADC_FIFOC(sc), 438 __SHIFTIN(ADC_FS_48KHZ, ADC_FIFOC_FS) | 439 __SHIFTIN(RX_TRIG_LEVEL, ADC_FIFOC_RX_TRIG_LEVEL) | 440 ADC_FIFOC_EN_AD | ADC_FIFOC_RX_FIFO_MODE); 441 442 /* Enable ADC DRQ */ 443 val = CODEC_READ(sc, AC_ADC_FIFOC(sc)); 444 CODEC_WRITE(sc, AC_ADC_FIFOC(sc), val | ADC_FIFOC_DRQ_EN); 445 446 /* Start DMA transfer */ 447 error = sunxi_codec_transfer(ch); 448 if (error != 0) { 449 aprint_error_dev(sc->sc_dev, 450 "failed to start DMA transfer: %d\n", error); 451 return error; 452 } 453 454 return 0; 455 } 456 457 static int 458 sunxi_codec_halt_output(void *priv) 459 { 460 struct sunxi_codec_softc * const sc = priv; 461 struct sunxi_codec_chan *ch = &sc->sc_pchan; 462 uint32_t val; 463 464 /* Disable DMA channel */ 465 fdtbus_dma_halt(ch->ch_dma); 466 467 /* flush fifo */ 468 val = CODEC_READ(sc, AC_DAC_FIFOC(sc)); 469 CODEC_WRITE(sc, AC_DAC_FIFOC(sc), val | DAC_FIFOC_FIFO_FLUSH); 470 while (val & DAC_FIFOC_FIFO_FLUSH) 471 val = CODEC_READ(sc, AC_DAC_FIFOC(sc)); 472 473 /* Mute output */ 474 if (sc->sc_cfg->mute) 475 sc->sc_cfg->mute(sc, 1, ch->ch_mode); 476 477 /* Disable DAC DRQ */ 478 val = CODEC_READ(sc, AC_DAC_FIFOC(sc)); 479 CODEC_WRITE(sc, AC_DAC_FIFOC(sc), val & ~DAC_FIFOC_DRQ_EN); 480 481 ch->ch_intr = NULL; 482 ch->ch_intrarg = NULL; 483 484 return 0; 485 } 486 487 static int 488 sunxi_codec_halt_input(void *priv) 489 { 490 struct sunxi_codec_softc * const sc = priv; 491 struct sunxi_codec_chan *ch = &sc->sc_rchan; 492 uint32_t val; 493 494 /* Mute output */ 495 if (sc->sc_cfg->mute) 496 sc->sc_cfg->mute(sc, 1, ch->ch_mode); 497 498 /* flush fifo */ 499 val = CODEC_READ(sc, AC_ADC_FIFOC(sc)); 500 CODEC_WRITE(sc, AC_ADC_FIFOC(sc), val | ADC_FIFOC_FIFO_FLUSH); 501 while (val & ADC_FIFOC_FIFO_FLUSH) 502 val = CODEC_READ(sc, AC_ADC_FIFOC(sc)); 503 504 /* Disable DMA channel */ 505 fdtbus_dma_halt(ch->ch_dma); 506 507 /* Disable ADC DRQ */ 508 val = CODEC_READ(sc, AC_ADC_FIFOC(sc)); 509 CODEC_WRITE(sc, AC_ADC_FIFOC(sc), val & ~ADC_FIFOC_DRQ_EN); 510 511 return 0; 512 } 513 514 static void 515 sunxi_codec_get_locks(void *priv, kmutex_t **intr, kmutex_t **thread) 516 { 517 struct sunxi_codec_softc * const sc = priv; 518 519 *intr = &sc->sc_intr_lock; 520 *thread = &sc->sc_lock; 521 } 522 523 static const struct audio_hw_if sunxi_codec_hw_if = { 524 .open = sunxi_codec_open, 525 .close = sunxi_codec_close, 526 .drain = NULL, 527 .query_encoding = sunxi_codec_query_encoding, 528 .set_params = sunxi_codec_set_params, 529 .allocm = sunxi_codec_allocm, 530 .freem = sunxi_codec_freem, 531 .mappage = sunxi_codec_mappage, 532 .getdev = sunxi_codec_getdev, 533 .set_port = sunxi_codec_set_port, 534 .get_port = sunxi_codec_get_port, 535 .query_devinfo = sunxi_codec_query_devinfo, 536 .get_props = sunxi_codec_get_props, 537 .round_blocksize = sunxi_codec_round_blocksize, 538 .round_buffersize = sunxi_codec_round_buffersize, 539 .trigger_output = sunxi_codec_trigger_output, 540 .trigger_input = sunxi_codec_trigger_input, 541 .halt_output = sunxi_codec_halt_output, 542 .halt_input = sunxi_codec_halt_input, 543 .get_locks = sunxi_codec_get_locks, 544 }; 545 546 static void 547 sunxi_codec_dmaintr(void *priv) 548 { 549 struct sunxi_codec_chan * const ch = priv; 550 struct sunxi_codec_softc * const sc = ch->ch_sc; 551 552 mutex_enter(&sc->sc_intr_lock); 553 ch->ch_cur_phys += ch->ch_blksize; 554 if (ch->ch_cur_phys >= ch->ch_end_phys) 555 ch->ch_cur_phys = ch->ch_start_phys; 556 557 if (ch->ch_intr) { 558 ch->ch_intr(ch->ch_intrarg); 559 sunxi_codec_transfer(ch); 560 } 561 mutex_exit(&sc->sc_intr_lock); 562 } 563 564 static int 565 sunxi_codec_chan_init(struct sunxi_codec_softc *sc, 566 struct sunxi_codec_chan *ch, u_int mode, const char *dmaname) 567 { 568 ch->ch_sc = sc; 569 ch->ch_mode = mode; 570 ch->ch_dma = fdtbus_dma_get(sc->sc_phandle, dmaname, sunxi_codec_dmaintr, ch); 571 if (ch->ch_dma == NULL) { 572 aprint_error(": couldn't get dma channel \"%s\"\n", dmaname); 573 return ENXIO; 574 } 575 576 if (mode == AUMODE_PLAY) { 577 ch->ch_req.dreq_dir = FDT_DMA_WRITE; 578 ch->ch_req.dreq_dev_phys = 579 sc->sc_baseaddr + AC_DAC_TXDATA(sc); 580 } else { 581 ch->ch_req.dreq_dir = FDT_DMA_READ; 582 ch->ch_req.dreq_dev_phys = 583 sc->sc_baseaddr + AC_ADC_RXDATA(sc); 584 } 585 ch->ch_req.dreq_mem_opt.opt_bus_width = 16; 586 ch->ch_req.dreq_mem_opt.opt_burst_len = 4; 587 ch->ch_req.dreq_dev_opt.opt_bus_width = 16; 588 ch->ch_req.dreq_dev_opt.opt_burst_len = 4; 589 590 return 0; 591 } 592 593 static int 594 sunxi_codec_clock_init(int phandle) 595 { 596 struct fdtbus_reset *rst; 597 struct clk *clk; 598 int error; 599 600 /* Set codec clock to 24.576MHz, suitable for 48 kHz sampling rates */ 601 clk = fdtbus_clock_get(phandle, "codec"); 602 if (clk == NULL) { 603 aprint_error(": couldn't find codec clock\n"); 604 return ENXIO; 605 } 606 error = clk_set_rate(clk, 24576000); 607 if (error != 0) { 608 aprint_error(": couldn't set codec clock rate: %d\n", error); 609 return error; 610 } 611 error = clk_enable(clk); 612 if (error != 0) { 613 aprint_error(": couldn't enable codec clock: %d\n", error); 614 return error; 615 } 616 617 /* Enable APB clock */ 618 clk = fdtbus_clock_get(phandle, "apb"); 619 if (clk == NULL) { 620 aprint_error(": couldn't find apb clock\n"); 621 return ENXIO; 622 } 623 error = clk_enable(clk); 624 if (error != 0) { 625 aprint_error(": couldn't enable apb clock: %d\n", error); 626 return error; 627 } 628 629 /* De-assert reset */ 630 rst = fdtbus_reset_get_index(phandle, 0); 631 if (rst != NULL) { 632 error = fdtbus_reset_deassert(rst); 633 if (error != 0) { 634 aprint_error(": couldn't de-assert reset: %d\n", error); 635 return error; 636 } 637 } 638 639 return 0; 640 } 641 642 static int 643 sunxi_codec_match(device_t parent, cfdata_t cf, void *aux) 644 { 645 struct fdt_attach_args * const faa = aux; 646 647 return of_match_compat_data(faa->faa_phandle, compat_data); 648 } 649 650 static void 651 sunxi_codec_attach(device_t parent, device_t self, void *aux) 652 { 653 struct sunxi_codec_softc * const sc = device_private(self); 654 struct fdt_attach_args * const faa = aux; 655 const int phandle = faa->faa_phandle; 656 bus_addr_t addr; 657 bus_size_t size; 658 uint32_t val; 659 int error; 660 661 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 662 aprint_error(": couldn't get registers\n"); 663 return; 664 } 665 666 if (sunxi_codec_clock_init(phandle) != 0) 667 return; 668 669 sc->sc_dev = self; 670 sc->sc_phandle = phandle; 671 sc->sc_baseaddr = addr; 672 sc->sc_bst = faa->faa_bst; 673 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 674 aprint_error(": couldn't map registers\n"); 675 return; 676 } 677 sc->sc_dmat = faa->faa_dmat; 678 LIST_INIT(&sc->sc_dmalist); 679 sc->sc_cfg = (void *)of_search_compatible(phandle, compat_data)->data; 680 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE); 681 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 682 683 if (sunxi_codec_chan_init(sc, &sc->sc_pchan, AUMODE_PLAY, "tx") != 0 || 684 sunxi_codec_chan_init(sc, &sc->sc_rchan, AUMODE_RECORD, "rx") != 0) { 685 aprint_error(": couldn't setup channels\n"); 686 return; 687 } 688 689 /* Optional PA mute GPIO */ 690 sc->sc_pin_pa = fdtbus_gpio_acquire(phandle, "allwinner,pa-gpios", GPIO_PIN_OUTPUT); 691 692 aprint_naive("\n"); 693 aprint_normal(": %s\n", sc->sc_cfg->name); 694 695 /* Enable DAC */ 696 val = CODEC_READ(sc, AC_DAC_DPC(sc)); 697 val |= DAC_DPC_EN_DA; 698 CODEC_WRITE(sc, AC_DAC_DPC(sc), val); 699 700 /* Initialize codec */ 701 if (sc->sc_cfg->init(sc) != 0) { 702 aprint_error_dev(self, "couldn't initialize codec\n"); 703 return; 704 } 705 706 sc->sc_format.mode = AUMODE_PLAY|AUMODE_RECORD; 707 sc->sc_format.encoding = AUDIO_ENCODING_SLINEAR_LE; 708 sc->sc_format.validbits = 16; 709 sc->sc_format.precision = 16; 710 sc->sc_format.channels = 2; 711 sc->sc_format.channel_mask = AUFMT_STEREO; 712 sc->sc_format.frequency_type = 0; 713 sc->sc_format.frequency[0] = sc->sc_format.frequency[1] = 48000; 714 715 error = auconv_create_encodings(&sc->sc_format, 1, &sc->sc_encodings); 716 if (error) { 717 aprint_error_dev(self, "couldn't create encodings\n"); 718 return; 719 } 720 721 audio_attach_mi(&sunxi_codec_hw_if, sc, self); 722 } 723 724 CFATTACH_DECL_NEW(sunxi_codec, sizeof(struct sunxi_codec_softc), 725 sunxi_codec_match, sunxi_codec_attach, NULL, NULL); 726 727 #ifdef DDB 728 void sunxicodec_dump(void); 729 730 void 731 sunxicodec_dump(void) 732 { 733 struct sunxi_codec_softc *sc; 734 device_t dev; 735 736 dev = device_find_by_driver_unit("sunxicodec", 0); 737 if (dev == NULL) 738 return; 739 sc = device_private(dev); 740 741 device_printf(dev, "AC_DAC_DPC: %08x\n", CODEC_READ(sc, AC_DAC_DPC(sc))); 742 device_printf(dev, "AC_DAC_FIFOC: %08x\n", CODEC_READ(sc, AC_DAC_FIFOC(sc))); 743 device_printf(dev, "AC_DAC_FIFOS: %08x\n", CODEC_READ(sc, AC_DAC_FIFOS(sc))); 744 device_printf(dev, "AC_ADC_FIFOC: %08x\n", CODEC_READ(sc, AC_ADC_FIFOC(sc))); 745 device_printf(dev, "AC_ADC_FIFOS: %08x\n", CODEC_READ(sc, AC_ADC_FIFOS(sc))); 746 device_printf(dev, "AC_DAC_CNT: %08x\n", CODEC_READ(sc, AC_DAC_CNT(sc))); 747 device_printf(dev, "AC_ADC_CNT: %08x\n", CODEC_READ(sc, AC_ADC_CNT(sc))); 748 } 749 #endif 750
Indexes created Thu Sep 25 16:09:42 GMT 2025