sunxi_debe.c revision 1.5
1 /* $NetBSD: sunxi_debe.c,v 1.5 2018/04/03 16:17:59 bouyer Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Manuel Bouyer <bouyer (at) antioche.eu.org> 5 * All rights reserved. 6 * 7 * Copyright (c) 2014 Jared D. McNeill <jmcneill (at) invisible.ca> 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 24 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 26 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 27 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 #include "genfb.h" 33 34 #ifndef SUNXI_DEBE_VIDEOMEM 35 #define SUNXI_DEBE_VIDEOMEM (16 * 1024 * 1024) 36 #endif 37 38 #define SUNXI_DEBE_CURMAX 64 39 40 #include <sys/cdefs.h> 41 __KERNEL_RCSID(0, "$NetBSD: sunxi_debe.c,v 1.5 2018/04/03 16:17:59 bouyer Exp $"); 42 43 #include <sys/param.h> 44 #include <sys/bus.h> 45 #include <sys/device.h> 46 #include <sys/intr.h> 47 #include <sys/systm.h> 48 #include <sys/kernel.h> 49 #include <sys/mutex.h> 50 #include <sys/condvar.h> 51 52 #include <dev/fdt/fdtvar.h> 53 #include <dev/fdt/fdt_port.h> 54 55 #include <dev/videomode/videomode.h> 56 #include <dev/wscons/wsconsio.h> 57 #include <dev/wsfb/genfbvar.h> 58 59 #include <arm/sunxi/sunxi_debereg.h> 60 #include <arm/sunxi/sunxi_display.h> 61 62 enum sunxi_debe_type { 63 DEBE_A10 = 1, 64 }; 65 66 struct sunxi_debe_softc { 67 device_t sc_dev; 68 device_t sc_fbdev; 69 enum sunxi_debe_type sc_type; 70 bus_space_tag_t sc_bst; 71 bus_space_handle_t sc_bsh; 72 bus_dma_tag_t sc_dmat; 73 74 struct clk *sc_clk_ahb; 75 struct clk *sc_clk_mod; 76 struct clk *sc_clk_ram; 77 78 bus_dma_segment_t sc_dmasegs[1]; 79 bus_size_t sc_dmasize; 80 bus_dmamap_t sc_dmamap; 81 void *sc_dmap; 82 83 bool sc_cursor_enable; 84 int sc_cursor_x, sc_cursor_y; 85 int sc_hot_x, sc_hot_y; 86 uint8_t sc_cursor_bitmap[8 * SUNXI_DEBE_CURMAX]; 87 uint8_t sc_cursor_mask[8 * SUNXI_DEBE_CURMAX]; 88 89 int sc_phandle; 90 struct fdt_device_ports sc_ports; 91 struct fdt_endpoint *sc_out_ep; 92 int sc_unit; /* debe0 or debe1 */ 93 }; 94 95 #define DEBE_READ(sc, reg) \ 96 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 97 #define DEBE_WRITE(sc, reg, val) \ 98 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 99 100 static const struct of_compat_data compat_data[] = { 101 {"allwinner,sun4i-a10-display-backend", DEBE_A10}, 102 {"allwinner,sun7i-a20-display-backend", DEBE_A10}, 103 {NULL} 104 }; 105 106 struct sunxifb_attach_args { 107 void *afb_fb; 108 uint32_t afb_width; 109 uint32_t afb_height; 110 bus_dma_tag_t afb_dmat; 111 bus_dma_segment_t *afb_dmasegs; 112 int afb_ndmasegs; 113 }; 114 115 static void sunxi_debe_ep_connect(device_t, struct fdt_endpoint *, bool); 116 static int sunxi_debe_ep_enable(device_t, struct fdt_endpoint *, bool); 117 static int sunxi_debe_match(device_t, cfdata_t, void *); 118 static void sunxi_debe_attach(device_t, device_t, void *); 119 120 static int sunxi_debe_alloc_videomem(struct sunxi_debe_softc *); 121 static void sunxi_debe_setup_fbdev(struct sunxi_debe_softc *, 122 const struct videomode *); 123 124 static int sunxi_debe_set_curpos(struct sunxi_debe_softc *, int, int); 125 static int sunxi_debe_set_cursor(struct sunxi_debe_softc *, 126 struct wsdisplay_cursor *); 127 static int sunxi_debe_ioctl(device_t, u_long, void *); 128 static void sunxi_befb_set_videomode(device_t, u_int, u_int); 129 void sunxi_debe_dump_regs(int); 130 131 CFATTACH_DECL_NEW(sunxi_debe, sizeof(struct sunxi_debe_softc), 132 sunxi_debe_match, sunxi_debe_attach, NULL, NULL); 133 134 static int 135 sunxi_debe_match(device_t parent, cfdata_t cf, void *aux) 136 { 137 struct fdt_attach_args * const faa = aux; 138 139 return of_match_compat_data(faa->faa_phandle, compat_data); 140 } 141 142 static void 143 sunxi_debe_attach(device_t parent, device_t self, void *aux) 144 { 145 struct sunxi_debe_softc *sc = device_private(self); 146 struct fdt_attach_args * const faa = aux; 147 const int phandle = faa->faa_phandle; 148 bus_addr_t addr; 149 bus_size_t size; 150 struct fdtbus_reset *rst; 151 #if NAWIN_MP > 0 152 device_t mpdev; 153 #endif 154 #ifdef AWIN_DEBE_FWINIT 155 struct videomode mode; 156 #endif 157 int error; 158 159 sc->sc_dev = self; 160 sc->sc_phandle = phandle; 161 sc->sc_bst = faa->faa_bst; 162 sc->sc_dmat = faa->faa_dmat; 163 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 164 aprint_error(": couldn't get registers\n"); 165 } 166 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 167 aprint_error(": couldn't map registers\n"); 168 return; 169 } 170 171 sc->sc_clk_ahb = fdtbus_clock_get(phandle, "ahb"); 172 sc->sc_clk_mod = fdtbus_clock_get(phandle, "mod"); 173 sc->sc_clk_ram = fdtbus_clock_get(phandle, "ram"); 174 175 rst = fdtbus_reset_get_index(phandle, 0); 176 if (rst == NULL) { 177 aprint_error(": couldn't get reset\n"); 178 return; 179 } 180 if (fdtbus_reset_assert(rst) != 0) { 181 aprint_error(": couldn't assert reset\n"); 182 return; 183 } 184 delay(1); 185 if (fdtbus_reset_deassert(rst) != 0) { 186 aprint_error(": couldn't de-assert reset\n"); 187 return; 188 } 189 190 if (sc->sc_clk_ahb == NULL || sc->sc_clk_mod == NULL 191 || sc->sc_clk_ram == NULL) { 192 aprint_error(": couldn't get clocks\n"); 193 aprint_debug_dev(self, "clk ahb %s mod %s ram %s\n", 194 sc->sc_clk_ahb == NULL ? "missing" : "present", 195 sc->sc_clk_mod == NULL ? "missing" : "present", 196 sc->sc_clk_ram == NULL ? "missing" : "present"); 197 return; 198 } 199 200 error = clk_set_rate(sc->sc_clk_mod, 300000000); 201 if (error) { 202 aprint_error("couln't set mod clock rate (%d)\n", error); 203 return; 204 } 205 206 if (clk_enable(sc->sc_clk_ahb) != 0 || 207 clk_enable(sc->sc_clk_mod) != 0) { 208 aprint_error(": couldn't enable clocks\n"); 209 return; 210 } 211 if (clk_disable(sc->sc_clk_ram) != 0) { 212 aprint_error(": couldn't disable ram clock\n"); 213 } 214 215 sc->sc_type = of_search_compatible(faa->faa_phandle, compat_data)->data; 216 217 aprint_naive("\n"); 218 aprint_normal(": Display Engine Backend (%s)\n", 219 fdtbus_get_string(phandle, "name")); 220 221 222 #ifdef AWIN_DEBE_FWINIT 223 const uint32_t modctl = DEBE_READ(sc, SUNXI_DEBE_MODCTL_REG); 224 const uint32_t dissize = DEBE_READ(sc, SUNXI_DEBE_DISSIZE_REG); 225 if ((modctl & SUNXI_DEBE_MODCTL_EN) == 0) { 226 aprint_error_dev(sc->sc_dev, "disabled\n"); 227 return; 228 } 229 if ((modctl & SUNXI_DEBE_MODCTL_START_CTL) == 0) { 230 aprint_error_dev(sc->sc_dev, "stopped\n"); 231 return; 232 } 233 memset(&mode, 0, sizeof(mode)); 234 mode.hdisplay = (dissize & 0xffff) + 1; 235 mode.vdisplay = ((dissize >> 16) & 0xffff) + 1; 236 237 if (mode.hdisplay == 1 || mode.vdisplay == 1) { 238 aprint_error_dev(sc->sc_dev, 239 "couldn't determine video mode\n"); 240 return; 241 } 242 243 aprint_verbose_dev(sc->sc_dev, "using %dx%d mode from firmware\n", 244 mode.hdisplay, mode.vdisplay); 245 246 sc->sc_dmasize = mode.hdisplay * mode.vdisplay * 4; 247 #else 248 for (unsigned int reg = 0x800; reg < 0x1000; reg += 4) { 249 DEBE_WRITE(sc, reg, 0); 250 } 251 252 DEBE_WRITE(sc, SUNXI_DEBE_MODCTL_REG, SUNXI_DEBE_MODCTL_EN); 253 254 sc->sc_dmasize = SUNXI_DEBE_VIDEOMEM; 255 #endif 256 257 DEBE_WRITE(sc, SUNXI_DEBE_HWC_PALETTE_TABLE, 0); 258 259 error = sunxi_debe_alloc_videomem(sc); 260 if (error) { 261 aprint_error_dev(sc->sc_dev, 262 "couldn't allocate video memory, error = %d\n", error); 263 return; 264 } 265 266 #if NAWIN_MP > 0 267 mpdev = device_find_by_driver_unit("sunximp", 0); 268 if (mpdev) { 269 paddr_t pa = sc->sc_dmamap->dm_segs[0].ds_addr; 270 if (pa >= SUNXI_SDRAM_PBASE) 271 pa -= SUNXI_SDRAM_PBASE; 272 sunxi_mp_setbase(mpdev, pa, sc->sc_dmasize); 273 } 274 #endif 275 sc->sc_unit = -1; 276 sc->sc_ports.dp_ep_connect = sunxi_debe_ep_connect; 277 sc->sc_ports.dp_ep_enable = sunxi_debe_ep_enable; 278 fdt_ports_register(&sc->sc_ports, self, phandle, EP_OTHER); 279 280 #ifdef AWIN_DEBE_FWINIT 281 sunxi_debe_set_videomode(device_unit(self), &mode); 282 sunxi_debe_enable(device_unit(self), true); 283 #else 284 if (clk_disable(sc->sc_clk_ahb) != 0 || 285 clk_disable(sc->sc_clk_mod) != 0) { 286 aprint_error(": couldn't disable clocks\n"); 287 return; 288 } 289 #endif 290 } 291 292 293 294 static void 295 sunxi_debe_ep_connect(device_t self, struct fdt_endpoint *ep, bool connect) 296 { 297 struct sunxi_debe_softc *sc = device_private(self); 298 struct fdt_endpoint *rep = fdt_endpoint_remote(ep); 299 int rep_idx = fdt_endpoint_index(rep); 300 301 KASSERT(device_is_a(self, "sunxidebe")); 302 if (!connect) { 303 aprint_error_dev(self, "endpoint disconnect not supported\n"); 304 return; 305 } 306 307 if (fdt_endpoint_port_index(ep) == 1) { 308 bool do_print = (sc->sc_unit == -1); 309 /* 310 * one of our output endpoints has been connected. 311 * the remote id is our unit number 312 */ 313 if (sc->sc_unit != -1 && rep_idx != -1 && 314 sc->sc_unit != rep_idx) { 315 aprint_error_dev(self, ": remote id %d doens't match" 316 " discovered unit number %d\n", 317 rep_idx, sc->sc_unit); 318 return; 319 } 320 if (!device_is_a(fdt_endpoint_device(rep), "sunxitcon")) { 321 aprint_error_dev(self, 322 ": output %d connected to unknown device\n", 323 fdt_endpoint_index(ep)); 324 return; 325 } 326 if (rep_idx != -1) 327 sc->sc_unit = rep_idx; 328 else { 329 /* assume only one debe */ 330 sc->sc_unit = 0; 331 } 332 if (do_print) 333 aprint_verbose_dev(self, "debe unit %d\n", sc->sc_unit); 334 } 335 } 336 337 static int 338 sunxi_debe_alloc_videomem(struct sunxi_debe_softc *sc) 339 { 340 int error, nsegs; 341 342 error = bus_dmamem_alloc(sc->sc_dmat, sc->sc_dmasize, 0x1000, 0, 343 sc->sc_dmasegs, 1, &nsegs, BUS_DMA_WAITOK); 344 if (error) 345 return error; 346 error = bus_dmamem_map(sc->sc_dmat, sc->sc_dmasegs, nsegs, 347 sc->sc_dmasize, &sc->sc_dmap, BUS_DMA_WAITOK | BUS_DMA_COHERENT); 348 if (error) 349 goto free; 350 error = bus_dmamap_create(sc->sc_dmat, sc->sc_dmasize, 1, 351 sc->sc_dmasize, 0, BUS_DMA_WAITOK, &sc->sc_dmamap); 352 if (error) 353 goto unmap; 354 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, sc->sc_dmap, 355 sc->sc_dmasize, NULL, BUS_DMA_WAITOK); 356 if (error) 357 goto destroy; 358 359 memset(sc->sc_dmap, 0, sc->sc_dmasize); 360 361 return 0; 362 363 destroy: 364 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 365 unmap: 366 bus_dmamem_unmap(sc->sc_dmat, sc->sc_dmap, sc->sc_dmasize); 367 free: 368 bus_dmamem_free(sc->sc_dmat, sc->sc_dmasegs, nsegs); 369 370 sc->sc_dmasize = 0; 371 sc->sc_dmap = NULL; 372 373 return error; 374 } 375 376 static void 377 sunxi_debe_setup_fbdev(struct sunxi_debe_softc *sc, const struct videomode *mode) 378 { 379 if (mode == NULL) 380 return; 381 382 const u_int interlace_p = !!(mode->flags & VID_INTERLACE); 383 const u_int fb_width = mode->hdisplay; 384 const u_int fb_height = (mode->vdisplay << interlace_p); 385 386 if (mode && sc->sc_fbdev == NULL) { 387 struct sunxifb_attach_args afb = { 388 .afb_fb = sc->sc_dmap, 389 .afb_width = fb_width, 390 .afb_height = fb_height, 391 .afb_dmat = sc->sc_dmat, 392 .afb_dmasegs = sc->sc_dmasegs, 393 .afb_ndmasegs = 1 394 }; 395 sc->sc_fbdev = config_found_ia(sc->sc_dev, "sunxidebe", 396 &afb, NULL); 397 } else if (sc->sc_fbdev != NULL) { 398 sunxi_befb_set_videomode(sc->sc_fbdev, fb_width, fb_height); 399 } 400 } 401 402 static int 403 sunxi_debe_set_curpos(struct sunxi_debe_softc *sc, int x, int y) 404 { 405 int xx, yy; 406 u_int yoff, xoff; 407 408 xoff = yoff = 0; 409 xx = x - sc->sc_hot_x; 410 yy = y - sc->sc_hot_y; 411 if (xx < 0) { 412 xoff -= xx; 413 xx = 0; 414 } 415 if (yy < 0) { 416 yoff -= yy; 417 yy = 0; 418 } 419 420 DEBE_WRITE(sc, SUNXI_DEBE_HWCCTL_REG, 421 __SHIFTIN(yy, SUNXI_DEBE_HWCCTL_YCOOR) | 422 __SHIFTIN(xx, SUNXI_DEBE_HWCCTL_XCOOR)); 423 DEBE_WRITE(sc, SUNXI_DEBE_HWCFBCTL_REG, 424 #if SUNXI_DEBE_CURMAX == 32 425 __SHIFTIN(SUNXI_DEBE_HWCFBCTL_YSIZE_32, SUNXI_DEBE_HWCFBCTL_YSIZE) | 426 __SHIFTIN(SUNXI_DEBE_HWCFBCTL_XSIZE_32, SUNXI_DEBE_HWCFBCTL_XSIZE) | 427 #else 428 __SHIFTIN(SUNXI_DEBE_HWCFBCTL_YSIZE_64, SUNXI_DEBE_HWCFBCTL_YSIZE) | 429 __SHIFTIN(SUNXI_DEBE_HWCFBCTL_XSIZE_64, SUNXI_DEBE_HWCFBCTL_XSIZE) | 430 #endif 431 __SHIFTIN(SUNXI_DEBE_HWCFBCTL_FBFMT_2BPP, SUNXI_DEBE_HWCFBCTL_FBFMT) | 432 __SHIFTIN(yoff, SUNXI_DEBE_HWCFBCTL_YCOOROFF) | 433 __SHIFTIN(xoff, SUNXI_DEBE_HWCFBCTL_XCOOROFF)); 434 435 return 0; 436 } 437 438 static int 439 sunxi_debe_set_cursor(struct sunxi_debe_softc *sc, struct wsdisplay_cursor *cur) 440 { 441 uint32_t val; 442 uint8_t r[4], g[4], b[4]; 443 u_int index, count, shift, off, pcnt; 444 int i, j, idx, error; 445 uint8_t mask; 446 447 if (cur->which & WSDISPLAY_CURSOR_DOCUR) { 448 val = DEBE_READ(sc, SUNXI_DEBE_MODCTL_REG); 449 if (cur->enable) 450 val |= SUNXI_DEBE_MODCTL_HWC_EN; 451 else 452 val &= ~SUNXI_DEBE_MODCTL_HWC_EN; 453 DEBE_WRITE(sc, SUNXI_DEBE_MODCTL_REG, val); 454 455 sc->sc_cursor_enable = cur->enable; 456 } 457 458 if (cur->which & WSDISPLAY_CURSOR_DOHOT) { 459 sc->sc_hot_x = cur->hot.x; 460 sc->sc_hot_y = cur->hot.y; 461 cur->which |= WSDISPLAY_CURSOR_DOPOS; 462 } 463 464 if (cur->which & WSDISPLAY_CURSOR_DOPOS) { 465 sunxi_debe_set_curpos(sc, cur->pos.x, cur->pos.y); 466 } 467 468 if (cur->which & WSDISPLAY_CURSOR_DOCMAP) { 469 index = cur->cmap.index; 470 count = cur->cmap.count; 471 if (index >= 2 || count > 2 - index) 472 return EINVAL; 473 error = copyin(cur->cmap.red, &r[index], count); 474 if (error) 475 return error; 476 error = copyin(cur->cmap.green, &g[index], count); 477 if (error) 478 return error; 479 error = copyin(cur->cmap.blue, &b[index], count); 480 if (error) 481 return error; 482 483 for (i = index; i < (index + count); i++) { 484 DEBE_WRITE(sc, 485 SUNXI_DEBE_HWC_PALETTE_TABLE + (4 * (i + 2)), 486 (r[i] << 16) | (g[i] << 8) | b[i] | 0xff000000); 487 } 488 } 489 490 if (cur->which & WSDISPLAY_CURSOR_DOSHAPE) { 491 error = copyin(cur->mask, sc->sc_cursor_mask, 492 SUNXI_DEBE_CURMAX * 8); 493 if (error) 494 return error; 495 error = copyin(cur->image, sc->sc_cursor_bitmap, 496 SUNXI_DEBE_CURMAX * 8); 497 if (error) 498 return error; 499 } 500 501 if (cur->which & (WSDISPLAY_CURSOR_DOCMAP|WSDISPLAY_CURSOR_DOSHAPE)) { 502 for (i = 0, pcnt = 0; i < SUNXI_DEBE_CURMAX * 8; i++) { 503 for (j = 0, mask = 1; j < 8; j++, mask <<= 1, pcnt++) { 504 idx = ((sc->sc_cursor_mask[i] & mask) ? 2 : 0) | 505 ((sc->sc_cursor_bitmap[i] & mask) ? 1 : 0); 506 off = (pcnt >> 4) * 4; 507 shift = (pcnt & 0xf) * 2; 508 val = DEBE_READ(sc, 509 SUNXI_DEBE_HWC_PATTERN_BLOCK + off); 510 val &= ~(3 << shift); 511 val |= (idx << shift); 512 DEBE_WRITE(sc, 513 SUNXI_DEBE_HWC_PATTERN_BLOCK + off, val); 514 } 515 } 516 } 517 518 return 0; 519 } 520 521 static int 522 sunxi_debe_ep_enable(device_t dev, struct fdt_endpoint *ep, bool enable) 523 { 524 struct sunxi_debe_softc *sc; 525 uint32_t val; 526 527 KASSERT(device_is_a(dev, "sunxidebe")); 528 sc = device_private(dev); 529 530 if (enable) { 531 if (clk_enable(sc->sc_clk_ram) != 0) { 532 device_printf(dev, 533 ": warning: failed to enable ram clock\n"); 534 } 535 val = DEBE_READ(sc, SUNXI_DEBE_REGBUFFCTL_REG); 536 val |= SUNXI_DEBE_REGBUFFCTL_REGLOADCTL; 537 DEBE_WRITE(sc, SUNXI_DEBE_REGBUFFCTL_REG, val); 538 539 val = DEBE_READ(sc, SUNXI_DEBE_MODCTL_REG); 540 val |= SUNXI_DEBE_MODCTL_START_CTL; 541 DEBE_WRITE(sc, SUNXI_DEBE_MODCTL_REG, val); 542 #ifdef SUNXI_DEBE_DEBUG 543 sunxi_debe_dump_regs(sc->sc_unit); 544 #endif 545 } else { 546 val = DEBE_READ(sc, SUNXI_DEBE_MODCTL_REG); 547 val &= ~SUNXI_DEBE_MODCTL_START_CTL; 548 DEBE_WRITE(sc, SUNXI_DEBE_MODCTL_REG, val); 549 if (clk_disable(sc->sc_clk_ram) != 0) { 550 device_printf(dev, 551 ": warning: failed to disable ram clock\n"); 552 } 553 } 554 #if 0 555 for (int i = 0; i < 0x1000; i += 4) { 556 printf("DEBE 0x%04x: 0x%08x\n", i, DEBE_READ(sc, i)); 557 } 558 #endif 559 return 0; 560 } 561 562 void 563 sunxi_debe_set_videomode(device_t dev, const struct videomode *mode) 564 { 565 struct sunxi_debe_softc *sc; 566 uint32_t val; 567 568 KASSERT(device_is_a(dev, "sunxidebe")); 569 sc = device_private(dev); 570 571 if (mode) { 572 const u_int interlace_p = !!(mode->flags & VID_INTERLACE); 573 const u_int width = mode->hdisplay; 574 const u_int height = (mode->vdisplay << interlace_p); 575 const u_int fb_width = width; 576 const u_int fb_height = height; 577 uint32_t vmem = width * height * 4; 578 579 if (vmem > sc->sc_dmasize) { 580 device_printf(sc->sc_dev, 581 "not enough memory for %ux%u fb (req %u have %u)\n", 582 width, height, vmem, (unsigned int)sc->sc_dmasize); 583 return; 584 } 585 586 paddr_t pa = sc->sc_dmamap->dm_segs[0].ds_addr; 587 #if !defined(ALLWINNER_A80) && 0 588 #define SUNXI_SDRAM_PBASE-0 0x40000000 589 /* 590 * On 2GB systems, we need to subtract AWIN_SDRAM_PBASE from 591 * the phys addr. 592 */ 593 if (pa >= SUNXI_SDRAM_PBASE) 594 pa -= SUNXI_SDRAM_PBASE; 595 #endif 596 597 /* notify fb */ 598 sunxi_debe_setup_fbdev(sc, mode); 599 600 DEBE_WRITE(sc, SUNXI_DEBE_DISSIZE_REG, 601 ((height - 1) << 16) | (width - 1)); 602 DEBE_WRITE(sc, SUNXI_DEBE_LAYSIZE_REG, 603 ((fb_height - 1) << 16) | (fb_width - 1)); 604 DEBE_WRITE(sc, SUNXI_DEBE_LAYCOOR_REG, 0); 605 DEBE_WRITE(sc, SUNXI_DEBE_LAYLINEWIDTH_REG, (fb_width << 5)); 606 DEBE_WRITE(sc, SUNXI_DEBE_LAYFB_L32ADD_REG, pa << 3); 607 DEBE_WRITE(sc, SUNXI_DEBE_LAYFB_H4ADD_REG, pa >> 29); 608 609 val = DEBE_READ(sc, SUNXI_DEBE_ATTCTL1_REG); 610 val &= ~SUNXI_DEBE_ATTCTL1_LAY_FBFMT; 611 val |= __SHIFTIN(SUNXI_DEBE_ATTCTL1_LAY_FBFMT_XRGB8888, 612 SUNXI_DEBE_ATTCTL1_LAY_FBFMT); 613 val &= ~SUNXI_DEBE_ATTCTL1_LAY_BRSWAPEN; 614 val &= ~SUNXI_DEBE_ATTCTL1_LAY_FBPS; 615 #if __ARMEB__ 616 val |= __SHIFTIN(SUNXI_DEBE_ATTCTL1_LAY_FBPS_32BPP_BGRA, 617 SUNXI_DEBE_ATTCTL1_LAY_FBPS); 618 #else 619 val |= __SHIFTIN(SUNXI_DEBE_ATTCTL1_LAY_FBPS_32BPP_ARGB, 620 SUNXI_DEBE_ATTCTL1_LAY_FBPS); 621 #endif 622 DEBE_WRITE(sc, SUNXI_DEBE_ATTCTL1_REG, val); 623 624 val = DEBE_READ(sc, SUNXI_DEBE_MODCTL_REG); 625 val |= SUNXI_DEBE_MODCTL_LAY0_EN; 626 if (interlace_p) { 627 val |= SUNXI_DEBE_MODCTL_ITLMOD_EN; 628 } else { 629 val &= ~SUNXI_DEBE_MODCTL_ITLMOD_EN; 630 } 631 val &= ~SUNXI_DEBE_MODCTL_OUT_SEL; 632 if (sc->sc_unit == 1) { 633 val |= __SHIFTIN(SUNXI_DEBE_MODCTL_OUT_SEL_LCD1, 634 SUNXI_DEBE_MODCTL_OUT_SEL); 635 } 636 DEBE_WRITE(sc, SUNXI_DEBE_MODCTL_REG, val); 637 } else { 638 /* disable */ 639 val = DEBE_READ(sc, SUNXI_DEBE_MODCTL_REG); 640 val &= ~SUNXI_DEBE_MODCTL_LAY0_EN; 641 val &= ~SUNXI_DEBE_MODCTL_START_CTL; 642 DEBE_WRITE(sc, SUNXI_DEBE_MODCTL_REG, val); 643 644 /* notify fb */ 645 sunxi_debe_setup_fbdev(sc, mode); 646 } 647 } 648 649 static int 650 sunxi_debe_ioctl(device_t self, u_long cmd, void *data) 651 { 652 struct sunxi_debe_softc *sc = device_private(self); 653 struct wsdisplay_curpos *cp; 654 uint32_t val; 655 int enable; 656 657 switch (cmd) { 658 case WSDISPLAYIO_SVIDEO: 659 enable = *(int *)data; 660 val = DEBE_READ(sc, SUNXI_DEBE_MODCTL_REG); 661 if (enable) { 662 if (val & SUNXI_DEBE_MODCTL_START_CTL) { 663 /* already enabled */ 664 return 0; 665 } 666 } else { 667 if ((val & SUNXI_DEBE_MODCTL_START_CTL) == 0) { 668 /* already disabled */ 669 return 0; 670 } 671 } 672 return fdt_endpoint_enable(sc->sc_out_ep, enable); 673 case WSDISPLAYIO_GVIDEO: 674 val = DEBE_READ(sc, SUNXI_DEBE_MODCTL_REG); 675 *(int *)data = !!(val & SUNXI_DEBE_MODCTL_LAY0_EN); 676 return 0; 677 case WSDISPLAYIO_GCURPOS: 678 cp = data; 679 cp->x = sc->sc_cursor_x; 680 cp->y = sc->sc_cursor_y; 681 return 0; 682 case WSDISPLAYIO_SCURPOS: 683 cp = data; 684 return sunxi_debe_set_curpos(sc, cp->x, cp->y); 685 case WSDISPLAYIO_GCURMAX: 686 cp = data; 687 cp->x = SUNXI_DEBE_CURMAX; 688 cp->y = SUNXI_DEBE_CURMAX; 689 return 0; 690 case WSDISPLAYIO_SCURSOR: 691 return sunxi_debe_set_cursor(sc, data); 692 } 693 694 return EPASSTHROUGH; 695 } 696 697 /* genfb attachement */ 698 699 struct sunxi_befb_softc { 700 struct genfb_softc sc_gen; 701 device_t sc_debedev; 702 device_t sc_mpdev; 703 704 bus_dma_tag_t sc_dmat; 705 bus_dma_segment_t *sc_dmasegs; 706 int sc_ndmasegs; 707 }; 708 709 static device_t sunxi_befb_consoledev = NULL; 710 711 static int sunxi_befb_match(device_t, cfdata_t, void *); 712 static void sunxi_befb_attach(device_t, device_t, void *); 713 714 static int sunxi_befb_ioctl(void *, void *, u_long, void *, int, lwp_t *); 715 static paddr_t sunxi_befb_mmap(void *, void *, off_t, int); 716 static bool sunxi_befb_shutdown(device_t, int); 717 718 CFATTACH_DECL_NEW(sunxi_befb, sizeof(struct sunxi_befb_softc), 719 sunxi_befb_match, sunxi_befb_attach, NULL, NULL); 720 721 static int 722 sunxi_befb_match(device_t parent, cfdata_t cf, void *aux) 723 { 724 return 1; 725 } 726 727 static void 728 sunxi_befb_attach(device_t parent, device_t self, void *aux) 729 { 730 struct sunxi_befb_softc *sc = device_private(self); 731 struct sunxifb_attach_args * const afb = aux; 732 prop_dictionary_t cfg = device_properties(self); 733 struct genfb_ops ops; 734 735 if (sunxi_befb_consoledev == NULL) 736 sunxi_befb_consoledev = self; 737 738 sc->sc_gen.sc_dev = self; 739 sc->sc_debedev = parent; 740 sc->sc_dmat = afb->afb_dmat; 741 sc->sc_dmasegs = afb->afb_dmasegs; 742 sc->sc_ndmasegs = afb->afb_ndmasegs; 743 sc->sc_mpdev = device_find_by_driver_unit("sunximp", 0); 744 745 prop_dictionary_set_uint32(cfg, "width", afb->afb_width); 746 prop_dictionary_set_uint32(cfg, "height", afb->afb_height); 747 prop_dictionary_set_uint8(cfg, "depth", 32); 748 prop_dictionary_set_uint16(cfg, "linebytes", afb->afb_width * 4); 749 prop_dictionary_set_uint32(cfg, "address", 0); 750 prop_dictionary_set_uint32(cfg, "virtual_address", 751 (uintptr_t)afb->afb_fb); 752 753 genfb_init(&sc->sc_gen); 754 755 if (sc->sc_gen.sc_width == 0 || sc->sc_gen.sc_fbsize == 0) { 756 aprint_normal(": disabled\n"); 757 return; 758 } 759 760 pmf_device_register1(self, NULL, NULL, sunxi_befb_shutdown); 761 762 memset(&ops, 0, sizeof(ops)); 763 ops.genfb_ioctl = sunxi_befb_ioctl; 764 ops.genfb_mmap = sunxi_befb_mmap; 765 766 aprint_naive("\n"); 767 768 bool is_console = false; 769 prop_dictionary_set_bool(cfg, "is_console", is_console); 770 771 if (is_console) 772 aprint_normal(": switching to framebuffer console\n"); 773 else 774 aprint_normal("\n"); 775 776 genfb_attach(&sc->sc_gen, &ops); 777 } 778 779 static int 780 sunxi_befb_ioctl(void *v, void *vs, u_long cmd, void *data, int flag, lwp_t *l) 781 { 782 struct sunxi_befb_softc *sc = v; 783 struct wsdisplayio_bus_id *busid; 784 struct wsdisplayio_fbinfo *fbi; 785 struct rasops_info *ri; 786 int error; 787 788 switch (cmd) { 789 case WSDISPLAYIO_GTYPE: 790 *(u_int *)data = WSDISPLAY_TYPE_ALLWINNER; 791 return 0; 792 case WSDISPLAYIO_GET_BUSID: 793 busid = data; 794 busid->bus_type = WSDISPLAYIO_BUS_SOC; 795 return 0; 796 case WSDISPLAYIO_GET_FBINFO: 797 fbi = data; 798 ri = &sc->sc_gen.vd.active->scr_ri; 799 error = wsdisplayio_get_fbinfo(ri, fbi); 800 if (error == 0) { 801 fbi->fbi_flags |= WSFB_VRAM_IS_RAM; 802 fbi->fbi_fbsize = sc->sc_dmasegs[0].ds_len; 803 #if NAWIN_MP > 0 804 if (sc->sc_mpdev) 805 fbi->fbi_flags |= WSFB_ACCEL; 806 #endif 807 } 808 return error; 809 case WSDISPLAYIO_SVIDEO: 810 case WSDISPLAYIO_GVIDEO: 811 case WSDISPLAYIO_GCURPOS: 812 case WSDISPLAYIO_SCURPOS: 813 case WSDISPLAYIO_GCURMAX: 814 case WSDISPLAYIO_SCURSOR: 815 return sunxi_debe_ioctl(sc->sc_debedev, cmd, data); 816 #if NAWIN_MP > 0 817 case WSDISPLAYIO_FILL: 818 case WSDISPLAYIO_COPY: 819 case WSDISPLAYIO_SYNC: 820 if (sc->sc_mpdev == NULL) 821 return EPASSTHROUGH; 822 return sunxi_mp_ioctl(sc->sc_mpdev, cmd, data); 823 #endif 824 default: 825 return EPASSTHROUGH; 826 } 827 } 828 829 static paddr_t 830 sunxi_befb_mmap(void *v, void *vs, off_t off, int prot) 831 { 832 struct sunxi_befb_softc *sc = v; 833 834 if (off < 0 || off >= sc->sc_dmasegs[0].ds_len) 835 return -1; 836 837 return bus_dmamem_mmap(sc->sc_dmat, sc->sc_dmasegs, sc->sc_ndmasegs, 838 off, prot, BUS_DMA_PREFETCHABLE); 839 } 840 841 static bool 842 sunxi_befb_shutdown(device_t self, int flags) 843 { 844 genfb_enable_polling(self); 845 return true; 846 } 847 848 static void 849 sunxi_befb_set_videomode(device_t dev, u_int width, u_int height) 850 { 851 struct sunxi_befb_softc *sc = device_private(dev); 852 853 if (sc->sc_gen.sc_width != width || sc->sc_gen.sc_height != height) { 854 device_printf(sc->sc_gen.sc_dev, 855 "mode switching not yet supported\n"); 856 } 857 } 858 859 int 860 sunxi_debe_pipeline(int phandle, bool active) 861 { 862 device_t dev; 863 struct sunxi_debe_softc *sc; 864 struct fdt_endpoint *ep; 865 int i, error; 866 867 if (!active) 868 return EOPNOTSUPP; 869 870 for (i = 0;;i++) { 871 dev = device_find_by_driver_unit("sunxidebe", i); 872 if (dev == NULL) 873 return ENODEV; 874 sc = device_private(dev); 875 if (sc->sc_phandle == phandle) 876 break; 877 } 878 aprint_normal("activate %s\n", device_xname(dev)); 879 if (clk_enable(sc->sc_clk_ahb) != 0 || 880 clk_enable(sc->sc_clk_mod) != 0) { 881 aprint_error_dev(dev, "couldn't enable clocks\n"); 882 return EIO; 883 } 884 /* connect debd0 to tcon0, debe1 to tcon1 */ 885 ep = fdt_endpoint_get_from_index(&sc->sc_ports, SUNXI_PORT_OUTPUT, 886 sc->sc_unit); 887 if (ep == NULL) { 888 aprint_error_dev(dev, "no output endpoint for %d\n", 889 sc->sc_unit); 890 return ENODEV; 891 } 892 error = fdt_endpoint_activate(ep, true); 893 if (error == 0) { 894 sc->sc_out_ep = ep; 895 fdt_endpoint_enable(ep, true); 896 } 897 return error; 898 } 899 900 #if defined(SUNXI_DEBE_DEBUG) 901 void 902 sunxi_debe_dump_regs(int u) 903 { 904 static const struct { 905 const char *name; 906 uint16_t reg; 907 } regs[] = { 908 { "SUNXI_DEBE_MODCTL_REG", SUNXI_DEBE_MODCTL_REG}, 909 { "SUNXI_DEBE_BACKCOLOR_REG", SUNXI_DEBE_BACKCOLOR_REG}, 910 { "SUNXI_DEBE_DISSIZE_REG", SUNXI_DEBE_DISSIZE_REG}, 911 { "SUNXI_DEBE_LAYSIZE_REG", SUNXI_DEBE_LAYSIZE_REG}, 912 { "SUNXI_DEBE_LAYCOOR_REG", SUNXI_DEBE_LAYCOOR_REG}, 913 { "SUNXI_DEBE_LAYLINEWIDTH_REG", SUNXI_DEBE_LAYLINEWIDTH_REG}, 914 { "SUNXI_DEBE_LAYFB_L32ADD_REG", SUNXI_DEBE_LAYFB_L32ADD_REG}, 915 { "SUNXI_DEBE_LAYFB_H4ADD_REG", SUNXI_DEBE_LAYFB_H4ADD_REG}, 916 { "SUNXI_DEBE_REGBUFFCTL_REG", SUNXI_DEBE_REGBUFFCTL_REG}, 917 { "SUNXI_DEBE_CKMAX_REG", SUNXI_DEBE_CKMAX_REG}, 918 { "SUNXI_DEBE_CKMIN_REG", SUNXI_DEBE_CKMIN_REG}, 919 { "SUNXI_DEBE_CKCFG_REG", SUNXI_DEBE_CKCFG_REG}, 920 { "SUNXI_DEBE_ATTCTL0_REG", SUNXI_DEBE_ATTCTL0_REG}, 921 { "SUNXI_DEBE_ATTCTL1_REG", SUNXI_DEBE_ATTCTL1_REG}, 922 { "SUNXI_DEBE_HWCCTL_REG", SUNXI_DEBE_HWCCTL_REG}, 923 { "SUNXI_DEBE_HWCFBCTL_REG", SUNXI_DEBE_HWCFBCTL_REG}, 924 { "SUNXI_DEBE_WBCTL_REG", SUNXI_DEBE_WBCTL_REG}, 925 { "SUNXI_DEBE_WBADD_REG", SUNXI_DEBE_WBADD_REG}, 926 { "SUNXI_DEBE_WBLINEWIDTH_REG", SUNXI_DEBE_WBLINEWIDTH_REG}, 927 { "SUNXI_DEBE_IYUVCTL_REG", SUNXI_DEBE_IYUVCTL_REG}, 928 { "SUNXI_DEBE_IYUVADD_REG", SUNXI_DEBE_IYUVADD_REG}, 929 { "SUNXI_DEBE_IYUVLINEWIDTH_REG", SUNXI_DEBE_IYUVLINEWIDTH_REG}, 930 { "SUNXI_DEBE_YGCOEF_REG", SUNXI_DEBE_YGCOEF_REG}, 931 { "SUNXI_DEBE_YGCONS_REG", SUNXI_DEBE_YGCONS_REG}, 932 { "SUNXI_DEBE_URCOEF_REG", SUNXI_DEBE_URCOEF_REG}, 933 { "SUNXI_DEBE_URCONS_REG", SUNXI_DEBE_URCONS_REG}, 934 { "SUNXI_DEBE_VBCOEF_REG", SUNXI_DEBE_VBCOEF_REG}, 935 { "SUNXI_DEBE_VBCONS_REG", SUNXI_DEBE_VBCONS_REG}, 936 { "SUNXI_DEBE_OCCTL_REG", SUNXI_DEBE_OCCTL_REG}, 937 { "SUNXI_DEBE_OCRCOEF_REG", SUNXI_DEBE_OCRCOEF_REG}, 938 { "SUNXI_DEBE_OCRCONS_REG", SUNXI_DEBE_OCRCONS_REG}, 939 { "SUNXI_DEBE_OCGCOEF_REG", SUNXI_DEBE_OCGCOEF_REG}, 940 { "SUNXI_DEBE_OCGCONS_REG", SUNXI_DEBE_OCGCONS_REG}, 941 { "SUNXI_DEBE_OCBCOEF_REG", SUNXI_DEBE_OCBCOEF_REG}, 942 { "SUNXI_DEBE_OCBCONS_REG", SUNXI_DEBE_OCBCONS_REG}, 943 }; 944 struct sunxi_debe_softc *sc; 945 device_t dev; 946 947 dev = device_find_by_driver_unit("sunxidebe", u); 948 if (dev == NULL) 949 return; 950 sc = device_private(dev); 951 952 for (int i = 0; i < __arraycount(regs); i++) { 953 printf("%s: 0x%08x\n", regs[i].name, 954 DEBE_READ(sc, regs[i].reg)); 955 } 956 } 957 #endif 958
Indexes created Tue Sep 30 20:09:53 GMT 2025