sunxi_emac.c revision 1.13.2.1
1 /* $NetBSD: sunxi_emac.c,v 1.13.2.1 2018/05/02 07:20:04 pgoyette Exp $ */ 2 3 /*- 4 * Copyright (c) 2016-2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Allwinner Gigabit Ethernet MAC (EMAC) controller 31 */ 32 33 #include "opt_net_mpsafe.h" 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: sunxi_emac.c,v 1.13.2.1 2018/05/02 07:20:04 pgoyette Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/bus.h> 40 #include <sys/device.h> 41 #include <sys/intr.h> 42 #include <sys/systm.h> 43 #include <sys/kernel.h> 44 #include <sys/mutex.h> 45 #include <sys/callout.h> 46 #include <sys/gpio.h> 47 #include <sys/cprng.h> 48 49 #include <net/if.h> 50 #include <net/if_dl.h> 51 #include <net/if_ether.h> 52 #include <net/if_media.h> 53 #include <net/bpf.h> 54 55 #include <dev/mii/miivar.h> 56 57 #include <dev/fdt/fdtvar.h> 58 59 #include <arm/sunxi/sunxi_emac.h> 60 61 #ifdef NET_MPSAFE 62 #define EMAC_MPSAFE 1 63 #define CALLOUT_FLAGS CALLOUT_MPSAFE 64 #define FDT_INTR_FLAGS FDT_INTR_MPSAFE 65 #else 66 #define CALLOUT_FLAGS 0 67 #define FDT_INTR_FLAGS 0 68 #endif 69 70 #define EMAC_IFNAME "emac%d" 71 72 #define ETHER_ALIGN 2 73 74 #define EMAC_LOCK(sc) mutex_enter(&(sc)->mtx) 75 #define EMAC_UNLOCK(sc) mutex_exit(&(sc)->mtx) 76 #define EMAC_ASSERT_LOCKED(sc) KASSERT(mutex_owned(&(sc)->mtx)) 77 78 #define DESC_ALIGN sizeof(struct sunxi_emac_desc) 79 #define TX_DESC_COUNT 1024 80 #define TX_DESC_SIZE (sizeof(struct sunxi_emac_desc) * TX_DESC_COUNT) 81 #define RX_DESC_COUNT 256 82 #define RX_DESC_SIZE (sizeof(struct sunxi_emac_desc) * RX_DESC_COUNT) 83 84 #define DESC_OFF(n) ((n) * sizeof(struct sunxi_emac_desc)) 85 #define TX_NEXT(n) (((n) + 1) & (TX_DESC_COUNT - 1)) 86 #define TX_SKIP(n, o) (((n) + (o)) & (TX_DESC_COUNT - 1)) 87 #define RX_NEXT(n) (((n) + 1) & (RX_DESC_COUNT - 1)) 88 89 #define TX_MAX_SEGS 128 90 91 #define SOFT_RST_RETRY 1000 92 #define MII_BUSY_RETRY 1000 93 #define MDIO_FREQ 2500000 94 95 #define BURST_LEN_DEFAULT 8 96 #define RX_TX_PRI_DEFAULT 0 97 #define PAUSE_TIME_DEFAULT 0x400 98 99 /* syscon EMAC clock register */ 100 #define EMAC_CLK_REG 0x30 101 #define EMAC_CLK_EPHY_ADDR (0x1f << 20) /* H3 */ 102 #define EMAC_CLK_EPHY_ADDR_SHIFT 20 103 #define EMAC_CLK_EPHY_LED_POL (1 << 17) /* H3 */ 104 #define EMAC_CLK_EPHY_SHUTDOWN (1 << 16) /* H3 */ 105 #define EMAC_CLK_EPHY_SELECT (1 << 15) /* H3 */ 106 #define EMAC_CLK_RMII_EN (1 << 13) 107 #define EMAC_CLK_ETXDC (0x7 << 10) 108 #define EMAC_CLK_ETXDC_SHIFT 10 109 #define EMAC_CLK_ERXDC (0x1f << 5) 110 #define EMAC_CLK_ERXDC_SHIFT 5 111 #define EMAC_CLK_PIT (0x1 << 2) 112 #define EMAC_CLK_PIT_MII (0 << 2) 113 #define EMAC_CLK_PIT_RGMII (1 << 2) 114 #define EMAC_CLK_SRC (0x3 << 0) 115 #define EMAC_CLK_SRC_MII (0 << 0) 116 #define EMAC_CLK_SRC_EXT_RGMII (1 << 0) 117 #define EMAC_CLK_SRC_RGMII (2 << 0) 118 119 /* Burst length of RX and TX DMA transfers */ 120 static int sunxi_emac_burst_len = BURST_LEN_DEFAULT; 121 122 /* RX / TX DMA priority. If 1, RX DMA has priority over TX DMA. */ 123 static int sunxi_emac_rx_tx_pri = RX_TX_PRI_DEFAULT; 124 125 /* Pause time field in the transmitted control frame */ 126 static int sunxi_emac_pause_time = PAUSE_TIME_DEFAULT; 127 128 enum sunxi_emac_type { 129 EMAC_A64 = 1, 130 EMAC_A83T, 131 EMAC_H3, 132 EMAC_H6, 133 }; 134 135 static const struct of_compat_data compat_data[] = { 136 { "allwinner,sun8i-a83t-emac", EMAC_A83T }, 137 { "allwinner,sun8i-h3-emac", EMAC_H3 }, 138 { "allwinner,sun50i-a64-emac", EMAC_A64 }, 139 { "allwinner,sun50i-h6-emac", EMAC_H6 }, 140 { NULL } 141 }; 142 143 struct sunxi_emac_bufmap { 144 bus_dmamap_t map; 145 struct mbuf *mbuf; 146 }; 147 148 struct sunxi_emac_txring { 149 bus_dma_tag_t desc_tag; 150 bus_dmamap_t desc_map; 151 bus_dma_segment_t desc_dmaseg; 152 struct sunxi_emac_desc *desc_ring; 153 bus_addr_t desc_ring_paddr; 154 bus_dma_tag_t buf_tag; 155 struct sunxi_emac_bufmap buf_map[TX_DESC_COUNT]; 156 u_int cur, next, queued; 157 }; 158 159 struct sunxi_emac_rxring { 160 bus_dma_tag_t desc_tag; 161 bus_dmamap_t desc_map; 162 bus_dma_segment_t desc_dmaseg; 163 struct sunxi_emac_desc *desc_ring; 164 bus_addr_t desc_ring_paddr; 165 bus_dma_tag_t buf_tag; 166 struct sunxi_emac_bufmap buf_map[RX_DESC_COUNT]; 167 u_int cur; 168 }; 169 170 enum { 171 _RES_EMAC, 172 _RES_SYSCON, 173 _RES_NITEMS 174 }; 175 176 struct sunxi_emac_softc { 177 device_t dev; 178 int phandle; 179 enum sunxi_emac_type type; 180 bus_space_tag_t bst; 181 bus_dma_tag_t dmat; 182 183 bus_space_handle_t bsh[_RES_NITEMS]; 184 struct clk *clk_ahb; 185 struct clk *clk_ephy; 186 struct fdtbus_reset *rst_ahb; 187 struct fdtbus_reset *rst_ephy; 188 struct fdtbus_regulator *reg_phy; 189 struct fdtbus_gpio_pin *pin_reset; 190 191 int phy_id; 192 193 kmutex_t mtx; 194 struct ethercom ec; 195 struct mii_data mii; 196 callout_t stat_ch; 197 void *ih; 198 u_int mdc_div_ratio_m; 199 200 struct sunxi_emac_txring tx; 201 struct sunxi_emac_rxring rx; 202 }; 203 204 #define RD4(sc, reg) \ 205 bus_space_read_4((sc)->bst, (sc)->bsh[_RES_EMAC], (reg)) 206 #define WR4(sc, reg, val) \ 207 bus_space_write_4((sc)->bst, (sc)->bsh[_RES_EMAC], (reg), (val)) 208 209 #define SYSCONRD4(sc, reg) \ 210 bus_space_read_4((sc)->bst, (sc)->bsh[_RES_SYSCON], (reg)) 211 #define SYSCONWR4(sc, reg, val) \ 212 bus_space_write_4((sc)->bst, (sc)->bsh[_RES_SYSCON], (reg), (val)) 213 214 static int 215 sunxi_emac_mii_readreg(device_t dev, int phy, int reg) 216 { 217 struct sunxi_emac_softc *sc = device_private(dev); 218 int retry, val; 219 220 val = 0; 221 222 WR4(sc, EMAC_MII_CMD, 223 (sc->mdc_div_ratio_m << MDC_DIV_RATIO_M_SHIFT) | 224 (phy << PHY_ADDR_SHIFT) | 225 (reg << PHY_REG_ADDR_SHIFT) | 226 MII_BUSY); 227 for (retry = MII_BUSY_RETRY; retry > 0; retry--) { 228 if ((RD4(sc, EMAC_MII_CMD) & MII_BUSY) == 0) { 229 val = RD4(sc, EMAC_MII_DATA); 230 break; 231 } 232 delay(10); 233 } 234 235 if (retry == 0) 236 device_printf(dev, "phy read timeout, phy=%d reg=%d\n", 237 phy, reg); 238 239 return val; 240 } 241 242 static void 243 sunxi_emac_mii_writereg(device_t dev, int phy, int reg, int val) 244 { 245 struct sunxi_emac_softc *sc = device_private(dev); 246 int retry; 247 248 WR4(sc, EMAC_MII_DATA, val); 249 WR4(sc, EMAC_MII_CMD, 250 (sc->mdc_div_ratio_m << MDC_DIV_RATIO_M_SHIFT) | 251 (phy << PHY_ADDR_SHIFT) | 252 (reg << PHY_REG_ADDR_SHIFT) | 253 MII_WR | MII_BUSY); 254 for (retry = MII_BUSY_RETRY; retry > 0; retry--) { 255 if ((RD4(sc, EMAC_MII_CMD) & MII_BUSY) == 0) 256 break; 257 delay(10); 258 } 259 260 if (retry == 0) 261 device_printf(dev, "phy write timeout, phy=%d reg=%d\n", 262 phy, reg); 263 } 264 265 static void 266 sunxi_emac_update_link(struct sunxi_emac_softc *sc) 267 { 268 struct mii_data *mii = &sc->mii; 269 uint32_t val; 270 271 val = RD4(sc, EMAC_BASIC_CTL_0); 272 val &= ~(BASIC_CTL_SPEED | BASIC_CTL_DUPLEX); 273 274 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 275 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 276 val |= BASIC_CTL_SPEED_1000 << BASIC_CTL_SPEED_SHIFT; 277 else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) 278 val |= BASIC_CTL_SPEED_100 << BASIC_CTL_SPEED_SHIFT; 279 else 280 val |= BASIC_CTL_SPEED_10 << BASIC_CTL_SPEED_SHIFT; 281 282 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 283 val |= BASIC_CTL_DUPLEX; 284 285 WR4(sc, EMAC_BASIC_CTL_0, val); 286 287 val = RD4(sc, EMAC_RX_CTL_0); 288 val &= ~RX_FLOW_CTL_EN; 289 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 290 val |= RX_FLOW_CTL_EN; 291 WR4(sc, EMAC_RX_CTL_0, val); 292 293 val = RD4(sc, EMAC_TX_FLOW_CTL); 294 val &= ~(PAUSE_TIME|TX_FLOW_CTL_EN); 295 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 296 val |= TX_FLOW_CTL_EN; 297 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 298 val |= sunxi_emac_pause_time << PAUSE_TIME_SHIFT; 299 WR4(sc, EMAC_TX_FLOW_CTL, val); 300 } 301 302 static void 303 sunxi_emac_mii_statchg(struct ifnet *ifp) 304 { 305 struct sunxi_emac_softc * const sc = ifp->if_softc; 306 307 sunxi_emac_update_link(sc); 308 } 309 310 static void 311 sunxi_emac_dma_sync(struct sunxi_emac_softc *sc, bus_dma_tag_t dmat, 312 bus_dmamap_t map, int start, int end, int total, int flags) 313 { 314 if (end > start) { 315 bus_dmamap_sync(dmat, map, DESC_OFF(start), 316 DESC_OFF(end) - DESC_OFF(start), flags); 317 } else { 318 bus_dmamap_sync(dmat, map, DESC_OFF(start), 319 DESC_OFF(total) - DESC_OFF(start), flags); 320 if (DESC_OFF(end) - DESC_OFF(0) > 0) 321 bus_dmamap_sync(dmat, map, DESC_OFF(0), 322 DESC_OFF(end) - DESC_OFF(0), flags); 323 } 324 } 325 326 static void 327 sunxi_emac_setup_txdesc(struct sunxi_emac_softc *sc, int index, int flags, 328 bus_addr_t paddr, u_int len) 329 { 330 uint32_t status, size; 331 332 if (paddr == 0 || len == 0) { 333 status = 0; 334 size = 0; 335 --sc->tx.queued; 336 } else { 337 status = TX_DESC_CTL; 338 size = flags | len; 339 ++sc->tx.queued; 340 } 341 342 sc->tx.desc_ring[index].addr = htole32((uint32_t)paddr); 343 sc->tx.desc_ring[index].size = htole32(size); 344 sc->tx.desc_ring[index].status = htole32(status); 345 } 346 347 static int 348 sunxi_emac_setup_txbuf(struct sunxi_emac_softc *sc, int index, struct mbuf *m) 349 { 350 bus_dma_segment_t *segs; 351 int error, nsegs, cur, i, flags; 352 u_int csum_flags; 353 354 error = bus_dmamap_load_mbuf(sc->tx.buf_tag, 355 sc->tx.buf_map[index].map, m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 356 if (error == EFBIG) { 357 device_printf(sc->dev, 358 "TX packet needs too many DMA segments, dropping...\n"); 359 m_freem(m); 360 return 0; 361 } 362 if (error != 0) 363 return 0; 364 365 segs = sc->tx.buf_map[index].map->dm_segs; 366 nsegs = sc->tx.buf_map[index].map->dm_nsegs; 367 368 flags = TX_FIR_DESC; 369 if ((m->m_pkthdr.csum_flags & M_CSUM_IPv4) != 0) { 370 if ((m->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) != 0) 371 csum_flags = TX_CHECKSUM_CTL_FULL; 372 else 373 csum_flags = TX_CHECKSUM_CTL_IP; 374 flags |= (csum_flags << TX_CHECKSUM_CTL_SHIFT); 375 } 376 377 for (cur = index, i = 0; i < nsegs; i++) { 378 sc->tx.buf_map[cur].mbuf = (i == 0 ? m : NULL); 379 if (i == nsegs - 1) 380 flags |= TX_LAST_DESC | TX_INT_CTL; 381 382 sunxi_emac_setup_txdesc(sc, cur, flags, segs[i].ds_addr, 383 segs[i].ds_len); 384 flags &= ~TX_FIR_DESC; 385 cur = TX_NEXT(cur); 386 } 387 388 bus_dmamap_sync(sc->tx.buf_tag, sc->tx.buf_map[index].map, 389 0, sc->tx.buf_map[index].map->dm_mapsize, BUS_DMASYNC_PREWRITE); 390 391 return nsegs; 392 } 393 394 static void 395 sunxi_emac_setup_rxdesc(struct sunxi_emac_softc *sc, int index, 396 bus_addr_t paddr) 397 { 398 uint32_t status, size; 399 400 status = RX_DESC_CTL; 401 size = MCLBYTES - 1; 402 403 sc->rx.desc_ring[index].addr = htole32((uint32_t)paddr); 404 sc->rx.desc_ring[index].size = htole32(size); 405 sc->rx.desc_ring[index].next = 406 htole32(sc->rx.desc_ring_paddr + DESC_OFF(RX_NEXT(index))); 407 sc->rx.desc_ring[index].status = htole32(status); 408 } 409 410 static int 411 sunxi_emac_setup_rxbuf(struct sunxi_emac_softc *sc, int index, struct mbuf *m) 412 { 413 int error; 414 415 m_adj(m, ETHER_ALIGN); 416 417 error = bus_dmamap_load_mbuf(sc->rx.buf_tag, 418 sc->rx.buf_map[index].map, m, BUS_DMA_READ|BUS_DMA_NOWAIT); 419 if (error != 0) 420 return error; 421 422 bus_dmamap_sync(sc->rx.buf_tag, sc->rx.buf_map[index].map, 423 0, sc->rx.buf_map[index].map->dm_mapsize, 424 BUS_DMASYNC_PREREAD); 425 426 sc->rx.buf_map[index].mbuf = m; 427 sunxi_emac_setup_rxdesc(sc, index, 428 sc->rx.buf_map[index].map->dm_segs[0].ds_addr); 429 430 return 0; 431 } 432 433 static struct mbuf * 434 sunxi_emac_alloc_mbufcl(struct sunxi_emac_softc *sc) 435 { 436 struct mbuf *m; 437 438 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 439 if (m != NULL) 440 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 441 442 return m; 443 } 444 445 static void 446 sunxi_emac_start_locked(struct sunxi_emac_softc *sc) 447 { 448 struct ifnet *ifp = &sc->ec.ec_if; 449 struct mbuf *m; 450 uint32_t val; 451 int cnt, nsegs, start; 452 453 EMAC_ASSERT_LOCKED(sc); 454 455 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 456 return; 457 458 for (cnt = 0, start = sc->tx.cur; ; cnt++) { 459 if (sc->tx.queued >= TX_DESC_COUNT - TX_MAX_SEGS) { 460 ifp->if_flags |= IFF_OACTIVE; 461 break; 462 } 463 464 IFQ_POLL(&ifp->if_snd, m); 465 if (m == NULL) 466 break; 467 468 nsegs = sunxi_emac_setup_txbuf(sc, sc->tx.cur, m); 469 if (nsegs == 0) { 470 ifp->if_flags |= IFF_OACTIVE; 471 break; 472 } 473 IFQ_DEQUEUE(&ifp->if_snd, m); 474 bpf_mtap(ifp, m); 475 476 sc->tx.cur = TX_SKIP(sc->tx.cur, nsegs); 477 } 478 479 if (cnt != 0) { 480 sunxi_emac_dma_sync(sc, sc->tx.desc_tag, sc->tx.desc_map, 481 start, sc->tx.cur, TX_DESC_COUNT, 482 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 483 484 /* Start and run TX DMA */ 485 val = RD4(sc, EMAC_TX_CTL_1); 486 WR4(sc, EMAC_TX_CTL_1, val | TX_DMA_START); 487 } 488 } 489 490 static void 491 sunxi_emac_start(struct ifnet *ifp) 492 { 493 struct sunxi_emac_softc *sc = ifp->if_softc; 494 495 EMAC_LOCK(sc); 496 sunxi_emac_start_locked(sc); 497 EMAC_UNLOCK(sc); 498 } 499 500 static void 501 sunxi_emac_tick(void *softc) 502 { 503 struct sunxi_emac_softc *sc = softc; 504 struct mii_data *mii = &sc->mii; 505 #ifndef EMAC_MPSAFE 506 int s = splnet(); 507 #endif 508 509 EMAC_LOCK(sc); 510 mii_tick(mii); 511 callout_schedule(&sc->stat_ch, hz); 512 EMAC_UNLOCK(sc); 513 514 #ifndef EMAC_MPSAFE 515 splx(s); 516 #endif 517 } 518 519 /* Bit Reversal - http://aggregate.org/MAGIC/#Bit%20Reversal */ 520 static uint32_t 521 bitrev32(uint32_t x) 522 { 523 x = (((x & 0xaaaaaaaa) >> 1) | ((x & 0x55555555) << 1)); 524 x = (((x & 0xcccccccc) >> 2) | ((x & 0x33333333) << 2)); 525 x = (((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4)); 526 x = (((x & 0xff00ff00) >> 8) | ((x & 0x00ff00ff) << 8)); 527 528 return (x >> 16) | (x << 16); 529 } 530 531 static void 532 sunxi_emac_setup_rxfilter(struct sunxi_emac_softc *sc) 533 { 534 struct ifnet *ifp = &sc->ec.ec_if; 535 uint32_t val, crc, hashreg, hashbit, hash[2], machi, maclo; 536 struct ether_multi *enm; 537 struct ether_multistep step; 538 const uint8_t *eaddr; 539 540 EMAC_ASSERT_LOCKED(sc); 541 542 val = 0; 543 hash[0] = hash[1] = 0; 544 545 if ((ifp->if_flags & IFF_PROMISC) != 0) 546 val |= DIS_ADDR_FILTER; 547 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 548 val |= RX_ALL_MULTICAST; 549 hash[0] = hash[1] = ~0; 550 } else { 551 val |= HASH_MULTICAST; 552 ETHER_FIRST_MULTI(step, &sc->ec, enm); 553 while (enm != NULL) { 554 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 555 crc &= 0x7f; 556 crc = bitrev32(~crc) >> 26; 557 hashreg = (crc >> 5); 558 hashbit = (crc & 0x1f); 559 hash[hashreg] |= (1 << hashbit); 560 ETHER_NEXT_MULTI(step, enm); 561 } 562 } 563 564 /* Write our unicast address */ 565 eaddr = CLLADDR(ifp->if_sadl); 566 machi = (eaddr[5] << 8) | eaddr[4]; 567 maclo = (eaddr[3] << 24) | (eaddr[2] << 16) | (eaddr[1] << 8) | 568 (eaddr[0] << 0); 569 WR4(sc, EMAC_ADDR_HIGH(0), machi); 570 WR4(sc, EMAC_ADDR_LOW(0), maclo); 571 572 /* Multicast hash filters */ 573 WR4(sc, EMAC_RX_HASH_0, hash[1]); 574 WR4(sc, EMAC_RX_HASH_1, hash[0]); 575 576 /* RX frame filter config */ 577 WR4(sc, EMAC_RX_FRM_FLT, val); 578 } 579 580 static void 581 sunxi_emac_enable_intr(struct sunxi_emac_softc *sc) 582 { 583 /* Enable interrupts */ 584 WR4(sc, EMAC_INT_EN, RX_INT_EN | TX_INT_EN | TX_BUF_UA_INT_EN); 585 } 586 587 static void 588 sunxi_emac_disable_intr(struct sunxi_emac_softc *sc) 589 { 590 /* Disable interrupts */ 591 WR4(sc, EMAC_INT_EN, 0); 592 } 593 594 static int 595 sunxi_emac_init_locked(struct sunxi_emac_softc *sc) 596 { 597 struct ifnet *ifp = &sc->ec.ec_if; 598 struct mii_data *mii = &sc->mii; 599 uint32_t val; 600 601 EMAC_ASSERT_LOCKED(sc); 602 603 if ((ifp->if_flags & IFF_RUNNING) != 0) 604 return 0; 605 606 sunxi_emac_setup_rxfilter(sc); 607 608 /* Configure DMA burst length and priorities */ 609 val = sunxi_emac_burst_len << BASIC_CTL_BURST_LEN_SHIFT; 610 if (sunxi_emac_rx_tx_pri) 611 val |= BASIC_CTL_RX_TX_PRI; 612 WR4(sc, EMAC_BASIC_CTL_1, val); 613 614 /* Enable interrupts */ 615 sunxi_emac_enable_intr(sc); 616 617 /* Enable transmit DMA */ 618 val = RD4(sc, EMAC_TX_CTL_1); 619 WR4(sc, EMAC_TX_CTL_1, val | TX_DMA_EN | TX_MD | TX_NEXT_FRAME); 620 621 /* Enable receive DMA */ 622 val = RD4(sc, EMAC_RX_CTL_1); 623 WR4(sc, EMAC_RX_CTL_1, val | RX_DMA_EN | RX_MD); 624 625 /* Enable transmitter */ 626 val = RD4(sc, EMAC_TX_CTL_0); 627 WR4(sc, EMAC_TX_CTL_0, val | TX_EN); 628 629 /* Enable receiver */ 630 val = RD4(sc, EMAC_RX_CTL_0); 631 WR4(sc, EMAC_RX_CTL_0, val | RX_EN | CHECK_CRC); 632 633 ifp->if_flags |= IFF_RUNNING; 634 ifp->if_flags &= ~IFF_OACTIVE; 635 636 mii_mediachg(mii); 637 callout_schedule(&sc->stat_ch, hz); 638 639 return 0; 640 } 641 642 static int 643 sunxi_emac_init(struct ifnet *ifp) 644 { 645 struct sunxi_emac_softc *sc = ifp->if_softc; 646 int error; 647 648 EMAC_LOCK(sc); 649 error = sunxi_emac_init_locked(sc); 650 EMAC_UNLOCK(sc); 651 652 return error; 653 } 654 655 static void 656 sunxi_emac_stop_locked(struct sunxi_emac_softc *sc, int disable) 657 { 658 struct ifnet *ifp = &sc->ec.ec_if; 659 uint32_t val; 660 661 EMAC_ASSERT_LOCKED(sc); 662 663 callout_stop(&sc->stat_ch); 664 665 mii_down(&sc->mii); 666 667 /* Stop transmit DMA and flush data in the TX FIFO */ 668 val = RD4(sc, EMAC_TX_CTL_1); 669 val &= ~TX_DMA_EN; 670 val |= FLUSH_TX_FIFO; 671 WR4(sc, EMAC_TX_CTL_1, val); 672 673 /* Disable transmitter */ 674 val = RD4(sc, EMAC_TX_CTL_0); 675 WR4(sc, EMAC_TX_CTL_0, val & ~TX_EN); 676 677 /* Disable receiver */ 678 val = RD4(sc, EMAC_RX_CTL_0); 679 WR4(sc, EMAC_RX_CTL_0, val & ~RX_EN); 680 681 /* Disable interrupts */ 682 sunxi_emac_disable_intr(sc); 683 684 /* Disable transmit DMA */ 685 val = RD4(sc, EMAC_TX_CTL_1); 686 WR4(sc, EMAC_TX_CTL_1, val & ~TX_DMA_EN); 687 688 /* Disable receive DMA */ 689 val = RD4(sc, EMAC_RX_CTL_1); 690 WR4(sc, EMAC_RX_CTL_1, val & ~RX_DMA_EN); 691 692 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 693 } 694 695 static void 696 sunxi_emac_stop(struct ifnet *ifp, int disable) 697 { 698 struct sunxi_emac_softc * const sc = ifp->if_softc; 699 700 EMAC_LOCK(sc); 701 sunxi_emac_stop_locked(sc, disable); 702 EMAC_UNLOCK(sc); 703 } 704 705 static int 706 sunxi_emac_rxintr(struct sunxi_emac_softc *sc) 707 { 708 struct ifnet *ifp = &sc->ec.ec_if; 709 int error, index, len, npkt; 710 struct mbuf *m, *m0; 711 uint32_t status; 712 713 npkt = 0; 714 715 for (index = sc->rx.cur; ; index = RX_NEXT(index)) { 716 sunxi_emac_dma_sync(sc, sc->rx.desc_tag, sc->rx.desc_map, 717 index, index + 1, 718 RX_DESC_COUNT, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 719 720 status = le32toh(sc->rx.desc_ring[index].status); 721 if ((status & RX_DESC_CTL) != 0) 722 break; 723 724 bus_dmamap_sync(sc->rx.buf_tag, sc->rx.buf_map[index].map, 725 0, sc->rx.buf_map[index].map->dm_mapsize, 726 BUS_DMASYNC_POSTREAD); 727 bus_dmamap_unload(sc->rx.buf_tag, sc->rx.buf_map[index].map); 728 729 len = (status & RX_FRM_LEN) >> RX_FRM_LEN_SHIFT; 730 if (len != 0) { 731 m = sc->rx.buf_map[index].mbuf; 732 m_set_rcvif(m, ifp); 733 m->m_flags |= M_HASFCS; 734 m->m_pkthdr.len = len; 735 m->m_len = len; 736 m->m_nextpkt = NULL; 737 738 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) != 0 && 739 (status & RX_FRM_TYPE) != 0) { 740 m->m_pkthdr.csum_flags = M_CSUM_IPv4 | 741 M_CSUM_TCPv4 | M_CSUM_UDPv4; 742 if ((status & RX_HEADER_ERR) != 0) 743 m->m_pkthdr.csum_flags |= 744 M_CSUM_IPv4_BAD; 745 if ((status & RX_PAYLOAD_ERR) != 0) 746 m->m_pkthdr.csum_flags |= 747 M_CSUM_TCP_UDP_BAD; 748 } 749 750 ++npkt; 751 752 if_percpuq_enqueue(ifp->if_percpuq, m); 753 } 754 755 if ((m0 = sunxi_emac_alloc_mbufcl(sc)) != NULL) { 756 error = sunxi_emac_setup_rxbuf(sc, index, m0); 757 if (error != 0) { 758 /* XXX hole in RX ring */ 759 } 760 } else 761 ifp->if_ierrors++; 762 763 sunxi_emac_dma_sync(sc, sc->rx.desc_tag, sc->rx.desc_map, 764 index, index + 1, 765 RX_DESC_COUNT, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 766 } 767 768 sc->rx.cur = index; 769 770 return npkt; 771 } 772 773 static void 774 sunxi_emac_txintr(struct sunxi_emac_softc *sc) 775 { 776 struct ifnet *ifp = &sc->ec.ec_if; 777 struct sunxi_emac_bufmap *bmap; 778 struct sunxi_emac_desc *desc; 779 uint32_t status; 780 int i; 781 782 EMAC_ASSERT_LOCKED(sc); 783 784 for (i = sc->tx.next; sc->tx.queued > 0; i = TX_NEXT(i)) { 785 KASSERT(sc->tx.queued > 0 && sc->tx.queued <= TX_DESC_COUNT); 786 sunxi_emac_dma_sync(sc, sc->tx.desc_tag, sc->tx.desc_map, 787 i, i + 1, TX_DESC_COUNT, 788 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 789 desc = &sc->tx.desc_ring[i]; 790 status = le32toh(desc->status); 791 if ((status & TX_DESC_CTL) != 0) 792 break; 793 bmap = &sc->tx.buf_map[i]; 794 if (bmap->mbuf != NULL) { 795 bus_dmamap_sync(sc->tx.buf_tag, bmap->map, 796 0, bmap->map->dm_mapsize, 797 BUS_DMASYNC_POSTWRITE); 798 bus_dmamap_unload(sc->tx.buf_tag, bmap->map); 799 m_freem(bmap->mbuf); 800 bmap->mbuf = NULL; 801 } 802 803 sunxi_emac_setup_txdesc(sc, i, 0, 0, 0); 804 sunxi_emac_dma_sync(sc, sc->tx.desc_tag, sc->tx.desc_map, 805 i, i + 1, TX_DESC_COUNT, 806 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 807 808 ifp->if_flags &= ~IFF_OACTIVE; 809 ifp->if_opackets++; 810 } 811 812 sc->tx.next = i; 813 } 814 815 static int 816 sunxi_emac_intr(void *arg) 817 { 818 struct sunxi_emac_softc *sc = arg; 819 struct ifnet *ifp = &sc->ec.ec_if; 820 uint32_t val; 821 822 EMAC_LOCK(sc); 823 824 val = RD4(sc, EMAC_INT_STA); 825 WR4(sc, EMAC_INT_STA, val); 826 827 if (val & RX_INT) 828 sunxi_emac_rxintr(sc); 829 830 if (val & (TX_INT|TX_BUF_UA_INT)) { 831 sunxi_emac_txintr(sc); 832 if_schedule_deferred_start(ifp); 833 } 834 835 EMAC_UNLOCK(sc); 836 837 return 1; 838 } 839 840 static int 841 sunxi_emac_ioctl(struct ifnet *ifp, u_long cmd, void *data) 842 { 843 struct sunxi_emac_softc *sc = ifp->if_softc; 844 struct mii_data *mii = &sc->mii; 845 struct ifreq *ifr = data; 846 int error, s; 847 848 #ifndef EMAC_MPSAFE 849 s = splnet(); 850 #endif 851 852 switch (cmd) { 853 case SIOCSIFMEDIA: 854 case SIOCGIFMEDIA: 855 #ifdef EMAC_MPSAFE 856 s = splnet(); 857 #endif 858 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 859 #ifdef EMAC_MPSAFE 860 splx(s); 861 #endif 862 break; 863 default: 864 #ifdef EMAC_MPSAFE 865 s = splnet(); 866 #endif 867 error = ether_ioctl(ifp, cmd, data); 868 #ifdef EMAC_MPSAFE 869 splx(s); 870 #endif 871 if (error != ENETRESET) 872 break; 873 874 error = 0; 875 876 if (cmd == SIOCSIFCAP) 877 error = (*ifp->if_init)(ifp); 878 else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 879 ; 880 else if ((ifp->if_flags & IFF_RUNNING) != 0) { 881 EMAC_LOCK(sc); 882 sunxi_emac_setup_rxfilter(sc); 883 EMAC_UNLOCK(sc); 884 } 885 break; 886 } 887 888 #ifndef EMAC_MPSAFE 889 splx(s); 890 #endif 891 892 return error; 893 } 894 895 static bool 896 sunxi_emac_has_internal_phy(struct sunxi_emac_softc *sc) 897 { 898 const char * mdio_internal_compat[] = { 899 "allwinner,sun8i-h3-mdio-internal", 900 NULL 901 }; 902 int phy; 903 904 /* Non-standard property, for compatible with old dts files */ 905 if (of_hasprop(sc->phandle, "allwinner,use-internal-phy")) 906 return true; 907 908 phy = fdtbus_get_phandle(sc->phandle, "phy-handle"); 909 if (phy == -1) 910 return false; 911 912 /* For internal PHY, check compatible string of parent node */ 913 return of_compatible(OF_parent(phy), mdio_internal_compat) >= 0; 914 } 915 916 static int 917 sunxi_emac_setup_phy(struct sunxi_emac_softc *sc) 918 { 919 uint32_t reg, tx_delay, rx_delay; 920 const char *phy_type; 921 922 phy_type = fdtbus_get_string(sc->phandle, "phy-mode"); 923 if (phy_type == NULL) 924 return 0; 925 926 aprint_debug_dev(sc->dev, "PHY type: %s\n", phy_type); 927 928 reg = SYSCONRD4(sc, 0); 929 930 reg &= ~(EMAC_CLK_PIT | EMAC_CLK_SRC | EMAC_CLK_RMII_EN); 931 if (strcmp(phy_type, "rgmii") == 0) 932 reg |= EMAC_CLK_PIT_RGMII | EMAC_CLK_SRC_RGMII; 933 else if (strcmp(phy_type, "rmii") == 0) 934 reg |= EMAC_CLK_RMII_EN; 935 else 936 reg |= EMAC_CLK_PIT_MII | EMAC_CLK_SRC_MII; 937 938 if (of_getprop_uint32(sc->phandle, "allwinner,tx-delay-ps", 939 &tx_delay) == 0) { 940 reg &= ~EMAC_CLK_ETXDC; 941 reg |= ((tx_delay / 100) << EMAC_CLK_ETXDC_SHIFT); 942 } else if (of_getprop_uint32(sc->phandle, "tx-delay", &tx_delay) == 0) { 943 reg &= ~EMAC_CLK_ETXDC; 944 reg |= (tx_delay << EMAC_CLK_ETXDC_SHIFT); 945 } 946 if (of_getprop_uint32(sc->phandle, "allwinner,rx-delay-ps", 947 &rx_delay) == 0) { 948 reg &= ~EMAC_CLK_ERXDC; 949 reg |= ((rx_delay / 100) << EMAC_CLK_ERXDC_SHIFT); 950 } else if (of_getprop_uint32(sc->phandle, "rx-delay", &rx_delay) == 0) { 951 reg &= ~EMAC_CLK_ERXDC; 952 reg |= (rx_delay << EMAC_CLK_ERXDC_SHIFT); 953 } 954 955 if (sc->type == EMAC_H3 || sc->type == EMAC_H6) { 956 if (sunxi_emac_has_internal_phy(sc)) { 957 reg |= EMAC_CLK_EPHY_SELECT; 958 reg &= ~EMAC_CLK_EPHY_SHUTDOWN; 959 if (of_hasprop(sc->phandle, 960 "allwinner,leds-active-low")) 961 reg |= EMAC_CLK_EPHY_LED_POL; 962 else 963 reg &= ~EMAC_CLK_EPHY_LED_POL; 964 965 /* Set internal PHY addr to 1 */ 966 reg &= ~EMAC_CLK_EPHY_ADDR; 967 reg |= (1 << EMAC_CLK_EPHY_ADDR_SHIFT); 968 } else { 969 reg &= ~EMAC_CLK_EPHY_SELECT; 970 } 971 } 972 973 aprint_debug_dev(sc->dev, "EMAC clock: 0x%08x\n", reg); 974 975 SYSCONWR4(sc, 0, reg); 976 977 return 0; 978 } 979 980 static int 981 sunxi_emac_setup_resources(struct sunxi_emac_softc *sc) 982 { 983 u_int freq; 984 int error, div; 985 986 /* Configure PHY for MII or RGMII mode */ 987 if (sunxi_emac_setup_phy(sc) != 0) 988 return ENXIO; 989 990 /* Enable clocks */ 991 error = clk_enable(sc->clk_ahb); 992 if (error != 0) { 993 aprint_error_dev(sc->dev, "cannot enable ahb clock\n"); 994 return error; 995 } 996 997 if (sc->clk_ephy != NULL) { 998 error = clk_enable(sc->clk_ephy); 999 if (error != 0) { 1000 aprint_error_dev(sc->dev, "cannot enable ephy clock\n"); 1001 return error; 1002 } 1003 } 1004 1005 /* De-assert reset */ 1006 error = fdtbus_reset_deassert(sc->rst_ahb); 1007 if (error != 0) { 1008 aprint_error_dev(sc->dev, "cannot de-assert ahb reset\n"); 1009 return error; 1010 } 1011 if (sc->rst_ephy != NULL) { 1012 error = fdtbus_reset_deassert(sc->rst_ephy); 1013 if (error != 0) { 1014 aprint_error_dev(sc->dev, 1015 "cannot de-assert ephy reset\n"); 1016 return error; 1017 } 1018 } 1019 1020 /* Enable PHY regulator if applicable */ 1021 if (sc->reg_phy != NULL) { 1022 error = fdtbus_regulator_enable(sc->reg_phy); 1023 if (error != 0) { 1024 aprint_error_dev(sc->dev, 1025 "cannot enable PHY regulator\n"); 1026 return error; 1027 } 1028 } 1029 1030 /* Determine MDC clock divide ratio based on AHB clock */ 1031 freq = clk_get_rate(sc->clk_ahb); 1032 if (freq == 0) { 1033 aprint_error_dev(sc->dev, "cannot get AHB clock frequency\n"); 1034 return ENXIO; 1035 } 1036 div = freq / MDIO_FREQ; 1037 if (div <= 16) 1038 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_16; 1039 else if (div <= 32) 1040 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_32; 1041 else if (div <= 64) 1042 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_64; 1043 else if (div <= 128) 1044 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_128; 1045 else { 1046 aprint_error_dev(sc->dev, 1047 "cannot determine MDC clock divide ratio\n"); 1048 return ENXIO; 1049 } 1050 1051 aprint_debug_dev(sc->dev, "AHB frequency %u Hz, MDC div: 0x%x\n", 1052 freq, sc->mdc_div_ratio_m); 1053 1054 return 0; 1055 } 1056 1057 static void 1058 sunxi_emac_get_eaddr(struct sunxi_emac_softc *sc, uint8_t *eaddr) 1059 { 1060 uint32_t maclo, machi; 1061 #if notyet 1062 u_char rootkey[16]; 1063 #endif 1064 1065 machi = RD4(sc, EMAC_ADDR_HIGH(0)) & 0xffff; 1066 maclo = RD4(sc, EMAC_ADDR_LOW(0)); 1067 1068 if (maclo == 0xffffffff && machi == 0xffff) { 1069 #if notyet 1070 /* MAC address in hardware is invalid, create one */ 1071 if (aw_sid_get_rootkey(rootkey) == 0 && 1072 (rootkey[3] | rootkey[12] | rootkey[13] | rootkey[14] | 1073 rootkey[15]) != 0) { 1074 /* MAC address is derived from the root key in SID */ 1075 maclo = (rootkey[13] << 24) | (rootkey[12] << 16) | 1076 (rootkey[3] << 8) | 0x02; 1077 machi = (rootkey[15] << 8) | rootkey[14]; 1078 } else { 1079 #endif 1080 /* Create one */ 1081 maclo = 0x00f2 | (cprng_strong32() & 0xffff0000); 1082 machi = cprng_strong32() & 0xffff; 1083 #if notyet 1084 } 1085 #endif 1086 } 1087 1088 eaddr[0] = maclo & 0xff; 1089 eaddr[1] = (maclo >> 8) & 0xff; 1090 eaddr[2] = (maclo >> 16) & 0xff; 1091 eaddr[3] = (maclo >> 24) & 0xff; 1092 eaddr[4] = machi & 0xff; 1093 eaddr[5] = (machi >> 8) & 0xff; 1094 } 1095 1096 #ifdef SUNXI_EMAC_DEBUG 1097 static void 1098 sunxi_emac_dump_regs(struct sunxi_emac_softc *sc) 1099 { 1100 static const struct { 1101 const char *name; 1102 u_int reg; 1103 } regs[] = { 1104 { "BASIC_CTL_0", EMAC_BASIC_CTL_0 }, 1105 { "BASIC_CTL_1", EMAC_BASIC_CTL_1 }, 1106 { "INT_STA", EMAC_INT_STA }, 1107 { "INT_EN", EMAC_INT_EN }, 1108 { "TX_CTL_0", EMAC_TX_CTL_0 }, 1109 { "TX_CTL_1", EMAC_TX_CTL_1 }, 1110 { "TX_FLOW_CTL", EMAC_TX_FLOW_CTL }, 1111 { "TX_DMA_LIST", EMAC_TX_DMA_LIST }, 1112 { "RX_CTL_0", EMAC_RX_CTL_0 }, 1113 { "RX_CTL_1", EMAC_RX_CTL_1 }, 1114 { "RX_DMA_LIST", EMAC_RX_DMA_LIST }, 1115 { "RX_FRM_FLT", EMAC_RX_FRM_FLT }, 1116 { "RX_HASH_0", EMAC_RX_HASH_0 }, 1117 { "RX_HASH_1", EMAC_RX_HASH_1 }, 1118 { "MII_CMD", EMAC_MII_CMD }, 1119 { "ADDR_HIGH0", EMAC_ADDR_HIGH(0) }, 1120 { "ADDR_LOW0", EMAC_ADDR_LOW(0) }, 1121 { "TX_DMA_STA", EMAC_TX_DMA_STA }, 1122 { "TX_DMA_CUR_DESC", EMAC_TX_DMA_CUR_DESC }, 1123 { "TX_DMA_CUR_BUF", EMAC_TX_DMA_CUR_BUF }, 1124 { "RX_DMA_STA", EMAC_RX_DMA_STA }, 1125 { "RX_DMA_CUR_DESC", EMAC_RX_DMA_CUR_DESC }, 1126 { "RX_DMA_CUR_BUF", EMAC_RX_DMA_CUR_BUF }, 1127 { "RGMII_STA", EMAC_RGMII_STA }, 1128 }; 1129 u_int n; 1130 1131 for (n = 0; n < __arraycount(regs); n++) 1132 device_printf(dev, " %-20s %08x\n", regs[n].name, 1133 RD4(sc, regs[n].reg)); 1134 } 1135 #endif 1136 1137 static int 1138 sunxi_emac_phy_reset(struct sunxi_emac_softc *sc) 1139 { 1140 uint32_t delay_prop[3]; 1141 int pin_value; 1142 1143 if (sc->pin_reset == NULL) 1144 return 0; 1145 1146 if (OF_getprop(sc->phandle, "allwinner,reset-delays-us", delay_prop, 1147 sizeof(delay_prop)) <= 0) 1148 return ENXIO; 1149 1150 pin_value = of_hasprop(sc->phandle, "allwinner,reset-active-low"); 1151 1152 fdtbus_gpio_write(sc->pin_reset, pin_value); 1153 delay(htole32(delay_prop[0])); 1154 fdtbus_gpio_write(sc->pin_reset, !pin_value); 1155 delay(htole32(delay_prop[1])); 1156 fdtbus_gpio_write(sc->pin_reset, pin_value); 1157 delay(htole32(delay_prop[2])); 1158 1159 return 0; 1160 } 1161 1162 static int 1163 sunxi_emac_reset(struct sunxi_emac_softc *sc) 1164 { 1165 int retry; 1166 1167 /* Reset PHY if necessary */ 1168 if (sunxi_emac_phy_reset(sc) != 0) { 1169 aprint_error_dev(sc->dev, "failed to reset PHY\n"); 1170 return ENXIO; 1171 } 1172 1173 /* Soft reset all registers and logic */ 1174 WR4(sc, EMAC_BASIC_CTL_1, BASIC_CTL_SOFT_RST); 1175 1176 /* Wait for soft reset bit to self-clear */ 1177 for (retry = SOFT_RST_RETRY; retry > 0; retry--) { 1178 if ((RD4(sc, EMAC_BASIC_CTL_1) & BASIC_CTL_SOFT_RST) == 0) 1179 break; 1180 delay(10); 1181 } 1182 if (retry == 0) { 1183 aprint_error_dev(sc->dev, "soft reset timed out\n"); 1184 #ifdef SUNXI_EMAC_DEBUG 1185 sunxi_emac_dump_regs(sc); 1186 #endif 1187 return ETIMEDOUT; 1188 } 1189 1190 return 0; 1191 } 1192 1193 static int 1194 sunxi_emac_setup_dma(struct sunxi_emac_softc *sc) 1195 { 1196 struct mbuf *m; 1197 int error, nsegs, i; 1198 1199 /* Setup TX ring */ 1200 sc->tx.buf_tag = sc->tx.desc_tag = sc->dmat; 1201 error = bus_dmamap_create(sc->dmat, TX_DESC_SIZE, 1, TX_DESC_SIZE, 0, 1202 BUS_DMA_WAITOK, &sc->tx.desc_map); 1203 if (error) 1204 return error; 1205 error = bus_dmamem_alloc(sc->dmat, TX_DESC_SIZE, DESC_ALIGN, 0, 1206 &sc->tx.desc_dmaseg, 1, &nsegs, BUS_DMA_WAITOK); 1207 if (error) 1208 return error; 1209 error = bus_dmamem_map(sc->dmat, &sc->tx.desc_dmaseg, nsegs, 1210 TX_DESC_SIZE, (void *)&sc->tx.desc_ring, 1211 BUS_DMA_WAITOK); 1212 if (error) 1213 return error; 1214 error = bus_dmamap_load(sc->dmat, sc->tx.desc_map, sc->tx.desc_ring, 1215 TX_DESC_SIZE, NULL, BUS_DMA_WAITOK); 1216 if (error) 1217 return error; 1218 sc->tx.desc_ring_paddr = sc->tx.desc_map->dm_segs[0].ds_addr; 1219 1220 memset(sc->tx.desc_ring, 0, TX_DESC_SIZE); 1221 bus_dmamap_sync(sc->dmat, sc->tx.desc_map, 0, TX_DESC_SIZE, 1222 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1223 1224 for (i = 0; i < TX_DESC_COUNT; i++) 1225 sc->tx.desc_ring[i].next = 1226 htole32(sc->tx.desc_ring_paddr + DESC_OFF(TX_NEXT(i))); 1227 1228 sc->tx.queued = TX_DESC_COUNT; 1229 for (i = 0; i < TX_DESC_COUNT; i++) { 1230 error = bus_dmamap_create(sc->tx.buf_tag, MCLBYTES, 1231 TX_MAX_SEGS, MCLBYTES, 0, BUS_DMA_WAITOK, 1232 &sc->tx.buf_map[i].map); 1233 if (error != 0) { 1234 device_printf(sc->dev, "cannot create TX buffer map\n"); 1235 return error; 1236 } 1237 sunxi_emac_setup_txdesc(sc, i, 0, 0, 0); 1238 } 1239 1240 /* Setup RX ring */ 1241 sc->rx.buf_tag = sc->rx.desc_tag = sc->dmat; 1242 error = bus_dmamap_create(sc->dmat, RX_DESC_SIZE, 1, RX_DESC_SIZE, 0, 1243 BUS_DMA_WAITOK, &sc->rx.desc_map); 1244 if (error) 1245 return error; 1246 error = bus_dmamem_alloc(sc->dmat, RX_DESC_SIZE, DESC_ALIGN, 0, 1247 &sc->rx.desc_dmaseg, 1, &nsegs, BUS_DMA_WAITOK); 1248 if (error) 1249 return error; 1250 error = bus_dmamem_map(sc->dmat, &sc->rx.desc_dmaseg, nsegs, 1251 RX_DESC_SIZE, (void *)&sc->rx.desc_ring, 1252 BUS_DMA_WAITOK); 1253 if (error) 1254 return error; 1255 error = bus_dmamap_load(sc->dmat, sc->rx.desc_map, sc->rx.desc_ring, 1256 RX_DESC_SIZE, NULL, BUS_DMA_WAITOK); 1257 if (error) 1258 return error; 1259 sc->rx.desc_ring_paddr = sc->rx.desc_map->dm_segs[0].ds_addr; 1260 1261 memset(sc->rx.desc_ring, 0, RX_DESC_SIZE); 1262 1263 for (i = 0; i < RX_DESC_COUNT; i++) { 1264 error = bus_dmamap_create(sc->rx.buf_tag, MCLBYTES, 1265 RX_DESC_COUNT, MCLBYTES, 0, BUS_DMA_WAITOK, 1266 &sc->rx.buf_map[i].map); 1267 if (error != 0) { 1268 device_printf(sc->dev, "cannot create RX buffer map\n"); 1269 return error; 1270 } 1271 if ((m = sunxi_emac_alloc_mbufcl(sc)) == NULL) { 1272 device_printf(sc->dev, "cannot allocate RX mbuf\n"); 1273 return ENOMEM; 1274 } 1275 error = sunxi_emac_setup_rxbuf(sc, i, m); 1276 if (error != 0) { 1277 device_printf(sc->dev, "cannot create RX buffer\n"); 1278 return error; 1279 } 1280 } 1281 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map, 1282 0, sc->rx.desc_map->dm_mapsize, 1283 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1284 1285 /* Write transmit and receive descriptor base address registers */ 1286 WR4(sc, EMAC_TX_DMA_LIST, sc->tx.desc_ring_paddr); 1287 WR4(sc, EMAC_RX_DMA_LIST, sc->rx.desc_ring_paddr); 1288 1289 return 0; 1290 } 1291 1292 static int 1293 sunxi_emac_get_resources(struct sunxi_emac_softc *sc) 1294 { 1295 const int phandle = sc->phandle; 1296 bus_addr_t addr, size; 1297 1298 /* Map EMAC registers */ 1299 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) 1300 return ENXIO; 1301 if (bus_space_map(sc->bst, addr, size, 0, &sc->bsh[_RES_EMAC]) != 0) 1302 return ENXIO; 1303 1304 /* Map SYSCON registers */ 1305 if (of_hasprop(phandle, "syscon")) { 1306 const int syscon_phandle = fdtbus_get_phandle(phandle, 1307 "syscon"); 1308 if (syscon_phandle == -1) 1309 return ENXIO; 1310 if (fdtbus_get_reg(syscon_phandle, 0, &addr, &size) != 0) 1311 return ENXIO; 1312 if (size < EMAC_CLK_REG + 4) 1313 return ENXIO; 1314 addr += EMAC_CLK_REG; 1315 size -= EMAC_CLK_REG; 1316 } else { 1317 if (fdtbus_get_reg(phandle, 1, &addr, &size) != 0) 1318 return ENXIO; 1319 } 1320 if (bus_space_map(sc->bst, addr, size, 0, &sc->bsh[_RES_SYSCON]) != 0) 1321 return ENXIO; 1322 1323 /* The "ahb"/"stmmaceth" clock and reset is required */ 1324 if ((sc->clk_ahb = fdtbus_clock_get(phandle, "ahb")) == NULL && 1325 (sc->clk_ahb = fdtbus_clock_get(phandle, "stmmaceth")) == NULL) 1326 return ENXIO; 1327 if ((sc->rst_ahb = fdtbus_reset_get(phandle, "ahb")) == NULL && 1328 (sc->rst_ahb = fdtbus_reset_get(phandle, "stmmaceth")) == NULL) 1329 return ENXIO; 1330 1331 /* Internal PHY clock and reset are optional properties. */ 1332 sc->clk_ephy = fdtbus_clock_get(phandle, "ephy"); 1333 if (sc->clk_ephy == NULL) { 1334 int phy_phandle = fdtbus_get_phandle(phandle, "phy-handle"); 1335 if (phy_phandle != -1) 1336 sc->clk_ephy = fdtbus_clock_get_index(phy_phandle, 0); 1337 } 1338 sc->rst_ephy = fdtbus_reset_get(phandle, "ephy"); 1339 if (sc->rst_ephy == NULL) { 1340 int phy_phandle = fdtbus_get_phandle(phandle, "phy-handle"); 1341 if (phy_phandle != -1) 1342 sc->rst_ephy = fdtbus_reset_get_index(phy_phandle, 0); 1343 } 1344 1345 /* Regulator is optional */ 1346 sc->reg_phy = fdtbus_regulator_acquire(phandle, "phy-supply"); 1347 1348 /* Reset GPIO is optional */ 1349 sc->pin_reset = fdtbus_gpio_acquire(sc->phandle, 1350 "allwinner,reset-gpio", GPIO_PIN_OUTPUT); 1351 1352 return 0; 1353 } 1354 1355 static int 1356 sunxi_emac_get_phyid(struct sunxi_emac_softc *sc) 1357 { 1358 bus_addr_t addr; 1359 int phy_phandle; 1360 1361 phy_phandle = fdtbus_get_phandle(sc->phandle, "phy"); 1362 if (phy_phandle == -1) 1363 phy_phandle = fdtbus_get_phandle(sc->phandle, "phy-handle"); 1364 if (phy_phandle == -1) 1365 return MII_PHY_ANY; 1366 1367 if (fdtbus_get_reg(phy_phandle, 0, &addr, NULL) != 0) 1368 return MII_PHY_ANY; 1369 1370 return (int)addr; 1371 } 1372 1373 static int 1374 sunxi_emac_match(device_t parent, cfdata_t cf, void *aux) 1375 { 1376 struct fdt_attach_args * const faa = aux; 1377 1378 return of_match_compat_data(faa->faa_phandle, compat_data); 1379 } 1380 1381 static void 1382 sunxi_emac_attach(device_t parent, device_t self, void *aux) 1383 { 1384 struct fdt_attach_args * const faa = aux; 1385 struct sunxi_emac_softc * const sc = device_private(self); 1386 const int phandle = faa->faa_phandle; 1387 struct mii_data *mii = &sc->mii; 1388 struct ifnet *ifp = &sc->ec.ec_if; 1389 uint8_t eaddr[ETHER_ADDR_LEN]; 1390 char intrstr[128]; 1391 1392 sc->dev = self; 1393 sc->phandle = phandle; 1394 sc->bst = faa->faa_bst; 1395 sc->dmat = faa->faa_dmat; 1396 sc->type = of_search_compatible(phandle, compat_data)->data; 1397 sc->phy_id = sunxi_emac_get_phyid(sc); 1398 1399 if (sunxi_emac_get_resources(sc) != 0) { 1400 aprint_error(": cannot allocate resources for device\n"); 1401 return; 1402 } 1403 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 1404 aprint_error(": cannot decode interrupt\n"); 1405 return; 1406 } 1407 1408 mutex_init(&sc->mtx, MUTEX_DEFAULT, IPL_NET); 1409 callout_init(&sc->stat_ch, CALLOUT_FLAGS); 1410 callout_setfunc(&sc->stat_ch, sunxi_emac_tick, sc); 1411 1412 aprint_naive("\n"); 1413 aprint_normal(": EMAC\n"); 1414 1415 /* Setup clocks and regulators */ 1416 if (sunxi_emac_setup_resources(sc) != 0) 1417 return; 1418 1419 /* Read MAC address before resetting the chip */ 1420 sunxi_emac_get_eaddr(sc, eaddr); 1421 1422 /* Soft reset EMAC core */ 1423 if (sunxi_emac_reset(sc) != 0) 1424 return; 1425 1426 /* Setup DMA descriptors */ 1427 if (sunxi_emac_setup_dma(sc) != 0) { 1428 aprint_error_dev(self, "failed to setup DMA descriptors\n"); 1429 return; 1430 } 1431 1432 /* Install interrupt handler */ 1433 sc->ih = fdtbus_intr_establish(phandle, 0, IPL_NET, 1434 FDT_INTR_FLAGS, sunxi_emac_intr, sc); 1435 if (sc->ih == NULL) { 1436 aprint_error_dev(self, "failed to establish interrupt on %s\n", 1437 intrstr); 1438 return; 1439 } 1440 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 1441 1442 /* Setup ethernet interface */ 1443 ifp->if_softc = sc; 1444 snprintf(ifp->if_xname, IFNAMSIZ, EMAC_IFNAME, device_unit(self)); 1445 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1446 #ifdef EMAC_MPSAFE 1447 ifp->if_extflags = IFEF_MPSAFE; 1448 #endif 1449 ifp->if_start = sunxi_emac_start; 1450 ifp->if_ioctl = sunxi_emac_ioctl; 1451 ifp->if_init = sunxi_emac_init; 1452 ifp->if_stop = sunxi_emac_stop; 1453 ifp->if_capabilities = IFCAP_CSUM_IPv4_Rx | 1454 IFCAP_CSUM_IPv4_Tx | 1455 IFCAP_CSUM_TCPv4_Rx | 1456 IFCAP_CSUM_TCPv4_Tx | 1457 IFCAP_CSUM_UDPv4_Rx | 1458 IFCAP_CSUM_UDPv4_Tx; 1459 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 1460 IFQ_SET_READY(&ifp->if_snd); 1461 1462 /* 802.1Q VLAN-sized frames are supported */ 1463 sc->ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 1464 1465 /* Attach MII driver */ 1466 sc->ec.ec_mii = mii; 1467 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 1468 mii->mii_ifp = ifp; 1469 mii->mii_readreg = sunxi_emac_mii_readreg; 1470 mii->mii_writereg = sunxi_emac_mii_writereg; 1471 mii->mii_statchg = sunxi_emac_mii_statchg; 1472 mii_attach(self, mii, 0xffffffff, sc->phy_id, MII_OFFSET_ANY, 1473 MIIF_DOPAUSE); 1474 1475 if (LIST_EMPTY(&mii->mii_phys)) { 1476 aprint_error_dev(self, "no PHY found!\n"); 1477 return; 1478 } 1479 ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_AUTO); 1480 1481 /* Attach interface */ 1482 if_attach(ifp); 1483 if_deferred_start_init(ifp, NULL); 1484 1485 /* Attach ethernet interface */ 1486 ether_ifattach(ifp, eaddr); 1487 } 1488 1489 CFATTACH_DECL_NEW(sunxi_emac, sizeof(struct sunxi_emac_softc), 1490 sunxi_emac_match, sunxi_emac_attach, NULL, NULL); 1491
Indexes created Mon Oct 20 20:10:13 GMT 2025