sunxi_emac.c revision 1.2
1 /* $NetBSD: sunxi_emac.c,v 1.2 2017/07/07 21:01:58 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2016-2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Allwinner Gigabit Ethernet MAC (EMAC) controller 31 */ 32 33 #include "opt_net_mpsafe.h" 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: sunxi_emac.c,v 1.2 2017/07/07 21:01:58 jmcneill Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/bus.h> 40 #include <sys/device.h> 41 #include <sys/intr.h> 42 #include <sys/systm.h> 43 #include <sys/kernel.h> 44 #include <sys/mutex.h> 45 #include <sys/callout.h> 46 #include <sys/gpio.h> 47 #include <sys/cprng.h> 48 49 #include <net/if.h> 50 #include <net/if_dl.h> 51 #include <net/if_ether.h> 52 #include <net/if_media.h> 53 #include <net/bpf.h> 54 55 #include <dev/mii/miivar.h> 56 57 #include <dev/fdt/fdtvar.h> 58 59 #include <arm/sunxi/sunxi_emac.h> 60 61 #ifdef NET_MPSAFE 62 #define EMAC_MPSAFE 1 63 #define CALLOUT_FLAGS CALLOUT_MPSAFE 64 #define FDT_INTR_FLAGS FDT_INTR_MPSAFE 65 #else 66 #define CALLOUT_FLAGS 0 67 #define FDT_INTR_FLAGS 0 68 #endif 69 70 #define EMAC_IFNAME "emac%d" 71 72 #define ETHER_ALIGN 2 73 74 #define EMAC_LOCK(sc) mutex_enter(&(sc)->mtx) 75 #define EMAC_UNLOCK(sc) mutex_exit(&(sc)->mtx) 76 #define EMAC_ASSERT_LOCKED(sc) KASSERT(mutex_owned(&(sc)->mtx)) 77 78 #define DESC_ALIGN sizeof(struct sunxi_emac_desc) 79 #define TX_DESC_COUNT 1024 80 #define TX_DESC_SIZE (sizeof(struct sunxi_emac_desc) * TX_DESC_COUNT) 81 #define RX_DESC_COUNT 256 82 #define RX_DESC_SIZE (sizeof(struct sunxi_emac_desc) * RX_DESC_COUNT) 83 84 #define DESC_OFF(n) ((n) * sizeof(struct sunxi_emac_desc)) 85 #define TX_NEXT(n) (((n) + 1) & (TX_DESC_COUNT - 1)) 86 #define TX_SKIP(n, o) (((n) + (o)) & (TX_DESC_COUNT - 1)) 87 #define RX_NEXT(n) (((n) + 1) & (RX_DESC_COUNT - 1)) 88 89 #define TX_MAX_SEGS 128 90 91 #define SOFT_RST_RETRY 1000 92 #define MII_BUSY_RETRY 1000 93 #define MDIO_FREQ 2500000 94 95 #define BURST_LEN_DEFAULT 8 96 #define RX_TX_PRI_DEFAULT 0 97 #define PAUSE_TIME_DEFAULT 0x400 98 #define TX_INTERVAL_DEFAULT 1 99 #define RX_BATCH_DEFAULT 1 100 101 /* syscon EMAC clock register */ 102 #define EMAC_CLK_EPHY_ADDR (0x1f << 20) /* H3 */ 103 #define EMAC_CLK_EPHY_ADDR_SHIFT 20 104 #define EMAC_CLK_EPHY_LED_POL (1 << 17) /* H3 */ 105 #define EMAC_CLK_EPHY_SHUTDOWN (1 << 16) /* H3 */ 106 #define EMAC_CLK_EPHY_SELECT (1 << 15) /* H3 */ 107 #define EMAC_CLK_RMII_EN (1 << 13) 108 #define EMAC_CLK_ETXDC (0x7 << 10) 109 #define EMAC_CLK_ETXDC_SHIFT 10 110 #define EMAC_CLK_ERXDC (0x1f << 5) 111 #define EMAC_CLK_ERXDC_SHIFT 5 112 #define EMAC_CLK_PIT (0x1 << 2) 113 #define EMAC_CLK_PIT_MII (0 << 2) 114 #define EMAC_CLK_PIT_RGMII (1 << 2) 115 #define EMAC_CLK_SRC (0x3 << 0) 116 #define EMAC_CLK_SRC_MII (0 << 0) 117 #define EMAC_CLK_SRC_EXT_RGMII (1 << 0) 118 #define EMAC_CLK_SRC_RGMII (2 << 0) 119 120 /* Burst length of RX and TX DMA transfers */ 121 static int sunxi_emac_burst_len = BURST_LEN_DEFAULT; 122 123 /* RX / TX DMA priority. If 1, RX DMA has priority over TX DMA. */ 124 static int sunxi_emac_rx_tx_pri = RX_TX_PRI_DEFAULT; 125 126 /* Pause time field in the transmitted control frame */ 127 static int sunxi_emac_pause_time = PAUSE_TIME_DEFAULT; 128 129 /* Request a TX interrupt every <n> descriptors */ 130 static int sunxi_emac_tx_interval = TX_INTERVAL_DEFAULT; 131 132 /* Maximum number of mbufs to send to if_input */ 133 static int sunxi_emac_rx_batch = RX_BATCH_DEFAULT; 134 135 enum sunxi_emac_type { 136 EMAC_A83T = 1, 137 EMAC_H3, 138 }; 139 140 static const struct of_compat_data compat_data[] = { 141 { "allwinner,sun8i-a83t-emac", EMAC_A83T }, 142 { "allwinner,sun8i-h3-emac", EMAC_H3 }, 143 { NULL } 144 }; 145 146 struct sunxi_emac_bufmap { 147 bus_dmamap_t map; 148 struct mbuf *mbuf; 149 }; 150 151 struct sunxi_emac_txring { 152 bus_dma_tag_t desc_tag; 153 bus_dmamap_t desc_map; 154 bus_dma_segment_t desc_dmaseg; 155 struct sunxi_emac_desc *desc_ring; 156 bus_addr_t desc_ring_paddr; 157 bus_dma_tag_t buf_tag; 158 struct sunxi_emac_bufmap buf_map[TX_DESC_COUNT]; 159 u_int cur, next, queued; 160 }; 161 162 struct sunxi_emac_rxring { 163 bus_dma_tag_t desc_tag; 164 bus_dmamap_t desc_map; 165 bus_dma_segment_t desc_dmaseg; 166 struct sunxi_emac_desc *desc_ring; 167 bus_addr_t desc_ring_paddr; 168 bus_dma_tag_t buf_tag; 169 struct sunxi_emac_bufmap buf_map[RX_DESC_COUNT]; 170 u_int cur; 171 }; 172 173 enum { 174 _RES_EMAC, 175 _RES_SYSCON, 176 _RES_NITEMS 177 }; 178 179 struct sunxi_emac_softc { 180 device_t dev; 181 int phandle; 182 enum sunxi_emac_type type; 183 bus_space_tag_t bst; 184 bus_dma_tag_t dmat; 185 186 bus_space_handle_t bsh[_RES_NITEMS]; 187 struct clk *clk_ahb; 188 struct clk *clk_ephy; 189 struct fdtbus_reset *rst_ahb; 190 struct fdtbus_reset *rst_ephy; 191 struct fdtbus_regulator *reg_phy; 192 struct fdtbus_gpio_pin *pin_reset; 193 194 kmutex_t mtx; 195 struct ethercom ec; 196 struct mii_data mii; 197 callout_t stat_ch; 198 void *ih; 199 u_int mdc_div_ratio_m; 200 201 struct sunxi_emac_txring tx; 202 struct sunxi_emac_rxring rx; 203 }; 204 205 #define RD4(sc, reg) \ 206 bus_space_read_4((sc)->bst, (sc)->bsh[_RES_EMAC], (reg)) 207 #define WR4(sc, reg, val) \ 208 bus_space_write_4((sc)->bst, (sc)->bsh[_RES_EMAC], (reg), (val)) 209 210 #define SYSCONRD4(sc, reg) \ 211 bus_space_read_4((sc)->bst, (sc)->bsh[_RES_SYSCON], (reg)) 212 #define SYSCONWR4(sc, reg, val) \ 213 bus_space_write_4((sc)->bst, (sc)->bsh[_RES_SYSCON], (reg), (val)) 214 215 static int 216 sunxi_emac_mii_readreg(device_t dev, int phy, int reg) 217 { 218 struct sunxi_emac_softc *sc = device_private(dev); 219 int retry, val; 220 221 val = 0; 222 223 WR4(sc, EMAC_MII_CMD, 224 (sc->mdc_div_ratio_m << MDC_DIV_RATIO_M_SHIFT) | 225 (phy << PHY_ADDR_SHIFT) | 226 (reg << PHY_REG_ADDR_SHIFT) | 227 MII_BUSY); 228 for (retry = MII_BUSY_RETRY; retry > 0; retry--) { 229 if ((RD4(sc, EMAC_MII_CMD) & MII_BUSY) == 0) { 230 val = RD4(sc, EMAC_MII_DATA); 231 break; 232 } 233 delay(10); 234 } 235 236 if (retry == 0) 237 device_printf(dev, "phy read timeout, phy=%d reg=%d\n", 238 phy, reg); 239 240 return val; 241 } 242 243 static void 244 sunxi_emac_mii_writereg(device_t dev, int phy, int reg, int val) 245 { 246 struct sunxi_emac_softc *sc = device_private(dev); 247 int retry; 248 249 WR4(sc, EMAC_MII_DATA, val); 250 WR4(sc, EMAC_MII_CMD, 251 (sc->mdc_div_ratio_m << MDC_DIV_RATIO_M_SHIFT) | 252 (phy << PHY_ADDR_SHIFT) | 253 (reg << PHY_REG_ADDR_SHIFT) | 254 MII_WR | MII_BUSY); 255 for (retry = MII_BUSY_RETRY; retry > 0; retry--) { 256 if ((RD4(sc, EMAC_MII_CMD) & MII_BUSY) == 0) 257 break; 258 delay(10); 259 } 260 261 if (retry == 0) 262 device_printf(dev, "phy write timeout, phy=%d reg=%d\n", 263 phy, reg); 264 } 265 266 static void 267 sunxi_emac_update_link(struct sunxi_emac_softc *sc) 268 { 269 struct mii_data *mii = &sc->mii; 270 uint32_t val; 271 272 val = RD4(sc, EMAC_BASIC_CTL_0); 273 val &= ~(BASIC_CTL_SPEED | BASIC_CTL_DUPLEX); 274 275 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 276 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 277 val |= BASIC_CTL_SPEED_1000 << BASIC_CTL_SPEED_SHIFT; 278 else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) 279 val |= BASIC_CTL_SPEED_100 << BASIC_CTL_SPEED_SHIFT; 280 else 281 val |= BASIC_CTL_SPEED_10 << BASIC_CTL_SPEED_SHIFT; 282 283 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 284 val |= BASIC_CTL_DUPLEX; 285 286 WR4(sc, EMAC_BASIC_CTL_0, val); 287 288 val = RD4(sc, EMAC_RX_CTL_0); 289 val &= ~RX_FLOW_CTL_EN; 290 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 291 val |= RX_FLOW_CTL_EN; 292 WR4(sc, EMAC_RX_CTL_0, val); 293 294 val = RD4(sc, EMAC_TX_FLOW_CTL); 295 val &= ~(PAUSE_TIME|TX_FLOW_CTL_EN); 296 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 297 val |= TX_FLOW_CTL_EN; 298 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 299 val |= sunxi_emac_pause_time << PAUSE_TIME_SHIFT; 300 WR4(sc, EMAC_TX_FLOW_CTL, val); 301 } 302 303 static void 304 sunxi_emac_mii_statchg(struct ifnet *ifp) 305 { 306 struct sunxi_emac_softc * const sc = ifp->if_softc; 307 308 sunxi_emac_update_link(sc); 309 } 310 311 static void 312 sunxi_emac_dma_sync(struct sunxi_emac_softc *sc, bus_dma_tag_t dmat, 313 bus_dmamap_t map, int start, int end, int total, int flags) 314 { 315 if (end > start) { 316 bus_dmamap_sync(dmat, map, DESC_OFF(start), 317 DESC_OFF(end) - DESC_OFF(start), flags); 318 } else { 319 bus_dmamap_sync(dmat, map, DESC_OFF(start), 320 DESC_OFF(total) - DESC_OFF(start), flags); 321 if (DESC_OFF(end) - DESC_OFF(0) > 0) 322 bus_dmamap_sync(dmat, map, DESC_OFF(0), 323 DESC_OFF(end) - DESC_OFF(0), flags); 324 } 325 } 326 327 static void 328 sunxi_emac_setup_txdesc(struct sunxi_emac_softc *sc, int index, int flags, 329 bus_addr_t paddr, u_int len) 330 { 331 uint32_t status, size; 332 333 if (paddr == 0 || len == 0) { 334 status = 0; 335 size = 0; 336 --sc->tx.queued; 337 } else { 338 status = TX_DESC_CTL; 339 size = flags | len; 340 if ((index & (sunxi_emac_tx_interval - 1)) == 0) 341 size |= TX_INT_CTL; 342 ++sc->tx.queued; 343 } 344 345 sc->tx.desc_ring[index].addr = htole32((uint32_t)paddr); 346 sc->tx.desc_ring[index].size = htole32(size); 347 sc->tx.desc_ring[index].status = htole32(status); 348 } 349 350 static int 351 sunxi_emac_setup_txbuf(struct sunxi_emac_softc *sc, int index, struct mbuf *m) 352 { 353 bus_dma_segment_t *segs; 354 int error, nsegs, cur, i, flags; 355 u_int csum_flags; 356 357 error = bus_dmamap_load_mbuf(sc->tx.buf_tag, 358 sc->tx.buf_map[index].map, m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 359 if (error == EFBIG) { 360 device_printf(sc->dev, 361 "TX packet needs too many DMA segments, dropping...\n"); 362 m_freem(m); 363 return 0; 364 } 365 if (error != 0) 366 return 0; 367 368 segs = sc->tx.buf_map[index].map->dm_segs; 369 nsegs = sc->tx.buf_map[index].map->dm_nsegs; 370 371 flags = TX_FIR_DESC; 372 if ((m->m_pkthdr.csum_flags & M_CSUM_IPv4) != 0) { 373 if ((m->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) != 0) 374 csum_flags = TX_CHECKSUM_CTL_FULL; 375 else 376 csum_flags = TX_CHECKSUM_CTL_IP; 377 flags |= (csum_flags << TX_CHECKSUM_CTL_SHIFT); 378 } 379 380 for (cur = index, i = 0; i < nsegs; i++) { 381 sc->tx.buf_map[cur].mbuf = (i == 0 ? m : NULL); 382 if (i == nsegs - 1) 383 flags |= TX_LAST_DESC; 384 385 sunxi_emac_setup_txdesc(sc, cur, flags, segs[i].ds_addr, 386 segs[i].ds_len); 387 flags &= ~TX_FIR_DESC; 388 cur = TX_NEXT(cur); 389 } 390 391 bus_dmamap_sync(sc->tx.buf_tag, sc->tx.buf_map[index].map, 392 0, sc->tx.buf_map[index].map->dm_mapsize, BUS_DMASYNC_PREWRITE); 393 394 return nsegs; 395 } 396 397 static void 398 sunxi_emac_setup_rxdesc(struct sunxi_emac_softc *sc, int index, 399 bus_addr_t paddr) 400 { 401 uint32_t status, size; 402 403 status = RX_DESC_CTL; 404 size = MCLBYTES - 1; 405 406 sc->rx.desc_ring[index].addr = htole32((uint32_t)paddr); 407 sc->rx.desc_ring[index].size = htole32(size); 408 sc->rx.desc_ring[index].next = 409 htole32(sc->rx.desc_ring_paddr + DESC_OFF(RX_NEXT(index))); 410 sc->rx.desc_ring[index].status = htole32(status); 411 } 412 413 static int 414 sunxi_emac_setup_rxbuf(struct sunxi_emac_softc *sc, int index, struct mbuf *m) 415 { 416 int error; 417 418 m_adj(m, ETHER_ALIGN); 419 420 error = bus_dmamap_load_mbuf(sc->rx.buf_tag, 421 sc->rx.buf_map[index].map, m, BUS_DMA_READ|BUS_DMA_NOWAIT); 422 if (error != 0) 423 return error; 424 425 bus_dmamap_sync(sc->rx.buf_tag, sc->rx.buf_map[index].map, 426 0, sc->rx.buf_map[index].map->dm_mapsize, 427 BUS_DMASYNC_PREREAD); 428 429 sc->rx.buf_map[index].mbuf = m; 430 sunxi_emac_setup_rxdesc(sc, index, 431 sc->rx.buf_map[index].map->dm_segs[0].ds_addr); 432 433 return 0; 434 } 435 436 static struct mbuf * 437 sunxi_emac_alloc_mbufcl(struct sunxi_emac_softc *sc) 438 { 439 struct mbuf *m; 440 441 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 442 if (m != NULL) 443 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 444 445 return m; 446 } 447 448 static void 449 sunxi_emac_start_locked(struct sunxi_emac_softc *sc) 450 { 451 struct ifnet *ifp = &sc->ec.ec_if; 452 struct mbuf *m; 453 uint32_t val; 454 int cnt, nsegs, start; 455 456 EMAC_ASSERT_LOCKED(sc); 457 458 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 459 return; 460 461 for (cnt = 0, start = sc->tx.cur; ; cnt++) { 462 if (sc->tx.queued >= TX_DESC_COUNT - TX_MAX_SEGS) { 463 ifp->if_flags |= IFF_OACTIVE; 464 break; 465 } 466 467 IFQ_POLL(&ifp->if_snd, m); 468 if (m == NULL) 469 break; 470 471 nsegs = sunxi_emac_setup_txbuf(sc, sc->tx.cur, m); 472 if (nsegs == 0) { 473 ifp->if_flags |= IFF_OACTIVE; 474 break; 475 } 476 IFQ_DEQUEUE(&ifp->if_snd, m); 477 bpf_mtap(ifp, m); 478 479 sc->tx.cur = TX_SKIP(sc->tx.cur, nsegs); 480 } 481 482 if (cnt != 0) { 483 sunxi_emac_dma_sync(sc, sc->tx.desc_tag, sc->tx.desc_map, 484 start, sc->tx.cur, TX_DESC_COUNT, 485 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 486 487 /* Start and run TX DMA */ 488 val = RD4(sc, EMAC_TX_CTL_1); 489 WR4(sc, EMAC_TX_CTL_1, val | TX_DMA_START); 490 } 491 } 492 493 static void 494 sunxi_emac_start(struct ifnet *ifp) 495 { 496 struct sunxi_emac_softc *sc = ifp->if_softc; 497 498 EMAC_LOCK(sc); 499 sunxi_emac_start_locked(sc); 500 EMAC_UNLOCK(sc); 501 } 502 503 static void 504 sunxi_emac_tick(void *softc) 505 { 506 struct sunxi_emac_softc *sc = softc; 507 struct mii_data *mii = &sc->mii; 508 #ifndef EMAC_MPSAFE 509 int s = splnet(); 510 #endif 511 512 EMAC_LOCK(sc); 513 mii_tick(mii); 514 callout_schedule(&sc->stat_ch, hz); 515 EMAC_UNLOCK(sc); 516 517 #ifndef EMAC_MPSAFE 518 splx(s); 519 #endif 520 } 521 522 /* Bit Reversal - http://aggregate.org/MAGIC/#Bit%20Reversal */ 523 static uint32_t 524 bitrev32(uint32_t x) 525 { 526 x = (((x & 0xaaaaaaaa) >> 1) | ((x & 0x55555555) << 1)); 527 x = (((x & 0xcccccccc) >> 2) | ((x & 0x33333333) << 2)); 528 x = (((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4)); 529 x = (((x & 0xff00ff00) >> 8) | ((x & 0x00ff00ff) << 8)); 530 531 return (x >> 16) | (x << 16); 532 } 533 534 static void 535 sunxi_emac_setup_rxfilter(struct sunxi_emac_softc *sc) 536 { 537 struct ifnet *ifp = &sc->ec.ec_if; 538 uint32_t val, crc, hashreg, hashbit, hash[2], machi, maclo; 539 struct ether_multi *enm; 540 struct ether_multistep step; 541 const uint8_t *eaddr; 542 543 EMAC_ASSERT_LOCKED(sc); 544 545 val = 0; 546 hash[0] = hash[1] = 0; 547 548 if ((ifp->if_flags & IFF_PROMISC) != 0) 549 val |= DIS_ADDR_FILTER; 550 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 551 val |= RX_ALL_MULTICAST; 552 hash[0] = hash[1] = ~0; 553 } else { 554 val |= HASH_MULTICAST; 555 ETHER_FIRST_MULTI(step, &sc->ec, enm); 556 while (enm != NULL) { 557 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 558 crc &= 0x7f; 559 crc = bitrev32(~crc) >> 26; 560 hashreg = (crc >> 5); 561 hashbit = (crc & 0x1f); 562 hash[hashreg] |= (1 << hashbit); 563 ETHER_NEXT_MULTI(step, enm); 564 } 565 } 566 567 /* Write our unicast address */ 568 eaddr = CLLADDR(ifp->if_sadl); 569 machi = (eaddr[5] << 8) | eaddr[4]; 570 maclo = (eaddr[3] << 24) | (eaddr[2] << 16) | (eaddr[1] << 8) | 571 (eaddr[0] << 0); 572 WR4(sc, EMAC_ADDR_HIGH(0), machi); 573 WR4(sc, EMAC_ADDR_LOW(0), maclo); 574 575 /* Multicast hash filters */ 576 WR4(sc, EMAC_RX_HASH_0, hash[1]); 577 WR4(sc, EMAC_RX_HASH_1, hash[0]); 578 579 /* RX frame filter config */ 580 WR4(sc, EMAC_RX_FRM_FLT, val); 581 } 582 583 static void 584 sunxi_emac_enable_intr(struct sunxi_emac_softc *sc) 585 { 586 /* Enable interrupts */ 587 WR4(sc, EMAC_INT_EN, RX_INT_EN | TX_INT_EN | TX_BUF_UA_INT_EN); 588 } 589 590 static void 591 sunxi_emac_disable_intr(struct sunxi_emac_softc *sc) 592 { 593 /* Disable interrupts */ 594 WR4(sc, EMAC_INT_EN, 0); 595 } 596 597 static int 598 sunxi_emac_init_locked(struct sunxi_emac_softc *sc) 599 { 600 struct ifnet *ifp = &sc->ec.ec_if; 601 struct mii_data *mii = &sc->mii; 602 uint32_t val; 603 604 EMAC_ASSERT_LOCKED(sc); 605 606 if ((ifp->if_flags & IFF_RUNNING) != 0) 607 return 0; 608 609 sunxi_emac_setup_rxfilter(sc); 610 611 /* Configure DMA burst length and priorities */ 612 val = sunxi_emac_burst_len << BASIC_CTL_BURST_LEN_SHIFT; 613 if (sunxi_emac_rx_tx_pri) 614 val |= BASIC_CTL_RX_TX_PRI; 615 WR4(sc, EMAC_BASIC_CTL_1, val); 616 617 /* Enable interrupts */ 618 sunxi_emac_enable_intr(sc); 619 620 /* Enable transmit DMA */ 621 val = RD4(sc, EMAC_TX_CTL_1); 622 WR4(sc, EMAC_TX_CTL_1, val | TX_DMA_EN | TX_MD | TX_NEXT_FRAME); 623 624 /* Enable receive DMA */ 625 val = RD4(sc, EMAC_RX_CTL_1); 626 WR4(sc, EMAC_RX_CTL_1, val | RX_DMA_EN | RX_MD); 627 628 /* Enable transmitter */ 629 val = RD4(sc, EMAC_TX_CTL_0); 630 WR4(sc, EMAC_TX_CTL_0, val | TX_EN); 631 632 /* Enable receiver */ 633 val = RD4(sc, EMAC_RX_CTL_0); 634 WR4(sc, EMAC_RX_CTL_0, val | RX_EN | CHECK_CRC); 635 636 ifp->if_flags |= IFF_RUNNING; 637 ifp->if_flags &= ~IFF_OACTIVE; 638 639 mii_mediachg(mii); 640 callout_schedule(&sc->stat_ch, hz); 641 642 return 0; 643 } 644 645 static int 646 sunxi_emac_init(struct ifnet *ifp) 647 { 648 struct sunxi_emac_softc *sc = ifp->if_softc; 649 int error; 650 651 EMAC_LOCK(sc); 652 error = sunxi_emac_init_locked(sc); 653 EMAC_UNLOCK(sc); 654 655 return error; 656 } 657 658 static void 659 sunxi_emac_stop_locked(struct sunxi_emac_softc *sc, int disable) 660 { 661 struct ifnet *ifp = &sc->ec.ec_if; 662 uint32_t val; 663 664 EMAC_ASSERT_LOCKED(sc); 665 666 callout_stop(&sc->stat_ch); 667 668 mii_down(&sc->mii); 669 670 /* Stop transmit DMA and flush data in the TX FIFO */ 671 val = RD4(sc, EMAC_TX_CTL_1); 672 val &= ~TX_DMA_EN; 673 val |= FLUSH_TX_FIFO; 674 WR4(sc, EMAC_TX_CTL_1, val); 675 676 /* Disable transmitter */ 677 val = RD4(sc, EMAC_TX_CTL_0); 678 WR4(sc, EMAC_TX_CTL_0, val & ~TX_EN); 679 680 /* Disable receiver */ 681 val = RD4(sc, EMAC_RX_CTL_0); 682 WR4(sc, EMAC_RX_CTL_0, val & ~RX_EN); 683 684 /* Disable interrupts */ 685 sunxi_emac_disable_intr(sc); 686 687 /* Disable transmit DMA */ 688 val = RD4(sc, EMAC_TX_CTL_1); 689 WR4(sc, EMAC_TX_CTL_1, val & ~TX_DMA_EN); 690 691 /* Disable receive DMA */ 692 val = RD4(sc, EMAC_RX_CTL_1); 693 WR4(sc, EMAC_RX_CTL_1, val & ~RX_DMA_EN); 694 695 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 696 } 697 698 static void 699 sunxi_emac_stop(struct ifnet *ifp, int disable) 700 { 701 struct sunxi_emac_softc * const sc = ifp->if_softc; 702 703 EMAC_LOCK(sc); 704 sunxi_emac_stop_locked(sc, disable); 705 EMAC_UNLOCK(sc); 706 } 707 708 static int 709 sunxi_emac_rxintr(struct sunxi_emac_softc *sc) 710 { 711 struct ifnet *ifp = &sc->ec.ec_if; 712 struct mbuf *m, *m0, *mh, *mt; 713 int error, index, len, cnt, npkt; 714 uint32_t status; 715 716 mh = mt = NULL; 717 cnt = 0; 718 npkt = 0; 719 720 for (index = sc->rx.cur; ; index = RX_NEXT(index)) { 721 sunxi_emac_dma_sync(sc, sc->rx.desc_tag, sc->rx.desc_map, 722 index, index + 1, 723 RX_DESC_COUNT, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 724 725 status = le32toh(sc->rx.desc_ring[index].status); 726 if ((status & RX_DESC_CTL) != 0) 727 break; 728 729 bus_dmamap_sync(sc->rx.buf_tag, sc->rx.buf_map[index].map, 730 0, sc->rx.buf_map[index].map->dm_mapsize, 731 BUS_DMASYNC_POSTREAD); 732 bus_dmamap_unload(sc->rx.buf_tag, sc->rx.buf_map[index].map); 733 734 len = (status & RX_FRM_LEN) >> RX_FRM_LEN_SHIFT; 735 if (len != 0) { 736 m = sc->rx.buf_map[index].mbuf; 737 m_set_rcvif(m, ifp); 738 m->m_flags |= M_HASFCS; 739 m->m_pkthdr.len = len; 740 m->m_len = len; 741 742 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) != 0 && 743 (status & RX_FRM_TYPE) != 0) { 744 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 745 if ((status & RX_HEADER_ERR) != 0) 746 m->m_pkthdr.csum_flags |= 747 M_CSUM_IPv4_BAD; 748 if ((status & RX_PAYLOAD_ERR) == 0) { 749 m->m_pkthdr.csum_flags |= 750 M_CSUM_DATA; 751 m->m_pkthdr.csum_data = 0xffff; 752 } 753 } 754 755 m->m_nextpkt = NULL; 756 if (mh == NULL) 757 mh = m; 758 else 759 mt->m_nextpkt = m; 760 mt = m; 761 ++cnt; 762 ++npkt; 763 764 if (cnt == sunxi_emac_rx_batch) { 765 if_percpuq_enqueue(ifp->if_percpuq, mh); 766 mh = mt = NULL; 767 cnt = 0; 768 } 769 } 770 771 if ((m0 = sunxi_emac_alloc_mbufcl(sc)) != NULL) { 772 error = sunxi_emac_setup_rxbuf(sc, index, m0); 773 if (error != 0) { 774 /* XXX hole in RX ring */ 775 } 776 } else 777 ifp->if_ierrors++; 778 779 sunxi_emac_dma_sync(sc, sc->rx.desc_tag, sc->rx.desc_map, 780 index, index + 1, 781 RX_DESC_COUNT, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 782 } 783 784 sc->rx.cur = index; 785 786 if (mh != NULL) 787 if_percpuq_enqueue(ifp->if_percpuq, mh); 788 789 return npkt; 790 } 791 792 static void 793 sunxi_emac_txintr(struct sunxi_emac_softc *sc) 794 { 795 struct ifnet *ifp = &sc->ec.ec_if; 796 struct sunxi_emac_bufmap *bmap; 797 struct sunxi_emac_desc *desc; 798 uint32_t status; 799 int i; 800 801 EMAC_ASSERT_LOCKED(sc); 802 803 for (i = sc->tx.next; sc->tx.queued > 0; i = TX_NEXT(i)) { 804 KASSERT(sc->tx.queued > 0 && sc->tx.queued <= TX_DESC_COUNT); 805 sunxi_emac_dma_sync(sc, sc->tx.desc_tag, sc->tx.desc_map, 806 i, i + 1, TX_DESC_COUNT, 807 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 808 desc = &sc->tx.desc_ring[i]; 809 status = le32toh(desc->status); 810 if ((status & TX_DESC_CTL) != 0) 811 break; 812 bmap = &sc->tx.buf_map[i]; 813 if (bmap->mbuf != NULL) { 814 bus_dmamap_sync(sc->tx.buf_tag, bmap->map, 815 0, bmap->map->dm_mapsize, 816 BUS_DMASYNC_POSTWRITE); 817 bus_dmamap_unload(sc->tx.buf_tag, bmap->map); 818 m_freem(bmap->mbuf); 819 bmap->mbuf = NULL; 820 } 821 822 sunxi_emac_setup_txdesc(sc, i, 0, 0, 0); 823 sunxi_emac_dma_sync(sc, sc->tx.desc_tag, sc->tx.desc_map, 824 i, i + 1, TX_DESC_COUNT, 825 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 826 827 ifp->if_flags &= ~IFF_OACTIVE; 828 ifp->if_opackets++; 829 } 830 831 sc->tx.next = i; 832 } 833 834 static int 835 sunxi_emac_intr(void *arg) 836 { 837 struct sunxi_emac_softc *sc = arg; 838 struct ifnet *ifp = &sc->ec.ec_if; 839 uint32_t val; 840 841 EMAC_LOCK(sc); 842 843 val = RD4(sc, EMAC_INT_STA); 844 WR4(sc, EMAC_INT_STA, val); 845 846 if (val & RX_INT) 847 sunxi_emac_rxintr(sc); 848 849 if (val & (TX_INT|TX_BUF_UA_INT)) { 850 sunxi_emac_txintr(sc); 851 if_schedule_deferred_start(ifp); 852 } 853 854 EMAC_UNLOCK(sc); 855 856 return 1; 857 } 858 859 static int 860 sunxi_emac_ioctl(struct ifnet *ifp, u_long cmd, void *data) 861 { 862 struct sunxi_emac_softc *sc = ifp->if_softc; 863 struct mii_data *mii = &sc->mii; 864 struct ifreq *ifr = data; 865 int error, s; 866 867 #ifndef EMAC_MPSAFE 868 s = splnet(); 869 #endif 870 871 switch (cmd) { 872 case SIOCSIFMEDIA: 873 case SIOCGIFMEDIA: 874 #ifdef EMAC_MPSAFE 875 s = splnet(); 876 #endif 877 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 878 #ifdef EMAC_MPSAFE 879 splx(s); 880 #endif 881 break; 882 default: 883 #ifdef EMAC_MPSAFE 884 s = splnet(); 885 #endif 886 error = ether_ioctl(ifp, cmd, data); 887 #ifdef EMAC_MPSAFE 888 splx(s); 889 #endif 890 if (error != ENETRESET) 891 break; 892 893 error = 0; 894 895 if (cmd == SIOCSIFCAP) 896 error = (*ifp->if_init)(ifp); 897 else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 898 ; 899 else if ((ifp->if_flags & IFF_RUNNING) != 0) { 900 EMAC_LOCK(sc); 901 sunxi_emac_setup_rxfilter(sc); 902 EMAC_UNLOCK(sc); 903 } 904 break; 905 } 906 907 #ifndef EMAC_MPSAFE 908 splx(s); 909 #endif 910 911 return error; 912 } 913 914 static int 915 sunxi_emac_setup_phy(struct sunxi_emac_softc *sc) 916 { 917 uint32_t reg, tx_delay, rx_delay; 918 const char *phy_type; 919 920 phy_type = fdtbus_get_string(sc->phandle, "phy-mode"); 921 if (phy_type == NULL) 922 return 0; 923 924 aprint_debug_dev(sc->dev, "PHY type: %s\n", phy_type); 925 926 reg = SYSCONRD4(sc, 0); 927 928 reg &= ~(EMAC_CLK_PIT | EMAC_CLK_SRC | EMAC_CLK_RMII_EN); 929 if (strcmp(phy_type, "rgmii") == 0) 930 reg |= EMAC_CLK_PIT_RGMII | EMAC_CLK_SRC_RGMII; 931 else if (strcmp(phy_type, "rmii") == 0) 932 reg |= EMAC_CLK_RMII_EN; 933 else 934 reg |= EMAC_CLK_PIT_MII | EMAC_CLK_SRC_MII; 935 936 if (of_getprop_uint32(sc->phandle, "tx-delay", &tx_delay) == 0) { 937 reg &= ~EMAC_CLK_ETXDC; 938 reg |= (tx_delay << EMAC_CLK_ETXDC_SHIFT); 939 } 940 if (of_getprop_uint32(sc->phandle, "rx-delay", &rx_delay) == 0) { 941 reg &= ~EMAC_CLK_ERXDC; 942 reg |= (rx_delay << EMAC_CLK_ERXDC_SHIFT); 943 } 944 945 if (sc->type == EMAC_H3) { 946 if (of_hasprop(sc->phandle, "allwinner,use-internal-phy")) { 947 reg |= EMAC_CLK_EPHY_SELECT; 948 reg &= ~EMAC_CLK_EPHY_SHUTDOWN; 949 if (of_hasprop(sc->phandle, 950 "allwinner,leds-active-low")) 951 reg |= EMAC_CLK_EPHY_LED_POL; 952 else 953 reg &= ~EMAC_CLK_EPHY_LED_POL; 954 955 /* Set internal PHY addr to 1 */ 956 reg &= ~EMAC_CLK_EPHY_ADDR; 957 reg |= (1 << EMAC_CLK_EPHY_ADDR_SHIFT); 958 } else { 959 reg &= ~EMAC_CLK_EPHY_SELECT; 960 } 961 } 962 963 aprint_debug_dev(sc->dev, "EMAC clock: 0x%08x\n", reg); 964 965 SYSCONWR4(sc, 0, reg); 966 967 return 0; 968 } 969 970 static int 971 sunxi_emac_setup_resources(struct sunxi_emac_softc *sc) 972 { 973 u_int freq; 974 int error, div; 975 976 /* Configure PHY for MII or RGMII mode */ 977 if (sunxi_emac_setup_phy(sc) != 0) 978 return ENXIO; 979 980 /* Enable clocks */ 981 error = clk_enable(sc->clk_ahb); 982 if (error != 0) { 983 aprint_error_dev(sc->dev, "cannot enable ahb clock\n"); 984 return error; 985 } 986 987 if (sc->clk_ephy != NULL) { 988 error = clk_enable(sc->clk_ephy); 989 if (error != 0) { 990 aprint_error_dev(sc->dev, "cannot enable ephy clock\n"); 991 return error; 992 } 993 } 994 995 /* De-assert reset */ 996 error = fdtbus_reset_deassert(sc->rst_ahb); 997 if (error != 0) { 998 aprint_error_dev(sc->dev, "cannot de-assert ahb reset\n"); 999 return error; 1000 } 1001 if (sc->rst_ephy != NULL) { 1002 error = fdtbus_reset_deassert(sc->rst_ephy); 1003 if (error != 0) { 1004 aprint_error_dev(sc->dev, 1005 "cannot de-assert ephy reset\n"); 1006 return error; 1007 } 1008 } 1009 1010 /* Enable PHY regulator if applicable */ 1011 if (sc->reg_phy != NULL) { 1012 error = fdtbus_regulator_enable(sc->reg_phy); 1013 if (error != 0) { 1014 aprint_error_dev(sc->dev, 1015 "cannot enable PHY regulator\n"); 1016 return error; 1017 } 1018 } 1019 1020 /* Determine MDC clock divide ratio based on AHB clock */ 1021 freq = clk_get_rate(sc->clk_ahb); 1022 if (freq == 0) { 1023 aprint_error_dev(sc->dev, "cannot get AHB clock frequency\n"); 1024 return ENXIO; 1025 } 1026 div = freq / MDIO_FREQ; 1027 if (div <= 16) 1028 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_16; 1029 else if (div <= 32) 1030 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_32; 1031 else if (div <= 64) 1032 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_64; 1033 else if (div <= 128) 1034 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_128; 1035 else { 1036 aprint_error_dev(sc->dev, 1037 "cannot determine MDC clock divide ratio\n"); 1038 return ENXIO; 1039 } 1040 1041 aprint_debug_dev(sc->dev, "AHB frequency %u Hz, MDC div: 0x%x\n", 1042 freq, sc->mdc_div_ratio_m); 1043 1044 return 0; 1045 } 1046 1047 static void 1048 sunxi_emac_get_eaddr(struct sunxi_emac_softc *sc, uint8_t *eaddr) 1049 { 1050 uint32_t maclo, machi; 1051 #if notyet 1052 u_char rootkey[16]; 1053 #endif 1054 1055 machi = RD4(sc, EMAC_ADDR_HIGH(0)) & 0xffff; 1056 maclo = RD4(sc, EMAC_ADDR_LOW(0)); 1057 1058 if (maclo == 0xffffffff && machi == 0xffff) { 1059 #if notyet 1060 /* MAC address in hardware is invalid, create one */ 1061 if (aw_sid_get_rootkey(rootkey) == 0 && 1062 (rootkey[3] | rootkey[12] | rootkey[13] | rootkey[14] | 1063 rootkey[15]) != 0) { 1064 /* MAC address is derived from the root key in SID */ 1065 maclo = (rootkey[13] << 24) | (rootkey[12] << 16) | 1066 (rootkey[3] << 8) | 0x02; 1067 machi = (rootkey[15] << 8) | rootkey[14]; 1068 } else { 1069 #endif 1070 /* Create one */ 1071 maclo = 0x00f2 | (cprng_strong32() & 0xffff0000); 1072 machi = cprng_strong32() & 0xffff; 1073 #if notyet 1074 } 1075 #endif 1076 } 1077 1078 eaddr[0] = maclo & 0xff; 1079 eaddr[1] = (maclo >> 8) & 0xff; 1080 eaddr[2] = (maclo >> 16) & 0xff; 1081 eaddr[3] = (maclo >> 24) & 0xff; 1082 eaddr[4] = machi & 0xff; 1083 eaddr[5] = (machi >> 8) & 0xff; 1084 } 1085 1086 #ifdef SUNXI_EMAC_DEBUG 1087 static void 1088 sunxi_emac_dump_regs(struct sunxi_emac_softc *sc) 1089 { 1090 static const struct { 1091 const char *name; 1092 u_int reg; 1093 } regs[] = { 1094 { "BASIC_CTL_0", EMAC_BASIC_CTL_0 }, 1095 { "BASIC_CTL_1", EMAC_BASIC_CTL_1 }, 1096 { "INT_STA", EMAC_INT_STA }, 1097 { "INT_EN", EMAC_INT_EN }, 1098 { "TX_CTL_0", EMAC_TX_CTL_0 }, 1099 { "TX_CTL_1", EMAC_TX_CTL_1 }, 1100 { "TX_FLOW_CTL", EMAC_TX_FLOW_CTL }, 1101 { "TX_DMA_LIST", EMAC_TX_DMA_LIST }, 1102 { "RX_CTL_0", EMAC_RX_CTL_0 }, 1103 { "RX_CTL_1", EMAC_RX_CTL_1 }, 1104 { "RX_DMA_LIST", EMAC_RX_DMA_LIST }, 1105 { "RX_FRM_FLT", EMAC_RX_FRM_FLT }, 1106 { "RX_HASH_0", EMAC_RX_HASH_0 }, 1107 { "RX_HASH_1", EMAC_RX_HASH_1 }, 1108 { "MII_CMD", EMAC_MII_CMD }, 1109 { "ADDR_HIGH0", EMAC_ADDR_HIGH(0) }, 1110 { "ADDR_LOW0", EMAC_ADDR_LOW(0) }, 1111 { "TX_DMA_STA", EMAC_TX_DMA_STA }, 1112 { "TX_DMA_CUR_DESC", EMAC_TX_DMA_CUR_DESC }, 1113 { "TX_DMA_CUR_BUF", EMAC_TX_DMA_CUR_BUF }, 1114 { "RX_DMA_STA", EMAC_RX_DMA_STA }, 1115 { "RX_DMA_CUR_DESC", EMAC_RX_DMA_CUR_DESC }, 1116 { "RX_DMA_CUR_BUF", EMAC_RX_DMA_CUR_BUF }, 1117 { "RGMII_STA", EMAC_RGMII_STA }, 1118 }; 1119 u_int n; 1120 1121 for (n = 0; n < __arraycount(regs); n++) 1122 device_printf(dev, " %-20s %08x\n", regs[n].name, 1123 RD4(sc, regs[n].reg)); 1124 } 1125 #endif 1126 1127 static int 1128 sunxi_emac_phy_reset(struct sunxi_emac_softc *sc) 1129 { 1130 uint32_t delay_prop[3]; 1131 int pin_value; 1132 1133 if (sc->pin_reset == NULL) 1134 return 0; 1135 1136 if (OF_getprop(sc->phandle, "allwinner,reset-delays-us", delay_prop, 1137 sizeof(delay_prop)) <= 0) 1138 return ENXIO; 1139 1140 pin_value = of_hasprop(sc->phandle, "allwinner,reset-active-low"); 1141 1142 fdtbus_gpio_write(sc->pin_reset, pin_value); 1143 delay(htole32(delay_prop[0])); 1144 fdtbus_gpio_write(sc->pin_reset, !pin_value); 1145 delay(htole32(delay_prop[1])); 1146 fdtbus_gpio_write(sc->pin_reset, pin_value); 1147 delay(htole32(delay_prop[2])); 1148 1149 return 0; 1150 } 1151 1152 static int 1153 sunxi_emac_reset(struct sunxi_emac_softc *sc) 1154 { 1155 int retry; 1156 1157 /* Reset PHY if necessary */ 1158 if (sunxi_emac_phy_reset(sc) != 0) { 1159 aprint_error_dev(sc->dev, "failed to reset PHY\n"); 1160 return ENXIO; 1161 } 1162 1163 /* Soft reset all registers and logic */ 1164 WR4(sc, EMAC_BASIC_CTL_1, BASIC_CTL_SOFT_RST); 1165 1166 /* Wait for soft reset bit to self-clear */ 1167 for (retry = SOFT_RST_RETRY; retry > 0; retry--) { 1168 if ((RD4(sc, EMAC_BASIC_CTL_1) & BASIC_CTL_SOFT_RST) == 0) 1169 break; 1170 delay(10); 1171 } 1172 if (retry == 0) { 1173 aprint_error_dev(sc->dev, "soft reset timed out\n"); 1174 #ifdef SUNXI_EMAC_DEBUG 1175 sunxi_emac_dump_regs(sc); 1176 #endif 1177 return ETIMEDOUT; 1178 } 1179 1180 return 0; 1181 } 1182 1183 static int 1184 sunxi_emac_setup_dma(struct sunxi_emac_softc *sc) 1185 { 1186 struct mbuf *m; 1187 int error, nsegs, i; 1188 1189 /* Setup TX ring */ 1190 sc->tx.buf_tag = sc->tx.desc_tag = sc->dmat; 1191 error = bus_dmamap_create(sc->dmat, TX_DESC_SIZE, 1, TX_DESC_SIZE, 0, 1192 BUS_DMA_WAITOK, &sc->tx.desc_map); 1193 if (error) 1194 return error; 1195 error = bus_dmamem_alloc(sc->dmat, TX_DESC_SIZE, DESC_ALIGN, 0, 1196 &sc->tx.desc_dmaseg, 1, &nsegs, BUS_DMA_WAITOK); 1197 if (error) 1198 return error; 1199 error = bus_dmamem_map(sc->dmat, &sc->tx.desc_dmaseg, nsegs, 1200 TX_DESC_SIZE, (void *)&sc->tx.desc_ring, 1201 BUS_DMA_WAITOK); 1202 if (error) 1203 return error; 1204 error = bus_dmamap_load(sc->dmat, sc->tx.desc_map, sc->tx.desc_ring, 1205 TX_DESC_SIZE, NULL, BUS_DMA_WAITOK); 1206 if (error) 1207 return error; 1208 sc->tx.desc_ring_paddr = sc->tx.desc_map->dm_segs[0].ds_addr; 1209 1210 memset(sc->tx.desc_ring, 0, TX_DESC_SIZE); 1211 bus_dmamap_sync(sc->dmat, sc->tx.desc_map, 0, TX_DESC_SIZE, 1212 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1213 1214 for (i = 0; i < TX_DESC_COUNT; i++) 1215 sc->tx.desc_ring[i].next = 1216 htole32(sc->tx.desc_ring_paddr + DESC_OFF(TX_NEXT(i))); 1217 1218 sc->tx.queued = TX_DESC_COUNT; 1219 for (i = 0; i < TX_DESC_COUNT; i++) { 1220 error = bus_dmamap_create(sc->tx.buf_tag, MCLBYTES, 1221 TX_MAX_SEGS, MCLBYTES, 0, BUS_DMA_WAITOK, 1222 &sc->tx.buf_map[i].map); 1223 if (error != 0) { 1224 device_printf(sc->dev, "cannot create TX buffer map\n"); 1225 return error; 1226 } 1227 sunxi_emac_setup_txdesc(sc, i, 0, 0, 0); 1228 } 1229 1230 /* Setup RX ring */ 1231 sc->rx.buf_tag = sc->rx.desc_tag = sc->dmat; 1232 error = bus_dmamap_create(sc->dmat, RX_DESC_SIZE, 1, RX_DESC_SIZE, 0, 1233 BUS_DMA_WAITOK, &sc->rx.desc_map); 1234 if (error) 1235 return error; 1236 error = bus_dmamem_alloc(sc->dmat, RX_DESC_SIZE, DESC_ALIGN, 0, 1237 &sc->rx.desc_dmaseg, 1, &nsegs, BUS_DMA_WAITOK); 1238 if (error) 1239 return error; 1240 error = bus_dmamem_map(sc->dmat, &sc->rx.desc_dmaseg, nsegs, 1241 RX_DESC_SIZE, (void *)&sc->rx.desc_ring, 1242 BUS_DMA_WAITOK); 1243 if (error) 1244 return error; 1245 error = bus_dmamap_load(sc->dmat, sc->rx.desc_map, sc->rx.desc_ring, 1246 RX_DESC_SIZE, NULL, BUS_DMA_WAITOK); 1247 if (error) 1248 return error; 1249 sc->rx.desc_ring_paddr = sc->rx.desc_map->dm_segs[0].ds_addr; 1250 1251 memset(sc->rx.desc_ring, 0, RX_DESC_SIZE); 1252 1253 for (i = 0; i < RX_DESC_COUNT; i++) { 1254 error = bus_dmamap_create(sc->rx.buf_tag, MCLBYTES, 1255 RX_DESC_COUNT, MCLBYTES, 0, BUS_DMA_WAITOK, 1256 &sc->rx.buf_map[i].map); 1257 if (error != 0) { 1258 device_printf(sc->dev, "cannot create RX buffer map\n"); 1259 return error; 1260 } 1261 if ((m = sunxi_emac_alloc_mbufcl(sc)) == NULL) { 1262 device_printf(sc->dev, "cannot allocate RX mbuf\n"); 1263 return ENOMEM; 1264 } 1265 error = sunxi_emac_setup_rxbuf(sc, i, m); 1266 if (error != 0) { 1267 device_printf(sc->dev, "cannot create RX buffer\n"); 1268 return error; 1269 } 1270 } 1271 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map, 1272 0, sc->rx.desc_map->dm_mapsize, 1273 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1274 1275 /* Write transmit and receive descriptor base address registers */ 1276 WR4(sc, EMAC_TX_DMA_LIST, sc->tx.desc_ring_paddr); 1277 WR4(sc, EMAC_RX_DMA_LIST, sc->rx.desc_ring_paddr); 1278 1279 return 0; 1280 } 1281 1282 static int 1283 sunxi_emac_get_resources(struct sunxi_emac_softc *sc) 1284 { 1285 const int phandle = sc->phandle; 1286 bus_addr_t addr, size; 1287 u_int n; 1288 1289 /* Map registers */ 1290 for (n = 0; n < _RES_NITEMS; n++) { 1291 if (fdtbus_get_reg(phandle, n, &addr, &size) != 0) 1292 return ENXIO; 1293 if (bus_space_map(sc->bst, addr, size, 0, &sc->bsh[n]) != 0) 1294 return ENXIO; 1295 } 1296 1297 /* Get clocks and resets. "ahb" is required, "ephy" is optional. */ 1298 1299 if ((sc->clk_ahb = fdtbus_clock_get(phandle, "ahb")) == NULL) 1300 return ENXIO; 1301 sc->clk_ephy = fdtbus_clock_get(phandle, "ephy"); 1302 1303 if ((sc->rst_ahb = fdtbus_reset_get(phandle, "ahb")) == NULL) 1304 return ENXIO; 1305 sc->rst_ahb = fdtbus_reset_get(phandle, "ephy"); 1306 1307 /* Regulator is optional */ 1308 sc->reg_phy = fdtbus_regulator_acquire(phandle, "phy-supply"); 1309 1310 /* Reset GPIO is optional */ 1311 sc->pin_reset = fdtbus_gpio_acquire(sc->phandle, 1312 "allwinner,reset-gpio", GPIO_PIN_OUTPUT); 1313 1314 return 0; 1315 } 1316 1317 static int 1318 sunxi_emac_match(device_t parent, cfdata_t cf, void *aux) 1319 { 1320 struct fdt_attach_args * const faa = aux; 1321 1322 return of_match_compat_data(faa->faa_phandle, compat_data); 1323 } 1324 1325 static void 1326 sunxi_emac_attach(device_t parent, device_t self, void *aux) 1327 { 1328 struct fdt_attach_args * const faa = aux; 1329 struct sunxi_emac_softc * const sc = device_private(self); 1330 const int phandle = faa->faa_phandle; 1331 struct mii_data *mii = &sc->mii; 1332 struct ifnet *ifp = &sc->ec.ec_if; 1333 uint8_t eaddr[ETHER_ADDR_LEN]; 1334 char intrstr[128]; 1335 1336 sc->dev = self; 1337 sc->phandle = phandle; 1338 sc->bst = faa->faa_bst; 1339 sc->dmat = faa->faa_dmat; 1340 sc->type = of_search_compatible(phandle, compat_data)->data; 1341 1342 if (sunxi_emac_get_resources(sc) != 0) { 1343 aprint_error(": cannot allocate resources for device\n"); 1344 return; 1345 } 1346 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 1347 aprint_error(": cannot decode interrupt\n"); 1348 return; 1349 } 1350 1351 mutex_init(&sc->mtx, MUTEX_DEFAULT, IPL_NET); 1352 callout_init(&sc->stat_ch, CALLOUT_FLAGS); 1353 callout_setfunc(&sc->stat_ch, sunxi_emac_tick, sc); 1354 1355 aprint_naive("\n"); 1356 aprint_normal(": EMAC\n"); 1357 1358 /* Setup clocks and regulators */ 1359 if (sunxi_emac_setup_resources(sc) != 0) 1360 return; 1361 1362 /* Read MAC address before resetting the chip */ 1363 sunxi_emac_get_eaddr(sc, eaddr); 1364 1365 /* Soft reset EMAC core */ 1366 if (sunxi_emac_reset(sc) != 0) 1367 return; 1368 1369 /* Setup DMA descriptors */ 1370 if (sunxi_emac_setup_dma(sc) != 0) { 1371 aprint_error_dev(self, "failed to setup DMA descriptors\n"); 1372 return; 1373 } 1374 1375 /* Install interrupt handler */ 1376 sc->ih = fdtbus_intr_establish(phandle, 0, IPL_NET, 1377 FDT_INTR_FLAGS, sunxi_emac_intr, sc); 1378 if (sc->ih == NULL) { 1379 aprint_error_dev(self, "failed to establish interrupt on %s\n", 1380 intrstr); 1381 return; 1382 } 1383 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 1384 1385 /* Setup ethernet interface */ 1386 ifp->if_softc = sc; 1387 snprintf(ifp->if_xname, IFNAMSIZ, EMAC_IFNAME, device_unit(self)); 1388 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1389 #ifdef EMAC_MPSAFE 1390 ifp->if_extflags = IFEF_START_MPSAFE; 1391 #endif 1392 ifp->if_start = sunxi_emac_start; 1393 ifp->if_ioctl = sunxi_emac_ioctl; 1394 ifp->if_init = sunxi_emac_init; 1395 ifp->if_stop = sunxi_emac_stop; 1396 ifp->if_capabilities = IFCAP_CSUM_IPv4_Rx | 1397 IFCAP_CSUM_IPv4_Tx | 1398 IFCAP_CSUM_TCPv4_Rx | 1399 IFCAP_CSUM_TCPv4_Tx | 1400 IFCAP_CSUM_UDPv4_Rx | 1401 IFCAP_CSUM_UDPv4_Tx; 1402 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 1403 IFQ_SET_READY(&ifp->if_snd); 1404 1405 /* 802.1Q VLAN-sized frames are supported */ 1406 sc->ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 1407 1408 /* Attach MII driver */ 1409 sc->ec.ec_mii = mii; 1410 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 1411 mii->mii_ifp = ifp; 1412 mii->mii_readreg = sunxi_emac_mii_readreg; 1413 mii->mii_writereg = sunxi_emac_mii_writereg; 1414 mii->mii_statchg = sunxi_emac_mii_statchg; 1415 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 1416 MIIF_DOPAUSE); 1417 1418 if (LIST_EMPTY(&mii->mii_phys)) { 1419 aprint_error_dev(self, "no PHY found!\n"); 1420 return; 1421 } 1422 ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_AUTO); 1423 1424 /* Attach interface */ 1425 if_attach(ifp); 1426 if_deferred_start_init(ifp, NULL); 1427 1428 /* Attach ethernet interface */ 1429 ether_ifattach(ifp, eaddr); 1430 } 1431 1432 CFATTACH_DECL_NEW(sunxi_emac, sizeof(struct sunxi_emac_softc), 1433 sunxi_emac_match, sunxi_emac_attach, NULL, NULL); 1434
Indexes created Tue Oct 21 16:10:11 GMT 2025