sunxi_emac.c revision 1.22
1 /* $NetBSD: sunxi_emac.c,v 1.22 2019/03/04 11:35:38 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2016-2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Allwinner Gigabit Ethernet MAC (EMAC) controller 31 */ 32 33 #include "opt_net_mpsafe.h" 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: sunxi_emac.c,v 1.22 2019/03/04 11:35:38 jmcneill Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/bus.h> 40 #include <sys/device.h> 41 #include <sys/intr.h> 42 #include <sys/systm.h> 43 #include <sys/kernel.h> 44 #include <sys/mutex.h> 45 #include <sys/callout.h> 46 #include <sys/gpio.h> 47 #include <sys/cprng.h> 48 49 #include <net/if.h> 50 #include <net/if_dl.h> 51 #include <net/if_ether.h> 52 #include <net/if_media.h> 53 #include <net/bpf.h> 54 55 #include <dev/mii/miivar.h> 56 57 #include <dev/fdt/fdtvar.h> 58 #include <dev/fdt/syscon.h> 59 60 #include <arm/sunxi/sunxi_emac.h> 61 62 #ifdef NET_MPSAFE 63 #define EMAC_MPSAFE 1 64 #define CALLOUT_FLAGS CALLOUT_MPSAFE 65 #define FDT_INTR_FLAGS FDT_INTR_MPSAFE 66 #else 67 #define CALLOUT_FLAGS 0 68 #define FDT_INTR_FLAGS 0 69 #endif 70 71 #define EMAC_IFNAME "emac%d" 72 73 #define ETHER_ALIGN 2 74 75 #define EMAC_LOCK(sc) mutex_enter(&(sc)->mtx) 76 #define EMAC_UNLOCK(sc) mutex_exit(&(sc)->mtx) 77 #define EMAC_ASSERT_LOCKED(sc) KASSERT(mutex_owned(&(sc)->mtx)) 78 79 #define DESC_ALIGN sizeof(struct sunxi_emac_desc) 80 #define TX_DESC_COUNT 1024 81 #define TX_DESC_SIZE (sizeof(struct sunxi_emac_desc) * TX_DESC_COUNT) 82 #define RX_DESC_COUNT 256 83 #define RX_DESC_SIZE (sizeof(struct sunxi_emac_desc) * RX_DESC_COUNT) 84 85 #define DESC_OFF(n) ((n) * sizeof(struct sunxi_emac_desc)) 86 #define TX_NEXT(n) (((n) + 1) & (TX_DESC_COUNT - 1)) 87 #define TX_SKIP(n, o) (((n) + (o)) & (TX_DESC_COUNT - 1)) 88 #define RX_NEXT(n) (((n) + 1) & (RX_DESC_COUNT - 1)) 89 90 #define TX_MAX_SEGS 128 91 92 #define SOFT_RST_RETRY 1000 93 #define MII_BUSY_RETRY 1000 94 #define MDIO_FREQ 2500000 95 96 #define BURST_LEN_DEFAULT 8 97 #define RX_TX_PRI_DEFAULT 0 98 #define PAUSE_TIME_DEFAULT 0x400 99 100 /* syscon EMAC clock register */ 101 #define EMAC_CLK_REG 0x30 102 #define EMAC_CLK_EPHY_ADDR (0x1f << 20) /* H3 */ 103 #define EMAC_CLK_EPHY_ADDR_SHIFT 20 104 #define EMAC_CLK_EPHY_LED_POL (1 << 17) /* H3 */ 105 #define EMAC_CLK_EPHY_SHUTDOWN (1 << 16) /* H3 */ 106 #define EMAC_CLK_EPHY_SELECT (1 << 15) /* H3 */ 107 #define EMAC_CLK_RMII_EN (1 << 13) 108 #define EMAC_CLK_ETXDC (0x7 << 10) 109 #define EMAC_CLK_ETXDC_SHIFT 10 110 #define EMAC_CLK_ERXDC (0x1f << 5) 111 #define EMAC_CLK_ERXDC_SHIFT 5 112 #define EMAC_CLK_PIT (0x1 << 2) 113 #define EMAC_CLK_PIT_MII (0 << 2) 114 #define EMAC_CLK_PIT_RGMII (1 << 2) 115 #define EMAC_CLK_SRC (0x3 << 0) 116 #define EMAC_CLK_SRC_MII (0 << 0) 117 #define EMAC_CLK_SRC_EXT_RGMII (1 << 0) 118 #define EMAC_CLK_SRC_RGMII (2 << 0) 119 120 /* Burst length of RX and TX DMA transfers */ 121 static int sunxi_emac_burst_len = BURST_LEN_DEFAULT; 122 123 /* RX / TX DMA priority. If 1, RX DMA has priority over TX DMA. */ 124 static int sunxi_emac_rx_tx_pri = RX_TX_PRI_DEFAULT; 125 126 /* Pause time field in the transmitted control frame */ 127 static int sunxi_emac_pause_time = PAUSE_TIME_DEFAULT; 128 129 enum sunxi_emac_type { 130 EMAC_A64 = 1, 131 EMAC_A83T, 132 EMAC_H3, 133 EMAC_H6, 134 }; 135 136 static const struct of_compat_data compat_data[] = { 137 { "allwinner,sun8i-a83t-emac", EMAC_A83T }, 138 { "allwinner,sun8i-h3-emac", EMAC_H3 }, 139 { "allwinner,sun50i-a64-emac", EMAC_A64 }, 140 { "allwinner,sun50i-h6-emac", EMAC_H6 }, 141 { NULL } 142 }; 143 144 struct sunxi_emac_bufmap { 145 bus_dmamap_t map; 146 struct mbuf *mbuf; 147 }; 148 149 struct sunxi_emac_txring { 150 bus_dma_tag_t desc_tag; 151 bus_dmamap_t desc_map; 152 bus_dma_segment_t desc_dmaseg; 153 struct sunxi_emac_desc *desc_ring; 154 bus_addr_t desc_ring_paddr; 155 bus_dma_tag_t buf_tag; 156 struct sunxi_emac_bufmap buf_map[TX_DESC_COUNT]; 157 u_int cur, next, queued; 158 }; 159 160 struct sunxi_emac_rxring { 161 bus_dma_tag_t desc_tag; 162 bus_dmamap_t desc_map; 163 bus_dma_segment_t desc_dmaseg; 164 struct sunxi_emac_desc *desc_ring; 165 bus_addr_t desc_ring_paddr; 166 bus_dma_tag_t buf_tag; 167 struct sunxi_emac_bufmap buf_map[RX_DESC_COUNT]; 168 u_int cur; 169 }; 170 171 struct sunxi_emac_softc { 172 device_t dev; 173 int phandle; 174 enum sunxi_emac_type type; 175 bus_space_tag_t bst; 176 bus_dma_tag_t dmat; 177 178 bus_space_handle_t bsh; 179 struct clk *clk_ahb; 180 struct clk *clk_ephy; 181 struct fdtbus_reset *rst_ahb; 182 struct fdtbus_reset *rst_ephy; 183 struct fdtbus_regulator *reg_phy; 184 struct fdtbus_gpio_pin *pin_reset; 185 186 struct syscon *syscon; 187 188 int phy_id; 189 190 kmutex_t mtx; 191 struct ethercom ec; 192 struct mii_data mii; 193 callout_t stat_ch; 194 void *ih; 195 u_int mdc_div_ratio_m; 196 197 struct sunxi_emac_txring tx; 198 struct sunxi_emac_rxring rx; 199 }; 200 201 #define RD4(sc, reg) \ 202 bus_space_read_4((sc)->bst, (sc)->bsh, (reg)) 203 #define WR4(sc, reg, val) \ 204 bus_space_write_4((sc)->bst, (sc)->bsh, (reg), (val)) 205 206 static int 207 sunxi_emac_mii_readreg(device_t dev, int phy, int reg, uint16_t *val) 208 { 209 struct sunxi_emac_softc *sc = device_private(dev); 210 int retry; 211 212 WR4(sc, EMAC_MII_CMD, 213 (sc->mdc_div_ratio_m << MDC_DIV_RATIO_M_SHIFT) | 214 (phy << PHY_ADDR_SHIFT) | 215 (reg << PHY_REG_ADDR_SHIFT) | 216 MII_BUSY); 217 for (retry = MII_BUSY_RETRY; retry > 0; retry--) { 218 if ((RD4(sc, EMAC_MII_CMD) & MII_BUSY) == 0) { 219 *val = RD4(sc, EMAC_MII_DATA) & 0xffff; 220 break; 221 } 222 delay(10); 223 } 224 225 if (retry == 0) { 226 device_printf(dev, "phy read timeout, phy=%d reg=%d\n", 227 phy, reg); 228 return ETIMEDOUT; 229 } 230 231 return 0; 232 } 233 234 static int 235 sunxi_emac_mii_writereg(device_t dev, int phy, int reg, uint16_t val) 236 { 237 struct sunxi_emac_softc *sc = device_private(dev); 238 int retry; 239 240 WR4(sc, EMAC_MII_DATA, val); 241 WR4(sc, EMAC_MII_CMD, 242 (sc->mdc_div_ratio_m << MDC_DIV_RATIO_M_SHIFT) | 243 (phy << PHY_ADDR_SHIFT) | 244 (reg << PHY_REG_ADDR_SHIFT) | 245 MII_WR | MII_BUSY); 246 for (retry = MII_BUSY_RETRY; retry > 0; retry--) { 247 if ((RD4(sc, EMAC_MII_CMD) & MII_BUSY) == 0) 248 break; 249 delay(10); 250 } 251 252 if (retry == 0) { 253 device_printf(dev, "phy write timeout, phy=%d reg=%d\n", 254 phy, reg); 255 return ETIMEDOUT; 256 } 257 258 return 0; 259 } 260 261 static void 262 sunxi_emac_update_link(struct sunxi_emac_softc *sc) 263 { 264 struct mii_data *mii = &sc->mii; 265 uint32_t val; 266 267 val = RD4(sc, EMAC_BASIC_CTL_0); 268 val &= ~(BASIC_CTL_SPEED | BASIC_CTL_DUPLEX); 269 270 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 271 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 272 val |= BASIC_CTL_SPEED_1000 << BASIC_CTL_SPEED_SHIFT; 273 else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) 274 val |= BASIC_CTL_SPEED_100 << BASIC_CTL_SPEED_SHIFT; 275 else 276 val |= BASIC_CTL_SPEED_10 << BASIC_CTL_SPEED_SHIFT; 277 278 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 279 val |= BASIC_CTL_DUPLEX; 280 281 WR4(sc, EMAC_BASIC_CTL_0, val); 282 283 val = RD4(sc, EMAC_RX_CTL_0); 284 val &= ~RX_FLOW_CTL_EN; 285 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 286 val |= RX_FLOW_CTL_EN; 287 WR4(sc, EMAC_RX_CTL_0, val); 288 289 val = RD4(sc, EMAC_TX_FLOW_CTL); 290 val &= ~(PAUSE_TIME|TX_FLOW_CTL_EN); 291 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 292 val |= TX_FLOW_CTL_EN; 293 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 294 val |= sunxi_emac_pause_time << PAUSE_TIME_SHIFT; 295 WR4(sc, EMAC_TX_FLOW_CTL, val); 296 } 297 298 static void 299 sunxi_emac_mii_statchg(struct ifnet *ifp) 300 { 301 struct sunxi_emac_softc * const sc = ifp->if_softc; 302 303 sunxi_emac_update_link(sc); 304 } 305 306 static void 307 sunxi_emac_dma_sync(struct sunxi_emac_softc *sc, bus_dma_tag_t dmat, 308 bus_dmamap_t map, int start, int end, int total, int flags) 309 { 310 if (end > start) { 311 bus_dmamap_sync(dmat, map, DESC_OFF(start), 312 DESC_OFF(end) - DESC_OFF(start), flags); 313 } else { 314 bus_dmamap_sync(dmat, map, DESC_OFF(start), 315 DESC_OFF(total) - DESC_OFF(start), flags); 316 if (DESC_OFF(end) - DESC_OFF(0) > 0) 317 bus_dmamap_sync(dmat, map, DESC_OFF(0), 318 DESC_OFF(end) - DESC_OFF(0), flags); 319 } 320 } 321 322 static void 323 sunxi_emac_setup_txdesc(struct sunxi_emac_softc *sc, int index, int flags, 324 bus_addr_t paddr, u_int len) 325 { 326 uint32_t status, size; 327 328 if (paddr == 0 || len == 0) { 329 status = 0; 330 size = 0; 331 --sc->tx.queued; 332 } else { 333 status = TX_DESC_CTL; 334 size = flags | len; 335 ++sc->tx.queued; 336 } 337 338 sc->tx.desc_ring[index].addr = htole32((uint32_t)paddr); 339 sc->tx.desc_ring[index].size = htole32(size); 340 sc->tx.desc_ring[index].status = htole32(status); 341 } 342 343 static int 344 sunxi_emac_setup_txbuf(struct sunxi_emac_softc *sc, int index, struct mbuf *m) 345 { 346 bus_dma_segment_t *segs; 347 int error, nsegs, cur, i, flags; 348 u_int csum_flags; 349 350 error = bus_dmamap_load_mbuf(sc->tx.buf_tag, 351 sc->tx.buf_map[index].map, m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 352 if (error == EFBIG) { 353 device_printf(sc->dev, 354 "TX packet needs too many DMA segments, dropping...\n"); 355 m_freem(m); 356 return 0; 357 } 358 if (error != 0) 359 return 0; 360 361 segs = sc->tx.buf_map[index].map->dm_segs; 362 nsegs = sc->tx.buf_map[index].map->dm_nsegs; 363 364 flags = TX_FIR_DESC; 365 if ((m->m_pkthdr.csum_flags & M_CSUM_IPv4) != 0) { 366 if ((m->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) != 0) 367 csum_flags = TX_CHECKSUM_CTL_FULL; 368 else 369 csum_flags = TX_CHECKSUM_CTL_IP; 370 flags |= (csum_flags << TX_CHECKSUM_CTL_SHIFT); 371 } 372 373 for (cur = index, i = 0; i < nsegs; i++) { 374 sc->tx.buf_map[cur].mbuf = (i == 0 ? m : NULL); 375 if (i == nsegs - 1) 376 flags |= TX_LAST_DESC | TX_INT_CTL; 377 378 sunxi_emac_setup_txdesc(sc, cur, flags, segs[i].ds_addr, 379 segs[i].ds_len); 380 flags &= ~TX_FIR_DESC; 381 cur = TX_NEXT(cur); 382 } 383 384 bus_dmamap_sync(sc->tx.buf_tag, sc->tx.buf_map[index].map, 385 0, sc->tx.buf_map[index].map->dm_mapsize, BUS_DMASYNC_PREWRITE); 386 387 return nsegs; 388 } 389 390 static void 391 sunxi_emac_setup_rxdesc(struct sunxi_emac_softc *sc, int index, 392 bus_addr_t paddr) 393 { 394 uint32_t status, size; 395 396 status = RX_DESC_CTL; 397 size = MCLBYTES - 1; 398 399 sc->rx.desc_ring[index].addr = htole32((uint32_t)paddr); 400 sc->rx.desc_ring[index].size = htole32(size); 401 sc->rx.desc_ring[index].next = 402 htole32(sc->rx.desc_ring_paddr + DESC_OFF(RX_NEXT(index))); 403 sc->rx.desc_ring[index].status = htole32(status); 404 } 405 406 static int 407 sunxi_emac_setup_rxbuf(struct sunxi_emac_softc *sc, int index, struct mbuf *m) 408 { 409 int error; 410 411 m_adj(m, ETHER_ALIGN); 412 413 error = bus_dmamap_load_mbuf(sc->rx.buf_tag, 414 sc->rx.buf_map[index].map, m, BUS_DMA_READ|BUS_DMA_NOWAIT); 415 if (error != 0) 416 return error; 417 418 bus_dmamap_sync(sc->rx.buf_tag, sc->rx.buf_map[index].map, 419 0, sc->rx.buf_map[index].map->dm_mapsize, 420 BUS_DMASYNC_PREREAD); 421 422 sc->rx.buf_map[index].mbuf = m; 423 sunxi_emac_setup_rxdesc(sc, index, 424 sc->rx.buf_map[index].map->dm_segs[0].ds_addr); 425 426 return 0; 427 } 428 429 static struct mbuf * 430 sunxi_emac_alloc_mbufcl(struct sunxi_emac_softc *sc) 431 { 432 struct mbuf *m; 433 434 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 435 if (m != NULL) 436 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 437 438 return m; 439 } 440 441 static void 442 sunxi_emac_start_locked(struct sunxi_emac_softc *sc) 443 { 444 struct ifnet *ifp = &sc->ec.ec_if; 445 struct mbuf *m; 446 uint32_t val; 447 int cnt, nsegs, start; 448 449 EMAC_ASSERT_LOCKED(sc); 450 451 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 452 return; 453 454 for (cnt = 0, start = sc->tx.cur; ; cnt++) { 455 if (sc->tx.queued >= TX_DESC_COUNT - TX_MAX_SEGS) { 456 ifp->if_flags |= IFF_OACTIVE; 457 break; 458 } 459 460 IFQ_POLL(&ifp->if_snd, m); 461 if (m == NULL) 462 break; 463 464 nsegs = sunxi_emac_setup_txbuf(sc, sc->tx.cur, m); 465 if (nsegs == 0) { 466 ifp->if_flags |= IFF_OACTIVE; 467 break; 468 } 469 IFQ_DEQUEUE(&ifp->if_snd, m); 470 bpf_mtap(ifp, m, BPF_D_OUT); 471 472 sc->tx.cur = TX_SKIP(sc->tx.cur, nsegs); 473 } 474 475 if (cnt != 0) { 476 sunxi_emac_dma_sync(sc, sc->tx.desc_tag, sc->tx.desc_map, 477 start, sc->tx.cur, TX_DESC_COUNT, 478 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 479 480 /* Start and run TX DMA */ 481 val = RD4(sc, EMAC_TX_CTL_1); 482 WR4(sc, EMAC_TX_CTL_1, val | TX_DMA_START); 483 } 484 } 485 486 static void 487 sunxi_emac_start(struct ifnet *ifp) 488 { 489 struct sunxi_emac_softc *sc = ifp->if_softc; 490 491 EMAC_LOCK(sc); 492 sunxi_emac_start_locked(sc); 493 EMAC_UNLOCK(sc); 494 } 495 496 static void 497 sunxi_emac_tick(void *softc) 498 { 499 struct sunxi_emac_softc *sc = softc; 500 struct mii_data *mii = &sc->mii; 501 #ifndef EMAC_MPSAFE 502 int s = splnet(); 503 #endif 504 505 EMAC_LOCK(sc); 506 mii_tick(mii); 507 callout_schedule(&sc->stat_ch, hz); 508 EMAC_UNLOCK(sc); 509 510 #ifndef EMAC_MPSAFE 511 splx(s); 512 #endif 513 } 514 515 /* Bit Reversal - http://aggregate.org/MAGIC/#Bit%20Reversal */ 516 static uint32_t 517 bitrev32(uint32_t x) 518 { 519 x = (((x & 0xaaaaaaaa) >> 1) | ((x & 0x55555555) << 1)); 520 x = (((x & 0xcccccccc) >> 2) | ((x & 0x33333333) << 2)); 521 x = (((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4)); 522 x = (((x & 0xff00ff00) >> 8) | ((x & 0x00ff00ff) << 8)); 523 524 return (x >> 16) | (x << 16); 525 } 526 527 static void 528 sunxi_emac_setup_rxfilter(struct sunxi_emac_softc *sc) 529 { 530 struct ifnet *ifp = &sc->ec.ec_if; 531 uint32_t val, crc, hashreg, hashbit, hash[2], machi, maclo; 532 struct ether_multi *enm; 533 struct ether_multistep step; 534 const uint8_t *eaddr; 535 536 EMAC_ASSERT_LOCKED(sc); 537 538 val = 0; 539 hash[0] = hash[1] = 0; 540 541 if ((ifp->if_flags & IFF_PROMISC) != 0) 542 val |= DIS_ADDR_FILTER; 543 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 544 val |= RX_ALL_MULTICAST; 545 hash[0] = hash[1] = ~0; 546 } else { 547 val |= HASH_MULTICAST; 548 ETHER_FIRST_MULTI(step, &sc->ec, enm); 549 while (enm != NULL) { 550 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 551 crc &= 0x7f; 552 crc = bitrev32(~crc) >> 26; 553 hashreg = (crc >> 5); 554 hashbit = (crc & 0x1f); 555 hash[hashreg] |= (1 << hashbit); 556 ETHER_NEXT_MULTI(step, enm); 557 } 558 } 559 560 /* Write our unicast address */ 561 eaddr = CLLADDR(ifp->if_sadl); 562 machi = (eaddr[5] << 8) | eaddr[4]; 563 maclo = (eaddr[3] << 24) | (eaddr[2] << 16) | (eaddr[1] << 8) | 564 (eaddr[0] << 0); 565 WR4(sc, EMAC_ADDR_HIGH(0), machi); 566 WR4(sc, EMAC_ADDR_LOW(0), maclo); 567 568 /* Multicast hash filters */ 569 WR4(sc, EMAC_RX_HASH_0, hash[1]); 570 WR4(sc, EMAC_RX_HASH_1, hash[0]); 571 572 /* RX frame filter config */ 573 WR4(sc, EMAC_RX_FRM_FLT, val); 574 } 575 576 static void 577 sunxi_emac_enable_intr(struct sunxi_emac_softc *sc) 578 { 579 /* Enable interrupts */ 580 WR4(sc, EMAC_INT_EN, RX_INT_EN | TX_INT_EN | TX_BUF_UA_INT_EN); 581 } 582 583 static void 584 sunxi_emac_disable_intr(struct sunxi_emac_softc *sc) 585 { 586 /* Disable interrupts */ 587 WR4(sc, EMAC_INT_EN, 0); 588 } 589 590 #ifdef SUNXI_EMAC_DEBUG 591 static void 592 sunxi_emac_dump_regs(struct sunxi_emac_softc *sc) 593 { 594 static const struct { 595 const char *name; 596 u_int reg; 597 } regs[] = { 598 { "BASIC_CTL_0", EMAC_BASIC_CTL_0 }, 599 { "BASIC_CTL_1", EMAC_BASIC_CTL_1 }, 600 { "INT_STA", EMAC_INT_STA }, 601 { "INT_EN", EMAC_INT_EN }, 602 { "TX_CTL_0", EMAC_TX_CTL_0 }, 603 { "TX_CTL_1", EMAC_TX_CTL_1 }, 604 { "TX_FLOW_CTL", EMAC_TX_FLOW_CTL }, 605 { "TX_DMA_LIST", EMAC_TX_DMA_LIST }, 606 { "RX_CTL_0", EMAC_RX_CTL_0 }, 607 { "RX_CTL_1", EMAC_RX_CTL_1 }, 608 { "RX_DMA_LIST", EMAC_RX_DMA_LIST }, 609 { "RX_FRM_FLT", EMAC_RX_FRM_FLT }, 610 { "RX_HASH_0", EMAC_RX_HASH_0 }, 611 { "RX_HASH_1", EMAC_RX_HASH_1 }, 612 { "MII_CMD", EMAC_MII_CMD }, 613 { "ADDR_HIGH0", EMAC_ADDR_HIGH(0) }, 614 { "ADDR_LOW0", EMAC_ADDR_LOW(0) }, 615 { "TX_DMA_STA", EMAC_TX_DMA_STA }, 616 { "TX_DMA_CUR_DESC", EMAC_TX_DMA_CUR_DESC }, 617 { "TX_DMA_CUR_BUF", EMAC_TX_DMA_CUR_BUF }, 618 { "RX_DMA_STA", EMAC_RX_DMA_STA }, 619 { "RX_DMA_CUR_DESC", EMAC_RX_DMA_CUR_DESC }, 620 { "RX_DMA_CUR_BUF", EMAC_RX_DMA_CUR_BUF }, 621 { "RGMII_STA", EMAC_RGMII_STA }, 622 }; 623 u_int n; 624 625 for (n = 0; n < __arraycount(regs); n++) 626 device_printf(sc->dev, " %-20s %08x\n", regs[n].name, 627 RD4(sc, regs[n].reg)); 628 } 629 #endif 630 631 static int 632 sunxi_emac_reset(struct sunxi_emac_softc *sc) 633 { 634 int retry; 635 636 /* Soft reset all registers and logic */ 637 WR4(sc, EMAC_BASIC_CTL_1, BASIC_CTL_SOFT_RST); 638 639 /* Wait for soft reset bit to self-clear */ 640 for (retry = SOFT_RST_RETRY; retry > 0; retry--) { 641 if ((RD4(sc, EMAC_BASIC_CTL_1) & BASIC_CTL_SOFT_RST) == 0) 642 break; 643 delay(10); 644 } 645 if (retry == 0) { 646 aprint_debug_dev(sc->dev, "soft reset timed out\n"); 647 #ifdef SUNXI_EMAC_DEBUG 648 sunxi_emac_dump_regs(sc); 649 #endif 650 return ETIMEDOUT; 651 } 652 653 return 0; 654 } 655 656 static int 657 sunxi_emac_init_locked(struct sunxi_emac_softc *sc) 658 { 659 struct ifnet *ifp = &sc->ec.ec_if; 660 struct mii_data *mii = &sc->mii; 661 uint32_t val; 662 663 EMAC_ASSERT_LOCKED(sc); 664 665 if ((ifp->if_flags & IFF_RUNNING) != 0) 666 return 0; 667 668 /* Soft reset EMAC core */ 669 sunxi_emac_reset(sc); 670 671 /* Write transmit and receive descriptor base address registers */ 672 WR4(sc, EMAC_TX_DMA_LIST, sc->tx.desc_ring_paddr); 673 WR4(sc, EMAC_RX_DMA_LIST, sc->rx.desc_ring_paddr); 674 675 sunxi_emac_setup_rxfilter(sc); 676 677 /* Configure DMA burst length and priorities */ 678 val = sunxi_emac_burst_len << BASIC_CTL_BURST_LEN_SHIFT; 679 if (sunxi_emac_rx_tx_pri) 680 val |= BASIC_CTL_RX_TX_PRI; 681 WR4(sc, EMAC_BASIC_CTL_1, val); 682 683 /* Enable interrupts */ 684 sunxi_emac_enable_intr(sc); 685 686 /* Enable transmit DMA */ 687 val = RD4(sc, EMAC_TX_CTL_1); 688 WR4(sc, EMAC_TX_CTL_1, val | TX_DMA_EN | TX_MD | TX_NEXT_FRAME); 689 690 /* Enable receive DMA */ 691 val = RD4(sc, EMAC_RX_CTL_1); 692 WR4(sc, EMAC_RX_CTL_1, val | RX_DMA_EN | RX_MD); 693 694 /* Enable transmitter */ 695 val = RD4(sc, EMAC_TX_CTL_0); 696 WR4(sc, EMAC_TX_CTL_0, val | TX_EN); 697 698 /* Enable receiver */ 699 val = RD4(sc, EMAC_RX_CTL_0); 700 WR4(sc, EMAC_RX_CTL_0, val | RX_EN | CHECK_CRC); 701 702 ifp->if_flags |= IFF_RUNNING; 703 ifp->if_flags &= ~IFF_OACTIVE; 704 705 mii_mediachg(mii); 706 callout_schedule(&sc->stat_ch, hz); 707 708 return 0; 709 } 710 711 static int 712 sunxi_emac_init(struct ifnet *ifp) 713 { 714 struct sunxi_emac_softc *sc = ifp->if_softc; 715 int error; 716 717 EMAC_LOCK(sc); 718 error = sunxi_emac_init_locked(sc); 719 EMAC_UNLOCK(sc); 720 721 return error; 722 } 723 724 static void 725 sunxi_emac_stop_locked(struct sunxi_emac_softc *sc, int disable) 726 { 727 struct ifnet *ifp = &sc->ec.ec_if; 728 uint32_t val; 729 730 EMAC_ASSERT_LOCKED(sc); 731 732 callout_stop(&sc->stat_ch); 733 734 mii_down(&sc->mii); 735 736 /* Stop transmit DMA and flush data in the TX FIFO */ 737 val = RD4(sc, EMAC_TX_CTL_1); 738 val &= ~TX_DMA_EN; 739 val |= FLUSH_TX_FIFO; 740 WR4(sc, EMAC_TX_CTL_1, val); 741 742 /* Disable transmitter */ 743 val = RD4(sc, EMAC_TX_CTL_0); 744 WR4(sc, EMAC_TX_CTL_0, val & ~TX_EN); 745 746 /* Disable receiver */ 747 val = RD4(sc, EMAC_RX_CTL_0); 748 WR4(sc, EMAC_RX_CTL_0, val & ~RX_EN); 749 750 /* Disable interrupts */ 751 sunxi_emac_disable_intr(sc); 752 753 /* Disable transmit DMA */ 754 val = RD4(sc, EMAC_TX_CTL_1); 755 WR4(sc, EMAC_TX_CTL_1, val & ~TX_DMA_EN); 756 757 /* Disable receive DMA */ 758 val = RD4(sc, EMAC_RX_CTL_1); 759 WR4(sc, EMAC_RX_CTL_1, val & ~RX_DMA_EN); 760 761 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 762 } 763 764 static void 765 sunxi_emac_stop(struct ifnet *ifp, int disable) 766 { 767 struct sunxi_emac_softc * const sc = ifp->if_softc; 768 769 EMAC_LOCK(sc); 770 sunxi_emac_stop_locked(sc, disable); 771 EMAC_UNLOCK(sc); 772 } 773 774 static int 775 sunxi_emac_rxintr(struct sunxi_emac_softc *sc) 776 { 777 struct ifnet *ifp = &sc->ec.ec_if; 778 int error, index, len, npkt; 779 struct mbuf *m, *m0; 780 uint32_t status; 781 782 npkt = 0; 783 784 for (index = sc->rx.cur; ; index = RX_NEXT(index)) { 785 sunxi_emac_dma_sync(sc, sc->rx.desc_tag, sc->rx.desc_map, 786 index, index + 1, 787 RX_DESC_COUNT, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 788 789 status = le32toh(sc->rx.desc_ring[index].status); 790 if ((status & RX_DESC_CTL) != 0) 791 break; 792 793 bus_dmamap_sync(sc->rx.buf_tag, sc->rx.buf_map[index].map, 794 0, sc->rx.buf_map[index].map->dm_mapsize, 795 BUS_DMASYNC_POSTREAD); 796 bus_dmamap_unload(sc->rx.buf_tag, sc->rx.buf_map[index].map); 797 798 len = (status & RX_FRM_LEN) >> RX_FRM_LEN_SHIFT; 799 if (len != 0) { 800 m = sc->rx.buf_map[index].mbuf; 801 m_set_rcvif(m, ifp); 802 m->m_flags |= M_HASFCS; 803 m->m_pkthdr.len = len; 804 m->m_len = len; 805 m->m_nextpkt = NULL; 806 807 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) != 0 && 808 (status & RX_FRM_TYPE) != 0) { 809 m->m_pkthdr.csum_flags = M_CSUM_IPv4 | 810 M_CSUM_TCPv4 | M_CSUM_UDPv4; 811 if ((status & RX_HEADER_ERR) != 0) 812 m->m_pkthdr.csum_flags |= 813 M_CSUM_IPv4_BAD; 814 if ((status & RX_PAYLOAD_ERR) != 0) 815 m->m_pkthdr.csum_flags |= 816 M_CSUM_TCP_UDP_BAD; 817 } 818 819 ++npkt; 820 821 if_percpuq_enqueue(ifp->if_percpuq, m); 822 } 823 824 if ((m0 = sunxi_emac_alloc_mbufcl(sc)) != NULL) { 825 error = sunxi_emac_setup_rxbuf(sc, index, m0); 826 if (error != 0) { 827 /* XXX hole in RX ring */ 828 } 829 } else 830 ifp->if_ierrors++; 831 832 sunxi_emac_dma_sync(sc, sc->rx.desc_tag, sc->rx.desc_map, 833 index, index + 1, 834 RX_DESC_COUNT, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 835 } 836 837 sc->rx.cur = index; 838 839 return npkt; 840 } 841 842 static void 843 sunxi_emac_txintr(struct sunxi_emac_softc *sc) 844 { 845 struct ifnet *ifp = &sc->ec.ec_if; 846 struct sunxi_emac_bufmap *bmap; 847 struct sunxi_emac_desc *desc; 848 uint32_t status; 849 int i; 850 851 EMAC_ASSERT_LOCKED(sc); 852 853 for (i = sc->tx.next; sc->tx.queued > 0; i = TX_NEXT(i)) { 854 KASSERT(sc->tx.queued > 0 && sc->tx.queued <= TX_DESC_COUNT); 855 sunxi_emac_dma_sync(sc, sc->tx.desc_tag, sc->tx.desc_map, 856 i, i + 1, TX_DESC_COUNT, 857 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 858 desc = &sc->tx.desc_ring[i]; 859 status = le32toh(desc->status); 860 if ((status & TX_DESC_CTL) != 0) 861 break; 862 bmap = &sc->tx.buf_map[i]; 863 if (bmap->mbuf != NULL) { 864 bus_dmamap_sync(sc->tx.buf_tag, bmap->map, 865 0, bmap->map->dm_mapsize, 866 BUS_DMASYNC_POSTWRITE); 867 bus_dmamap_unload(sc->tx.buf_tag, bmap->map); 868 m_freem(bmap->mbuf); 869 bmap->mbuf = NULL; 870 } 871 872 sunxi_emac_setup_txdesc(sc, i, 0, 0, 0); 873 sunxi_emac_dma_sync(sc, sc->tx.desc_tag, sc->tx.desc_map, 874 i, i + 1, TX_DESC_COUNT, 875 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 876 877 ifp->if_flags &= ~IFF_OACTIVE; 878 ifp->if_opackets++; 879 } 880 881 sc->tx.next = i; 882 } 883 884 static int 885 sunxi_emac_intr(void *arg) 886 { 887 struct sunxi_emac_softc *sc = arg; 888 struct ifnet *ifp = &sc->ec.ec_if; 889 uint32_t val; 890 891 EMAC_LOCK(sc); 892 893 val = RD4(sc, EMAC_INT_STA); 894 WR4(sc, EMAC_INT_STA, val); 895 896 if (val & RX_INT) 897 sunxi_emac_rxintr(sc); 898 899 if (val & (TX_INT|TX_BUF_UA_INT)) { 900 sunxi_emac_txintr(sc); 901 if_schedule_deferred_start(ifp); 902 } 903 904 EMAC_UNLOCK(sc); 905 906 return 1; 907 } 908 909 static int 910 sunxi_emac_ioctl(struct ifnet *ifp, u_long cmd, void *data) 911 { 912 struct sunxi_emac_softc *sc = ifp->if_softc; 913 struct mii_data *mii = &sc->mii; 914 struct ifreq *ifr = data; 915 int error, s; 916 917 #ifndef EMAC_MPSAFE 918 s = splnet(); 919 #endif 920 921 switch (cmd) { 922 case SIOCSIFMEDIA: 923 case SIOCGIFMEDIA: 924 #ifdef EMAC_MPSAFE 925 s = splnet(); 926 #endif 927 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 928 #ifdef EMAC_MPSAFE 929 splx(s); 930 #endif 931 break; 932 default: 933 #ifdef EMAC_MPSAFE 934 s = splnet(); 935 #endif 936 error = ether_ioctl(ifp, cmd, data); 937 #ifdef EMAC_MPSAFE 938 splx(s); 939 #endif 940 if (error != ENETRESET) 941 break; 942 943 error = 0; 944 945 if (cmd == SIOCSIFCAP) 946 error = (*ifp->if_init)(ifp); 947 else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 948 ; 949 else if ((ifp->if_flags & IFF_RUNNING) != 0) { 950 EMAC_LOCK(sc); 951 sunxi_emac_setup_rxfilter(sc); 952 EMAC_UNLOCK(sc); 953 } 954 break; 955 } 956 957 #ifndef EMAC_MPSAFE 958 splx(s); 959 #endif 960 961 return error; 962 } 963 964 static bool 965 sunxi_emac_has_internal_phy(struct sunxi_emac_softc *sc) 966 { 967 const char * mdio_internal_compat[] = { 968 "allwinner,sun8i-h3-mdio-internal", 969 NULL 970 }; 971 int phy; 972 973 /* Non-standard property, for compatible with old dts files */ 974 if (of_hasprop(sc->phandle, "allwinner,use-internal-phy")) 975 return true; 976 977 phy = fdtbus_get_phandle(sc->phandle, "phy-handle"); 978 if (phy == -1) 979 return false; 980 981 /* For internal PHY, check compatible string of parent node */ 982 return of_compatible(OF_parent(phy), mdio_internal_compat) >= 0; 983 } 984 985 static int 986 sunxi_emac_setup_phy(struct sunxi_emac_softc *sc) 987 { 988 uint32_t reg, tx_delay, rx_delay; 989 const char *phy_type; 990 991 phy_type = fdtbus_get_string(sc->phandle, "phy-mode"); 992 if (phy_type == NULL) 993 return 0; 994 995 aprint_debug_dev(sc->dev, "PHY type: %s\n", phy_type); 996 997 syscon_lock(sc->syscon); 998 reg = syscon_read_4(sc->syscon, EMAC_CLK_REG); 999 1000 reg &= ~(EMAC_CLK_PIT | EMAC_CLK_SRC | EMAC_CLK_RMII_EN); 1001 if (strcmp(phy_type, "rgmii") == 0) 1002 reg |= EMAC_CLK_PIT_RGMII | EMAC_CLK_SRC_RGMII; 1003 else if (strcmp(phy_type, "rmii") == 0) 1004 reg |= EMAC_CLK_RMII_EN; 1005 else 1006 reg |= EMAC_CLK_PIT_MII | EMAC_CLK_SRC_MII; 1007 1008 if (of_getprop_uint32(sc->phandle, "allwinner,tx-delay-ps", 1009 &tx_delay) == 0) { 1010 reg &= ~EMAC_CLK_ETXDC; 1011 reg |= ((tx_delay / 100) << EMAC_CLK_ETXDC_SHIFT); 1012 } else if (of_getprop_uint32(sc->phandle, "tx-delay", &tx_delay) == 0) { 1013 reg &= ~EMAC_CLK_ETXDC; 1014 reg |= (tx_delay << EMAC_CLK_ETXDC_SHIFT); 1015 } 1016 if (of_getprop_uint32(sc->phandle, "allwinner,rx-delay-ps", 1017 &rx_delay) == 0) { 1018 reg &= ~EMAC_CLK_ERXDC; 1019 reg |= ((rx_delay / 100) << EMAC_CLK_ERXDC_SHIFT); 1020 } else if (of_getprop_uint32(sc->phandle, "rx-delay", &rx_delay) == 0) { 1021 reg &= ~EMAC_CLK_ERXDC; 1022 reg |= (rx_delay << EMAC_CLK_ERXDC_SHIFT); 1023 } 1024 1025 if (sc->type == EMAC_H3 || sc->type == EMAC_H6) { 1026 if (sunxi_emac_has_internal_phy(sc)) { 1027 reg |= EMAC_CLK_EPHY_SELECT; 1028 reg &= ~EMAC_CLK_EPHY_SHUTDOWN; 1029 if (of_hasprop(sc->phandle, 1030 "allwinner,leds-active-low")) 1031 reg |= EMAC_CLK_EPHY_LED_POL; 1032 else 1033 reg &= ~EMAC_CLK_EPHY_LED_POL; 1034 1035 /* Set internal PHY addr to 1 */ 1036 reg &= ~EMAC_CLK_EPHY_ADDR; 1037 reg |= (1 << EMAC_CLK_EPHY_ADDR_SHIFT); 1038 } else { 1039 reg &= ~EMAC_CLK_EPHY_SELECT; 1040 } 1041 } 1042 1043 aprint_debug_dev(sc->dev, "EMAC clock: 0x%08x\n", reg); 1044 1045 syscon_write_4(sc->syscon, EMAC_CLK_REG, reg); 1046 syscon_unlock(sc->syscon); 1047 1048 return 0; 1049 } 1050 1051 static int 1052 sunxi_emac_setup_resources(struct sunxi_emac_softc *sc) 1053 { 1054 u_int freq; 1055 int error, div; 1056 1057 /* Configure PHY for MII or RGMII mode */ 1058 if (sunxi_emac_setup_phy(sc) != 0) 1059 return ENXIO; 1060 1061 /* Enable clocks */ 1062 error = clk_enable(sc->clk_ahb); 1063 if (error != 0) { 1064 aprint_error_dev(sc->dev, "cannot enable ahb clock\n"); 1065 return error; 1066 } 1067 1068 if (sc->clk_ephy != NULL) { 1069 error = clk_enable(sc->clk_ephy); 1070 if (error != 0) { 1071 aprint_error_dev(sc->dev, "cannot enable ephy clock\n"); 1072 return error; 1073 } 1074 } 1075 1076 /* De-assert reset */ 1077 error = fdtbus_reset_deassert(sc->rst_ahb); 1078 if (error != 0) { 1079 aprint_error_dev(sc->dev, "cannot de-assert ahb reset\n"); 1080 return error; 1081 } 1082 if (sc->rst_ephy != NULL) { 1083 error = fdtbus_reset_deassert(sc->rst_ephy); 1084 if (error != 0) { 1085 aprint_error_dev(sc->dev, 1086 "cannot de-assert ephy reset\n"); 1087 return error; 1088 } 1089 } 1090 1091 /* Enable PHY regulator if applicable */ 1092 if (sc->reg_phy != NULL) { 1093 error = fdtbus_regulator_enable(sc->reg_phy); 1094 if (error != 0) { 1095 aprint_error_dev(sc->dev, 1096 "cannot enable PHY regulator\n"); 1097 return error; 1098 } 1099 } 1100 1101 /* Determine MDC clock divide ratio based on AHB clock */ 1102 freq = clk_get_rate(sc->clk_ahb); 1103 if (freq == 0) { 1104 aprint_error_dev(sc->dev, "cannot get AHB clock frequency\n"); 1105 return ENXIO; 1106 } 1107 div = freq / MDIO_FREQ; 1108 if (div <= 16) 1109 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_16; 1110 else if (div <= 32) 1111 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_32; 1112 else if (div <= 64) 1113 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_64; 1114 else if (div <= 128) 1115 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_128; 1116 else { 1117 aprint_error_dev(sc->dev, 1118 "cannot determine MDC clock divide ratio\n"); 1119 return ENXIO; 1120 } 1121 1122 aprint_debug_dev(sc->dev, "AHB frequency %u Hz, MDC div: 0x%x\n", 1123 freq, sc->mdc_div_ratio_m); 1124 1125 return 0; 1126 } 1127 1128 static void 1129 sunxi_emac_get_eaddr(struct sunxi_emac_softc *sc, uint8_t *eaddr) 1130 { 1131 uint32_t maclo, machi; 1132 #if notyet 1133 u_char rootkey[16]; 1134 #endif 1135 1136 machi = RD4(sc, EMAC_ADDR_HIGH(0)) & 0xffff; 1137 maclo = RD4(sc, EMAC_ADDR_LOW(0)); 1138 1139 if (maclo == 0xffffffff && machi == 0xffff) { 1140 #if notyet 1141 /* MAC address in hardware is invalid, create one */ 1142 if (aw_sid_get_rootkey(rootkey) == 0 && 1143 (rootkey[3] | rootkey[12] | rootkey[13] | rootkey[14] | 1144 rootkey[15]) != 0) { 1145 /* MAC address is derived from the root key in SID */ 1146 maclo = (rootkey[13] << 24) | (rootkey[12] << 16) | 1147 (rootkey[3] << 8) | 0x02; 1148 machi = (rootkey[15] << 8) | rootkey[14]; 1149 } else { 1150 #endif 1151 /* Create one */ 1152 maclo = 0x00f2 | (cprng_strong32() & 0xffff0000); 1153 machi = cprng_strong32() & 0xffff; 1154 #if notyet 1155 } 1156 #endif 1157 } 1158 1159 eaddr[0] = maclo & 0xff; 1160 eaddr[1] = (maclo >> 8) & 0xff; 1161 eaddr[2] = (maclo >> 16) & 0xff; 1162 eaddr[3] = (maclo >> 24) & 0xff; 1163 eaddr[4] = machi & 0xff; 1164 eaddr[5] = (machi >> 8) & 0xff; 1165 } 1166 1167 static int 1168 sunxi_emac_phy_reset(struct sunxi_emac_softc *sc) 1169 { 1170 uint32_t delay_prop[3]; 1171 int pin_value; 1172 1173 if (sc->pin_reset == NULL) 1174 return 0; 1175 1176 if (OF_getprop(sc->phandle, "allwinner,reset-delays-us", delay_prop, 1177 sizeof(delay_prop)) <= 0) 1178 return ENXIO; 1179 1180 pin_value = of_hasprop(sc->phandle, "allwinner,reset-active-low"); 1181 1182 fdtbus_gpio_write(sc->pin_reset, pin_value); 1183 delay(htole32(delay_prop[0])); 1184 fdtbus_gpio_write(sc->pin_reset, !pin_value); 1185 delay(htole32(delay_prop[1])); 1186 fdtbus_gpio_write(sc->pin_reset, pin_value); 1187 delay(htole32(delay_prop[2])); 1188 1189 return 0; 1190 } 1191 1192 static int 1193 sunxi_emac_setup_dma(struct sunxi_emac_softc *sc) 1194 { 1195 struct mbuf *m; 1196 int error, nsegs, i; 1197 1198 /* Setup TX ring */ 1199 sc->tx.buf_tag = sc->tx.desc_tag = sc->dmat; 1200 error = bus_dmamap_create(sc->dmat, TX_DESC_SIZE, 1, TX_DESC_SIZE, 0, 1201 BUS_DMA_WAITOK, &sc->tx.desc_map); 1202 if (error) 1203 return error; 1204 error = bus_dmamem_alloc(sc->dmat, TX_DESC_SIZE, DESC_ALIGN, 0, 1205 &sc->tx.desc_dmaseg, 1, &nsegs, BUS_DMA_WAITOK); 1206 if (error) 1207 return error; 1208 error = bus_dmamem_map(sc->dmat, &sc->tx.desc_dmaseg, nsegs, 1209 TX_DESC_SIZE, (void *)&sc->tx.desc_ring, 1210 BUS_DMA_WAITOK); 1211 if (error) 1212 return error; 1213 error = bus_dmamap_load(sc->dmat, sc->tx.desc_map, sc->tx.desc_ring, 1214 TX_DESC_SIZE, NULL, BUS_DMA_WAITOK); 1215 if (error) 1216 return error; 1217 sc->tx.desc_ring_paddr = sc->tx.desc_map->dm_segs[0].ds_addr; 1218 1219 memset(sc->tx.desc_ring, 0, TX_DESC_SIZE); 1220 bus_dmamap_sync(sc->dmat, sc->tx.desc_map, 0, TX_DESC_SIZE, 1221 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1222 1223 for (i = 0; i < TX_DESC_COUNT; i++) 1224 sc->tx.desc_ring[i].next = 1225 htole32(sc->tx.desc_ring_paddr + DESC_OFF(TX_NEXT(i))); 1226 1227 sc->tx.queued = TX_DESC_COUNT; 1228 for (i = 0; i < TX_DESC_COUNT; i++) { 1229 error = bus_dmamap_create(sc->tx.buf_tag, MCLBYTES, 1230 TX_MAX_SEGS, MCLBYTES, 0, BUS_DMA_WAITOK, 1231 &sc->tx.buf_map[i].map); 1232 if (error != 0) { 1233 device_printf(sc->dev, "cannot create TX buffer map\n"); 1234 return error; 1235 } 1236 sunxi_emac_setup_txdesc(sc, i, 0, 0, 0); 1237 } 1238 1239 /* Setup RX ring */ 1240 sc->rx.buf_tag = sc->rx.desc_tag = sc->dmat; 1241 error = bus_dmamap_create(sc->dmat, RX_DESC_SIZE, 1, RX_DESC_SIZE, 0, 1242 BUS_DMA_WAITOK, &sc->rx.desc_map); 1243 if (error) 1244 return error; 1245 error = bus_dmamem_alloc(sc->dmat, RX_DESC_SIZE, DESC_ALIGN, 0, 1246 &sc->rx.desc_dmaseg, 1, &nsegs, BUS_DMA_WAITOK); 1247 if (error) 1248 return error; 1249 error = bus_dmamem_map(sc->dmat, &sc->rx.desc_dmaseg, nsegs, 1250 RX_DESC_SIZE, (void *)&sc->rx.desc_ring, 1251 BUS_DMA_WAITOK); 1252 if (error) 1253 return error; 1254 error = bus_dmamap_load(sc->dmat, sc->rx.desc_map, sc->rx.desc_ring, 1255 RX_DESC_SIZE, NULL, BUS_DMA_WAITOK); 1256 if (error) 1257 return error; 1258 sc->rx.desc_ring_paddr = sc->rx.desc_map->dm_segs[0].ds_addr; 1259 1260 memset(sc->rx.desc_ring, 0, RX_DESC_SIZE); 1261 1262 for (i = 0; i < RX_DESC_COUNT; i++) { 1263 error = bus_dmamap_create(sc->rx.buf_tag, MCLBYTES, 1264 RX_DESC_COUNT, MCLBYTES, 0, BUS_DMA_WAITOK, 1265 &sc->rx.buf_map[i].map); 1266 if (error != 0) { 1267 device_printf(sc->dev, "cannot create RX buffer map\n"); 1268 return error; 1269 } 1270 if ((m = sunxi_emac_alloc_mbufcl(sc)) == NULL) { 1271 device_printf(sc->dev, "cannot allocate RX mbuf\n"); 1272 return ENOMEM; 1273 } 1274 error = sunxi_emac_setup_rxbuf(sc, i, m); 1275 if (error != 0) { 1276 device_printf(sc->dev, "cannot create RX buffer\n"); 1277 return error; 1278 } 1279 } 1280 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map, 1281 0, sc->rx.desc_map->dm_mapsize, 1282 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1283 1284 return 0; 1285 } 1286 1287 static int 1288 sunxi_emac_get_resources(struct sunxi_emac_softc *sc) 1289 { 1290 const int phandle = sc->phandle; 1291 bus_addr_t addr, size; 1292 1293 /* Map EMAC registers */ 1294 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) 1295 return ENXIO; 1296 if (bus_space_map(sc->bst, addr, size, 0, &sc->bsh) != 0) 1297 return ENXIO; 1298 1299 /* Get SYSCON registers */ 1300 sc->syscon = fdtbus_syscon_acquire(phandle, "syscon"); 1301 if (sc->syscon == NULL) 1302 return ENXIO; 1303 1304 /* The "ahb"/"stmmaceth" clock and reset is required */ 1305 if ((sc->clk_ahb = fdtbus_clock_get(phandle, "ahb")) == NULL && 1306 (sc->clk_ahb = fdtbus_clock_get(phandle, "stmmaceth")) == NULL) 1307 return ENXIO; 1308 if ((sc->rst_ahb = fdtbus_reset_get(phandle, "ahb")) == NULL && 1309 (sc->rst_ahb = fdtbus_reset_get(phandle, "stmmaceth")) == NULL) 1310 return ENXIO; 1311 1312 /* Internal PHY clock and reset are optional properties. */ 1313 sc->clk_ephy = fdtbus_clock_get(phandle, "ephy"); 1314 if (sc->clk_ephy == NULL) { 1315 int phy_phandle = fdtbus_get_phandle(phandle, "phy-handle"); 1316 if (phy_phandle != -1) 1317 sc->clk_ephy = fdtbus_clock_get_index(phy_phandle, 0); 1318 } 1319 sc->rst_ephy = fdtbus_reset_get(phandle, "ephy"); 1320 if (sc->rst_ephy == NULL) { 1321 int phy_phandle = fdtbus_get_phandle(phandle, "phy-handle"); 1322 if (phy_phandle != -1) 1323 sc->rst_ephy = fdtbus_reset_get_index(phy_phandle, 0); 1324 } 1325 1326 /* Regulator is optional */ 1327 sc->reg_phy = fdtbus_regulator_acquire(phandle, "phy-supply"); 1328 1329 /* Reset GPIO is optional */ 1330 sc->pin_reset = fdtbus_gpio_acquire(sc->phandle, 1331 "allwinner,reset-gpio", GPIO_PIN_OUTPUT); 1332 1333 return 0; 1334 } 1335 1336 static int 1337 sunxi_emac_get_phyid(struct sunxi_emac_softc *sc) 1338 { 1339 bus_addr_t addr; 1340 int phy_phandle; 1341 1342 phy_phandle = fdtbus_get_phandle(sc->phandle, "phy"); 1343 if (phy_phandle == -1) 1344 phy_phandle = fdtbus_get_phandle(sc->phandle, "phy-handle"); 1345 if (phy_phandle == -1) 1346 return MII_PHY_ANY; 1347 1348 if (fdtbus_get_reg(phy_phandle, 0, &addr, NULL) != 0) 1349 return MII_PHY_ANY; 1350 1351 return (int)addr; 1352 } 1353 1354 static int 1355 sunxi_emac_match(device_t parent, cfdata_t cf, void *aux) 1356 { 1357 struct fdt_attach_args * const faa = aux; 1358 1359 return of_match_compat_data(faa->faa_phandle, compat_data); 1360 } 1361 1362 static void 1363 sunxi_emac_attach(device_t parent, device_t self, void *aux) 1364 { 1365 struct fdt_attach_args * const faa = aux; 1366 struct sunxi_emac_softc * const sc = device_private(self); 1367 const int phandle = faa->faa_phandle; 1368 struct mii_data *mii = &sc->mii; 1369 struct ifnet *ifp = &sc->ec.ec_if; 1370 uint8_t eaddr[ETHER_ADDR_LEN]; 1371 char intrstr[128]; 1372 1373 sc->dev = self; 1374 sc->phandle = phandle; 1375 sc->bst = faa->faa_bst; 1376 sc->dmat = faa->faa_dmat; 1377 sc->type = of_search_compatible(phandle, compat_data)->data; 1378 sc->phy_id = sunxi_emac_get_phyid(sc); 1379 1380 if (sunxi_emac_get_resources(sc) != 0) { 1381 aprint_error(": cannot allocate resources for device\n"); 1382 return; 1383 } 1384 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 1385 aprint_error(": cannot decode interrupt\n"); 1386 return; 1387 } 1388 1389 mutex_init(&sc->mtx, MUTEX_DEFAULT, IPL_NET); 1390 callout_init(&sc->stat_ch, CALLOUT_FLAGS); 1391 callout_setfunc(&sc->stat_ch, sunxi_emac_tick, sc); 1392 1393 aprint_naive("\n"); 1394 aprint_normal(": EMAC\n"); 1395 1396 /* Setup clocks and regulators */ 1397 if (sunxi_emac_setup_resources(sc) != 0) 1398 return; 1399 1400 /* Read MAC address before resetting the chip */ 1401 sunxi_emac_get_eaddr(sc, eaddr); 1402 aprint_normal_dev(self, "Ethernet address %s\n", ether_sprintf(eaddr)); 1403 1404 /* Reset PHY if necessary */ 1405 if (sunxi_emac_phy_reset(sc) != 0) { 1406 aprint_error_dev(self, "failed to reset PHY\n"); 1407 return; 1408 } 1409 1410 /* Setup DMA descriptors */ 1411 if (sunxi_emac_setup_dma(sc) != 0) { 1412 aprint_error_dev(self, "failed to setup DMA descriptors\n"); 1413 return; 1414 } 1415 1416 /* Install interrupt handler */ 1417 sc->ih = fdtbus_intr_establish(phandle, 0, IPL_NET, 1418 FDT_INTR_FLAGS, sunxi_emac_intr, sc); 1419 if (sc->ih == NULL) { 1420 aprint_error_dev(self, "failed to establish interrupt on %s\n", 1421 intrstr); 1422 return; 1423 } 1424 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 1425 1426 /* Setup ethernet interface */ 1427 ifp->if_softc = sc; 1428 snprintf(ifp->if_xname, IFNAMSIZ, EMAC_IFNAME, device_unit(self)); 1429 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1430 #ifdef EMAC_MPSAFE 1431 ifp->if_extflags = IFEF_MPSAFE; 1432 #endif 1433 ifp->if_start = sunxi_emac_start; 1434 ifp->if_ioctl = sunxi_emac_ioctl; 1435 ifp->if_init = sunxi_emac_init; 1436 ifp->if_stop = sunxi_emac_stop; 1437 ifp->if_capabilities = IFCAP_CSUM_IPv4_Rx | 1438 IFCAP_CSUM_IPv4_Tx | 1439 IFCAP_CSUM_TCPv4_Rx | 1440 IFCAP_CSUM_TCPv4_Tx | 1441 IFCAP_CSUM_UDPv4_Rx | 1442 IFCAP_CSUM_UDPv4_Tx; 1443 ifp->if_capenable = ifp->if_capabilities; 1444 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 1445 IFQ_SET_READY(&ifp->if_snd); 1446 1447 /* 802.1Q VLAN-sized frames are supported */ 1448 sc->ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 1449 1450 /* Attach MII driver */ 1451 sc->ec.ec_mii = mii; 1452 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 1453 mii->mii_ifp = ifp; 1454 mii->mii_readreg = sunxi_emac_mii_readreg; 1455 mii->mii_writereg = sunxi_emac_mii_writereg; 1456 mii->mii_statchg = sunxi_emac_mii_statchg; 1457 mii_attach(self, mii, 0xffffffff, sc->phy_id, MII_OFFSET_ANY, 1458 MIIF_DOPAUSE); 1459 1460 if (LIST_EMPTY(&mii->mii_phys)) { 1461 aprint_error_dev(self, "no PHY found!\n"); 1462 return; 1463 } 1464 ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_AUTO); 1465 1466 /* Attach interface */ 1467 if_attach(ifp); 1468 if_deferred_start_init(ifp, NULL); 1469 1470 /* Attach ethernet interface */ 1471 ether_ifattach(ifp, eaddr); 1472 } 1473 1474 CFATTACH_DECL_NEW(sunxi_emac, sizeof(struct sunxi_emac_softc), 1475 sunxi_emac_match, sunxi_emac_attach, NULL, NULL); 1476
Indexes created Wed Oct 22 13:09:56 GMT 2025