sunxi_emac.c revision 1.28.4.1
1 /* $NetBSD: sunxi_emac.c,v 1.28.4.1 2020/02/29 20:18:20 ad Exp $ */ 2 3 /*- 4 * Copyright (c) 2016-2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Allwinner Gigabit Ethernet MAC (EMAC) controller 31 */ 32 33 #include "opt_net_mpsafe.h" 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: sunxi_emac.c,v 1.28.4.1 2020/02/29 20:18:20 ad Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/bus.h> 40 #include <sys/device.h> 41 #include <sys/intr.h> 42 #include <sys/systm.h> 43 #include <sys/kernel.h> 44 #include <sys/mutex.h> 45 #include <sys/callout.h> 46 #include <sys/gpio.h> 47 #include <sys/cprng.h> 48 49 #include <net/if.h> 50 #include <net/if_dl.h> 51 #include <net/if_ether.h> 52 #include <net/if_media.h> 53 #include <net/bpf.h> 54 55 #include <dev/mii/miivar.h> 56 57 #include <dev/fdt/fdtvar.h> 58 #include <dev/fdt/syscon.h> 59 60 #include <arm/sunxi/sunxi_emac.h> 61 62 #ifdef NET_MPSAFE 63 #define EMAC_MPSAFE 1 64 #define CALLOUT_FLAGS CALLOUT_MPSAFE 65 #define FDT_INTR_FLAGS FDT_INTR_MPSAFE 66 #else 67 #define CALLOUT_FLAGS 0 68 #define FDT_INTR_FLAGS 0 69 #endif 70 71 #define EMAC_IFNAME "emac%d" 72 73 #define EMAC_LOCK(sc) mutex_enter(&(sc)->mtx) 74 #define EMAC_UNLOCK(sc) mutex_exit(&(sc)->mtx) 75 #define EMAC_ASSERT_LOCKED(sc) KASSERT(mutex_owned(&(sc)->mtx)) 76 77 #define DESC_ALIGN sizeof(struct sunxi_emac_desc) 78 #define TX_DESC_COUNT 1024 79 #define TX_DESC_SIZE (sizeof(struct sunxi_emac_desc) * TX_DESC_COUNT) 80 #define RX_DESC_COUNT 256 81 #define RX_DESC_SIZE (sizeof(struct sunxi_emac_desc) * RX_DESC_COUNT) 82 83 #define DESC_OFF(n) ((n) * sizeof(struct sunxi_emac_desc)) 84 #define TX_NEXT(n) (((n) + 1) & (TX_DESC_COUNT - 1)) 85 #define TX_SKIP(n, o) (((n) + (o)) & (TX_DESC_COUNT - 1)) 86 #define RX_NEXT(n) (((n) + 1) & (RX_DESC_COUNT - 1)) 87 88 #define TX_MAX_SEGS 128 89 90 #define SOFT_RST_RETRY 1000 91 #define MII_BUSY_RETRY 1000 92 #define MDIO_FREQ 2500000 93 94 #define BURST_LEN_DEFAULT 8 95 #define RX_TX_PRI_DEFAULT 0 96 #define PAUSE_TIME_DEFAULT 0x400 97 98 /* syscon EMAC clock register */ 99 #define EMAC_CLK_REG 0x30 100 #define EMAC_CLK_EPHY_ADDR (0x1f << 20) /* H3 */ 101 #define EMAC_CLK_EPHY_ADDR_SHIFT 20 102 #define EMAC_CLK_EPHY_LED_POL (1 << 17) /* H3 */ 103 #define EMAC_CLK_EPHY_SHUTDOWN (1 << 16) /* H3 */ 104 #define EMAC_CLK_EPHY_SELECT (1 << 15) /* H3 */ 105 #define EMAC_CLK_RMII_EN (1 << 13) 106 #define EMAC_CLK_ETXDC (0x7 << 10) 107 #define EMAC_CLK_ETXDC_SHIFT 10 108 #define EMAC_CLK_ERXDC (0x1f << 5) 109 #define EMAC_CLK_ERXDC_SHIFT 5 110 #define EMAC_CLK_PIT (0x1 << 2) 111 #define EMAC_CLK_PIT_MII (0 << 2) 112 #define EMAC_CLK_PIT_RGMII (1 << 2) 113 #define EMAC_CLK_SRC (0x3 << 0) 114 #define EMAC_CLK_SRC_MII (0 << 0) 115 #define EMAC_CLK_SRC_EXT_RGMII (1 << 0) 116 #define EMAC_CLK_SRC_RGMII (2 << 0) 117 118 /* Burst length of RX and TX DMA transfers */ 119 static int sunxi_emac_burst_len = BURST_LEN_DEFAULT; 120 121 /* RX / TX DMA priority. If 1, RX DMA has priority over TX DMA. */ 122 static int sunxi_emac_rx_tx_pri = RX_TX_PRI_DEFAULT; 123 124 /* Pause time field in the transmitted control frame */ 125 static int sunxi_emac_pause_time = PAUSE_TIME_DEFAULT; 126 127 enum sunxi_emac_type { 128 EMAC_A64 = 1, 129 EMAC_A83T, 130 EMAC_H3, 131 EMAC_H6, 132 }; 133 134 static const struct of_compat_data compat_data[] = { 135 { "allwinner,sun8i-a83t-emac", EMAC_A83T }, 136 { "allwinner,sun8i-h3-emac", EMAC_H3 }, 137 { "allwinner,sun50i-a64-emac", EMAC_A64 }, 138 { "allwinner,sun50i-h6-emac", EMAC_H6 }, 139 { NULL } 140 }; 141 142 struct sunxi_emac_bufmap { 143 bus_dmamap_t map; 144 struct mbuf *mbuf; 145 }; 146 147 struct sunxi_emac_txring { 148 bus_dma_tag_t desc_tag; 149 bus_dmamap_t desc_map; 150 bus_dma_segment_t desc_dmaseg; 151 struct sunxi_emac_desc *desc_ring; 152 bus_addr_t desc_ring_paddr; 153 bus_dma_tag_t buf_tag; 154 struct sunxi_emac_bufmap buf_map[TX_DESC_COUNT]; 155 u_int cur, next, queued; 156 }; 157 158 struct sunxi_emac_rxring { 159 bus_dma_tag_t desc_tag; 160 bus_dmamap_t desc_map; 161 bus_dma_segment_t desc_dmaseg; 162 struct sunxi_emac_desc *desc_ring; 163 bus_addr_t desc_ring_paddr; 164 bus_dma_tag_t buf_tag; 165 struct sunxi_emac_bufmap buf_map[RX_DESC_COUNT]; 166 u_int cur; 167 }; 168 169 struct sunxi_emac_softc { 170 device_t dev; 171 int phandle; 172 enum sunxi_emac_type type; 173 bus_space_tag_t bst; 174 bus_dma_tag_t dmat; 175 176 bus_space_handle_t bsh; 177 struct clk *clk_ahb; 178 struct clk *clk_ephy; 179 struct fdtbus_reset *rst_ahb; 180 struct fdtbus_reset *rst_ephy; 181 struct fdtbus_regulator *reg_phy; 182 struct fdtbus_gpio_pin *pin_reset; 183 184 struct syscon *syscon; 185 186 int phy_id; 187 188 kmutex_t mtx; 189 struct ethercom ec; 190 struct mii_data mii; 191 callout_t stat_ch; 192 void *ih; 193 u_int mdc_div_ratio_m; 194 195 struct sunxi_emac_txring tx; 196 struct sunxi_emac_rxring rx; 197 }; 198 199 #define RD4(sc, reg) \ 200 bus_space_read_4((sc)->bst, (sc)->bsh, (reg)) 201 #define WR4(sc, reg, val) \ 202 bus_space_write_4((sc)->bst, (sc)->bsh, (reg), (val)) 203 204 static int 205 sunxi_emac_mii_readreg(device_t dev, int phy, int reg, uint16_t *val) 206 { 207 struct sunxi_emac_softc *sc = device_private(dev); 208 int retry; 209 210 WR4(sc, EMAC_MII_CMD, 211 (sc->mdc_div_ratio_m << MDC_DIV_RATIO_M_SHIFT) | 212 (phy << PHY_ADDR_SHIFT) | 213 (reg << PHY_REG_ADDR_SHIFT) | 214 MII_BUSY); 215 for (retry = MII_BUSY_RETRY; retry > 0; retry--) { 216 if ((RD4(sc, EMAC_MII_CMD) & MII_BUSY) == 0) { 217 *val = RD4(sc, EMAC_MII_DATA) & 0xffff; 218 break; 219 } 220 delay(10); 221 } 222 223 if (retry == 0) { 224 device_printf(dev, "phy read timeout, phy=%d reg=%d\n", 225 phy, reg); 226 return ETIMEDOUT; 227 } 228 229 return 0; 230 } 231 232 static int 233 sunxi_emac_mii_writereg(device_t dev, int phy, int reg, uint16_t val) 234 { 235 struct sunxi_emac_softc *sc = device_private(dev); 236 int retry; 237 238 WR4(sc, EMAC_MII_DATA, val); 239 WR4(sc, EMAC_MII_CMD, 240 (sc->mdc_div_ratio_m << MDC_DIV_RATIO_M_SHIFT) | 241 (phy << PHY_ADDR_SHIFT) | 242 (reg << PHY_REG_ADDR_SHIFT) | 243 MII_WR | MII_BUSY); 244 for (retry = MII_BUSY_RETRY; retry > 0; retry--) { 245 if ((RD4(sc, EMAC_MII_CMD) & MII_BUSY) == 0) 246 break; 247 delay(10); 248 } 249 250 if (retry == 0) { 251 device_printf(dev, "phy write timeout, phy=%d reg=%d\n", 252 phy, reg); 253 return ETIMEDOUT; 254 } 255 256 return 0; 257 } 258 259 static void 260 sunxi_emac_update_link(struct sunxi_emac_softc *sc) 261 { 262 struct mii_data *mii = &sc->mii; 263 uint32_t val; 264 265 val = RD4(sc, EMAC_BASIC_CTL_0); 266 val &= ~(BASIC_CTL_SPEED | BASIC_CTL_DUPLEX); 267 268 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 269 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 270 val |= BASIC_CTL_SPEED_1000 << BASIC_CTL_SPEED_SHIFT; 271 else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) 272 val |= BASIC_CTL_SPEED_100 << BASIC_CTL_SPEED_SHIFT; 273 else 274 val |= BASIC_CTL_SPEED_10 << BASIC_CTL_SPEED_SHIFT; 275 276 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 277 val |= BASIC_CTL_DUPLEX; 278 279 WR4(sc, EMAC_BASIC_CTL_0, val); 280 281 val = RD4(sc, EMAC_RX_CTL_0); 282 val &= ~RX_FLOW_CTL_EN; 283 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 284 val |= RX_FLOW_CTL_EN; 285 WR4(sc, EMAC_RX_CTL_0, val); 286 287 val = RD4(sc, EMAC_TX_FLOW_CTL); 288 val &= ~(PAUSE_TIME | TX_FLOW_CTL_EN); 289 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 290 val |= TX_FLOW_CTL_EN; 291 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 292 val |= sunxi_emac_pause_time << PAUSE_TIME_SHIFT; 293 WR4(sc, EMAC_TX_FLOW_CTL, val); 294 } 295 296 static void 297 sunxi_emac_mii_statchg(struct ifnet *ifp) 298 { 299 struct sunxi_emac_softc * const sc = ifp->if_softc; 300 301 sunxi_emac_update_link(sc); 302 } 303 304 static void 305 sunxi_emac_dma_sync(struct sunxi_emac_softc *sc, bus_dma_tag_t dmat, 306 bus_dmamap_t map, int start, int end, int total, int flags) 307 { 308 if (end > start) { 309 bus_dmamap_sync(dmat, map, DESC_OFF(start), 310 DESC_OFF(end) - DESC_OFF(start), flags); 311 } else { 312 bus_dmamap_sync(dmat, map, DESC_OFF(start), 313 DESC_OFF(total) - DESC_OFF(start), flags); 314 if (DESC_OFF(end) - DESC_OFF(0) > 0) 315 bus_dmamap_sync(dmat, map, DESC_OFF(0), 316 DESC_OFF(end) - DESC_OFF(0), flags); 317 } 318 } 319 320 static void 321 sunxi_emac_setup_txdesc(struct sunxi_emac_softc *sc, int index, int flags, 322 bus_addr_t paddr, u_int len) 323 { 324 uint32_t status, size; 325 326 if (paddr == 0 || len == 0) { 327 status = 0; 328 size = 0; 329 --sc->tx.queued; 330 } else { 331 status = TX_DESC_CTL; 332 size = flags | len; 333 ++sc->tx.queued; 334 } 335 336 sc->tx.desc_ring[index].addr = htole32((uint32_t)paddr); 337 sc->tx.desc_ring[index].size = htole32(size); 338 sc->tx.desc_ring[index].status = htole32(status); 339 } 340 341 static int 342 sunxi_emac_setup_txbuf(struct sunxi_emac_softc *sc, int index, struct mbuf *m) 343 { 344 bus_dma_segment_t *segs; 345 int error, nsegs, cur, i, flags; 346 u_int csum_flags; 347 348 error = bus_dmamap_load_mbuf(sc->tx.buf_tag, 349 sc->tx.buf_map[index].map, m, BUS_DMA_WRITE | BUS_DMA_NOWAIT); 350 if (error == EFBIG) { 351 device_printf(sc->dev, 352 "TX packet needs too many DMA segments, dropping...\n"); 353 m_freem(m); 354 return 0; 355 } 356 if (error != 0) 357 return 0; 358 359 segs = sc->tx.buf_map[index].map->dm_segs; 360 nsegs = sc->tx.buf_map[index].map->dm_nsegs; 361 362 flags = TX_FIR_DESC; 363 if ((m->m_pkthdr.csum_flags & M_CSUM_IPv4) != 0) { 364 if ((m->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) != 0) 365 csum_flags = TX_CHECKSUM_CTL_FULL; 366 else 367 csum_flags = TX_CHECKSUM_CTL_IP; 368 flags |= (csum_flags << TX_CHECKSUM_CTL_SHIFT); 369 } 370 371 for (cur = index, i = 0; i < nsegs; i++) { 372 sc->tx.buf_map[cur].mbuf = (i == 0 ? m : NULL); 373 if (i == nsegs - 1) 374 flags |= TX_LAST_DESC | TX_INT_CTL; 375 376 sunxi_emac_setup_txdesc(sc, cur, flags, segs[i].ds_addr, 377 segs[i].ds_len); 378 flags &= ~TX_FIR_DESC; 379 cur = TX_NEXT(cur); 380 } 381 382 bus_dmamap_sync(sc->tx.buf_tag, sc->tx.buf_map[index].map, 383 0, sc->tx.buf_map[index].map->dm_mapsize, BUS_DMASYNC_PREWRITE); 384 385 return nsegs; 386 } 387 388 static void 389 sunxi_emac_setup_rxdesc(struct sunxi_emac_softc *sc, int index, 390 bus_addr_t paddr) 391 { 392 uint32_t status, size; 393 394 status = RX_DESC_CTL; 395 size = MCLBYTES - 1; 396 397 sc->rx.desc_ring[index].addr = htole32((uint32_t)paddr); 398 sc->rx.desc_ring[index].size = htole32(size); 399 sc->rx.desc_ring[index].next = 400 htole32(sc->rx.desc_ring_paddr + DESC_OFF(RX_NEXT(index))); 401 sc->rx.desc_ring[index].status = htole32(status); 402 } 403 404 static int 405 sunxi_emac_setup_rxbuf(struct sunxi_emac_softc *sc, int index, struct mbuf *m) 406 { 407 int error; 408 409 m_adj(m, ETHER_ALIGN); 410 411 error = bus_dmamap_load_mbuf(sc->rx.buf_tag, 412 sc->rx.buf_map[index].map, m, BUS_DMA_READ | BUS_DMA_NOWAIT); 413 if (error != 0) 414 return error; 415 416 bus_dmamap_sync(sc->rx.buf_tag, sc->rx.buf_map[index].map, 417 0, sc->rx.buf_map[index].map->dm_mapsize, 418 BUS_DMASYNC_PREREAD); 419 420 sc->rx.buf_map[index].mbuf = m; 421 sunxi_emac_setup_rxdesc(sc, index, 422 sc->rx.buf_map[index].map->dm_segs[0].ds_addr); 423 424 return 0; 425 } 426 427 static struct mbuf * 428 sunxi_emac_alloc_mbufcl(struct sunxi_emac_softc *sc) 429 { 430 struct mbuf *m; 431 432 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 433 if (m != NULL) 434 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 435 436 return m; 437 } 438 439 static void 440 sunxi_emac_start_locked(struct sunxi_emac_softc *sc) 441 { 442 struct ifnet *ifp = &sc->ec.ec_if; 443 struct mbuf *m; 444 uint32_t val; 445 int cnt, nsegs, start; 446 447 EMAC_ASSERT_LOCKED(sc); 448 449 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 450 return; 451 452 for (cnt = 0, start = sc->tx.cur; ; cnt++) { 453 if (sc->tx.queued >= TX_DESC_COUNT - TX_MAX_SEGS) { 454 ifp->if_flags |= IFF_OACTIVE; 455 break; 456 } 457 458 IFQ_POLL(&ifp->if_snd, m); 459 if (m == NULL) 460 break; 461 462 nsegs = sunxi_emac_setup_txbuf(sc, sc->tx.cur, m); 463 if (nsegs == 0) { 464 ifp->if_flags |= IFF_OACTIVE; 465 break; 466 } 467 IFQ_DEQUEUE(&ifp->if_snd, m); 468 bpf_mtap(ifp, m, BPF_D_OUT); 469 470 sc->tx.cur = TX_SKIP(sc->tx.cur, nsegs); 471 } 472 473 if (cnt != 0) { 474 sunxi_emac_dma_sync(sc, sc->tx.desc_tag, sc->tx.desc_map, 475 start, sc->tx.cur, TX_DESC_COUNT, 476 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 477 478 /* Start and run TX DMA */ 479 val = RD4(sc, EMAC_TX_CTL_1); 480 WR4(sc, EMAC_TX_CTL_1, val | TX_DMA_START); 481 } 482 } 483 484 static void 485 sunxi_emac_start(struct ifnet *ifp) 486 { 487 struct sunxi_emac_softc *sc = ifp->if_softc; 488 489 EMAC_LOCK(sc); 490 sunxi_emac_start_locked(sc); 491 EMAC_UNLOCK(sc); 492 } 493 494 static void 495 sunxi_emac_tick(void *softc) 496 { 497 struct sunxi_emac_softc *sc = softc; 498 struct mii_data *mii = &sc->mii; 499 #ifndef EMAC_MPSAFE 500 int s = splnet(); 501 #endif 502 503 EMAC_LOCK(sc); 504 mii_tick(mii); 505 callout_schedule(&sc->stat_ch, hz); 506 EMAC_UNLOCK(sc); 507 508 #ifndef EMAC_MPSAFE 509 splx(s); 510 #endif 511 } 512 513 /* Bit Reversal - http://aggregate.org/MAGIC/#Bit%20Reversal */ 514 static uint32_t 515 bitrev32(uint32_t x) 516 { 517 x = (((x & 0xaaaaaaaa) >> 1) | ((x & 0x55555555) << 1)); 518 x = (((x & 0xcccccccc) >> 2) | ((x & 0x33333333) << 2)); 519 x = (((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4)); 520 x = (((x & 0xff00ff00) >> 8) | ((x & 0x00ff00ff) << 8)); 521 522 return (x >> 16) | (x << 16); 523 } 524 525 static void 526 sunxi_emac_setup_rxfilter(struct sunxi_emac_softc *sc) 527 { 528 struct ethercom *ec = &sc->ec; 529 struct ifnet *ifp = &ec->ec_if; 530 uint32_t val, crc, hashreg, hashbit, hash[2], machi, maclo; 531 struct ether_multi *enm; 532 struct ether_multistep step; 533 const uint8_t *eaddr; 534 535 EMAC_ASSERT_LOCKED(sc); 536 537 val = 0; 538 hash[0] = hash[1] = 0; 539 540 if ((ifp->if_flags & IFF_PROMISC) != 0) 541 val |= DIS_ADDR_FILTER; 542 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 543 val |= RX_ALL_MULTICAST; 544 hash[0] = hash[1] = ~0; 545 } else { 546 val |= HASH_MULTICAST; 547 ETHER_LOCK(ec); 548 ETHER_FIRST_MULTI(step, ec, enm); 549 while (enm != NULL) { 550 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 551 crc &= 0x7f; 552 crc = bitrev32(~crc) >> 26; 553 hashreg = (crc >> 5); 554 hashbit = (crc & 0x1f); 555 hash[hashreg] |= (1 << hashbit); 556 ETHER_NEXT_MULTI(step, enm); 557 } 558 ETHER_UNLOCK(ec); 559 } 560 561 /* Write our unicast address */ 562 eaddr = CLLADDR(ifp->if_sadl); 563 machi = (eaddr[5] << 8) | eaddr[4]; 564 maclo = (eaddr[3] << 24) | (eaddr[2] << 16) | (eaddr[1] << 8) | 565 (eaddr[0] << 0); 566 WR4(sc, EMAC_ADDR_HIGH(0), machi); 567 WR4(sc, EMAC_ADDR_LOW(0), maclo); 568 569 /* Multicast hash filters */ 570 WR4(sc, EMAC_RX_HASH_0, hash[1]); 571 WR4(sc, EMAC_RX_HASH_1, hash[0]); 572 573 /* RX frame filter config */ 574 WR4(sc, EMAC_RX_FRM_FLT, val); 575 } 576 577 static void 578 sunxi_emac_enable_intr(struct sunxi_emac_softc *sc) 579 { 580 /* Enable interrupts */ 581 WR4(sc, EMAC_INT_EN, RX_INT_EN | TX_INT_EN | TX_BUF_UA_INT_EN); 582 } 583 584 static void 585 sunxi_emac_disable_intr(struct sunxi_emac_softc *sc) 586 { 587 /* Disable interrupts */ 588 WR4(sc, EMAC_INT_EN, 0); 589 } 590 591 #ifdef SUNXI_EMAC_DEBUG 592 static void 593 sunxi_emac_dump_regs(struct sunxi_emac_softc *sc) 594 { 595 static const struct { 596 const char *name; 597 u_int reg; 598 } regs[] = { 599 { "BASIC_CTL_0", EMAC_BASIC_CTL_0 }, 600 { "BASIC_CTL_1", EMAC_BASIC_CTL_1 }, 601 { "INT_STA", EMAC_INT_STA }, 602 { "INT_EN", EMAC_INT_EN }, 603 { "TX_CTL_0", EMAC_TX_CTL_0 }, 604 { "TX_CTL_1", EMAC_TX_CTL_1 }, 605 { "TX_FLOW_CTL", EMAC_TX_FLOW_CTL }, 606 { "TX_DMA_LIST", EMAC_TX_DMA_LIST }, 607 { "RX_CTL_0", EMAC_RX_CTL_0 }, 608 { "RX_CTL_1", EMAC_RX_CTL_1 }, 609 { "RX_DMA_LIST", EMAC_RX_DMA_LIST }, 610 { "RX_FRM_FLT", EMAC_RX_FRM_FLT }, 611 { "RX_HASH_0", EMAC_RX_HASH_0 }, 612 { "RX_HASH_1", EMAC_RX_HASH_1 }, 613 { "MII_CMD", EMAC_MII_CMD }, 614 { "ADDR_HIGH0", EMAC_ADDR_HIGH(0) }, 615 { "ADDR_LOW0", EMAC_ADDR_LOW(0) }, 616 { "TX_DMA_STA", EMAC_TX_DMA_STA }, 617 { "TX_DMA_CUR_DESC", EMAC_TX_DMA_CUR_DESC }, 618 { "TX_DMA_CUR_BUF", EMAC_TX_DMA_CUR_BUF }, 619 { "RX_DMA_STA", EMAC_RX_DMA_STA }, 620 { "RX_DMA_CUR_DESC", EMAC_RX_DMA_CUR_DESC }, 621 { "RX_DMA_CUR_BUF", EMAC_RX_DMA_CUR_BUF }, 622 { "RGMII_STA", EMAC_RGMII_STA }, 623 }; 624 u_int n; 625 626 for (n = 0; n < __arraycount(regs); n++) 627 device_printf(sc->dev, " %-20s %08x\n", regs[n].name, 628 RD4(sc, regs[n].reg)); 629 } 630 #endif 631 632 static int 633 sunxi_emac_reset(struct sunxi_emac_softc *sc) 634 { 635 int retry; 636 637 /* Soft reset all registers and logic */ 638 WR4(sc, EMAC_BASIC_CTL_1, BASIC_CTL_SOFT_RST); 639 640 /* Wait for soft reset bit to self-clear */ 641 for (retry = SOFT_RST_RETRY; retry > 0; retry--) { 642 if ((RD4(sc, EMAC_BASIC_CTL_1) & BASIC_CTL_SOFT_RST) == 0) 643 break; 644 delay(10); 645 } 646 if (retry == 0) { 647 aprint_debug_dev(sc->dev, "soft reset timed out\n"); 648 #ifdef SUNXI_EMAC_DEBUG 649 sunxi_emac_dump_regs(sc); 650 #endif 651 return ETIMEDOUT; 652 } 653 654 return 0; 655 } 656 657 static int 658 sunxi_emac_init_locked(struct sunxi_emac_softc *sc) 659 { 660 struct ifnet *ifp = &sc->ec.ec_if; 661 struct mii_data *mii = &sc->mii; 662 uint32_t val; 663 664 EMAC_ASSERT_LOCKED(sc); 665 666 if ((ifp->if_flags & IFF_RUNNING) != 0) 667 return 0; 668 669 /* Soft reset EMAC core */ 670 sunxi_emac_reset(sc); 671 672 /* Write transmit and receive descriptor base address registers */ 673 WR4(sc, EMAC_TX_DMA_LIST, sc->tx.desc_ring_paddr); 674 WR4(sc, EMAC_RX_DMA_LIST, sc->rx.desc_ring_paddr); 675 676 sunxi_emac_setup_rxfilter(sc); 677 678 /* Configure DMA burst length and priorities */ 679 val = sunxi_emac_burst_len << BASIC_CTL_BURST_LEN_SHIFT; 680 if (sunxi_emac_rx_tx_pri) 681 val |= BASIC_CTL_RX_TX_PRI; 682 WR4(sc, EMAC_BASIC_CTL_1, val); 683 684 /* Enable interrupts */ 685 sunxi_emac_enable_intr(sc); 686 687 /* Enable transmit DMA */ 688 val = RD4(sc, EMAC_TX_CTL_1); 689 WR4(sc, EMAC_TX_CTL_1, val | TX_DMA_EN | TX_MD | TX_NEXT_FRAME); 690 691 /* Enable receive DMA */ 692 val = RD4(sc, EMAC_RX_CTL_1); 693 WR4(sc, EMAC_RX_CTL_1, val | RX_DMA_EN | RX_MD); 694 695 /* Enable transmitter */ 696 val = RD4(sc, EMAC_TX_CTL_0); 697 WR4(sc, EMAC_TX_CTL_0, val | TX_EN); 698 699 /* Enable receiver */ 700 val = RD4(sc, EMAC_RX_CTL_0); 701 WR4(sc, EMAC_RX_CTL_0, val | RX_EN | CHECK_CRC); 702 703 ifp->if_flags |= IFF_RUNNING; 704 ifp->if_flags &= ~IFF_OACTIVE; 705 706 mii_mediachg(mii); 707 callout_schedule(&sc->stat_ch, hz); 708 709 return 0; 710 } 711 712 static int 713 sunxi_emac_init(struct ifnet *ifp) 714 { 715 struct sunxi_emac_softc *sc = ifp->if_softc; 716 int error; 717 718 EMAC_LOCK(sc); 719 error = sunxi_emac_init_locked(sc); 720 EMAC_UNLOCK(sc); 721 722 return error; 723 } 724 725 static void 726 sunxi_emac_stop_locked(struct sunxi_emac_softc *sc, int disable) 727 { 728 struct ifnet *ifp = &sc->ec.ec_if; 729 uint32_t val; 730 731 EMAC_ASSERT_LOCKED(sc); 732 733 callout_stop(&sc->stat_ch); 734 735 mii_down(&sc->mii); 736 737 /* Stop transmit DMA and flush data in the TX FIFO */ 738 val = RD4(sc, EMAC_TX_CTL_1); 739 val &= ~TX_DMA_EN; 740 val |= FLUSH_TX_FIFO; 741 WR4(sc, EMAC_TX_CTL_1, val); 742 743 /* Disable transmitter */ 744 val = RD4(sc, EMAC_TX_CTL_0); 745 WR4(sc, EMAC_TX_CTL_0, val & ~TX_EN); 746 747 /* Disable receiver */ 748 val = RD4(sc, EMAC_RX_CTL_0); 749 WR4(sc, EMAC_RX_CTL_0, val & ~RX_EN); 750 751 /* Disable interrupts */ 752 sunxi_emac_disable_intr(sc); 753 754 /* Disable transmit DMA */ 755 val = RD4(sc, EMAC_TX_CTL_1); 756 WR4(sc, EMAC_TX_CTL_1, val & ~TX_DMA_EN); 757 758 /* Disable receive DMA */ 759 val = RD4(sc, EMAC_RX_CTL_1); 760 WR4(sc, EMAC_RX_CTL_1, val & ~RX_DMA_EN); 761 762 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 763 } 764 765 static void 766 sunxi_emac_stop(struct ifnet *ifp, int disable) 767 { 768 struct sunxi_emac_softc * const sc = ifp->if_softc; 769 770 EMAC_LOCK(sc); 771 sunxi_emac_stop_locked(sc, disable); 772 EMAC_UNLOCK(sc); 773 } 774 775 static int 776 sunxi_emac_rxintr(struct sunxi_emac_softc *sc) 777 { 778 struct ifnet *ifp = &sc->ec.ec_if; 779 int error, index, len, npkt; 780 struct mbuf *m, *m0; 781 uint32_t status; 782 783 npkt = 0; 784 785 for (index = sc->rx.cur; ; index = RX_NEXT(index)) { 786 sunxi_emac_dma_sync(sc, sc->rx.desc_tag, sc->rx.desc_map, 787 index, index + 1, RX_DESC_COUNT, 788 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 789 790 status = le32toh(sc->rx.desc_ring[index].status); 791 if ((status & RX_DESC_CTL) != 0) 792 break; 793 794 bus_dmamap_sync(sc->rx.buf_tag, sc->rx.buf_map[index].map, 795 0, sc->rx.buf_map[index].map->dm_mapsize, 796 BUS_DMASYNC_POSTREAD); 797 bus_dmamap_unload(sc->rx.buf_tag, sc->rx.buf_map[index].map); 798 799 len = (status & RX_FRM_LEN) >> RX_FRM_LEN_SHIFT; 800 if (len != 0) { 801 m = sc->rx.buf_map[index].mbuf; 802 m_set_rcvif(m, ifp); 803 m->m_flags |= M_HASFCS; 804 m->m_pkthdr.len = len; 805 m->m_len = len; 806 m->m_nextpkt = NULL; 807 808 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) != 0 && 809 (status & RX_FRM_TYPE) != 0) { 810 m->m_pkthdr.csum_flags = M_CSUM_IPv4 | 811 M_CSUM_TCPv4 | M_CSUM_UDPv4; 812 if ((status & RX_HEADER_ERR) != 0) 813 m->m_pkthdr.csum_flags |= 814 M_CSUM_IPv4_BAD; 815 if ((status & RX_PAYLOAD_ERR) != 0) 816 m->m_pkthdr.csum_flags |= 817 M_CSUM_TCP_UDP_BAD; 818 } 819 820 ++npkt; 821 822 if_percpuq_enqueue(ifp->if_percpuq, m); 823 } 824 825 if ((m0 = sunxi_emac_alloc_mbufcl(sc)) != NULL) { 826 error = sunxi_emac_setup_rxbuf(sc, index, m0); 827 if (error != 0) { 828 /* XXX hole in RX ring */ 829 } 830 } else 831 if_statinc(ifp, if_ierrors); 832 833 sunxi_emac_dma_sync(sc, sc->rx.desc_tag, sc->rx.desc_map, 834 index, index + 1, 835 RX_DESC_COUNT, BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 836 } 837 838 sc->rx.cur = index; 839 840 return npkt; 841 } 842 843 static void 844 sunxi_emac_txintr(struct sunxi_emac_softc *sc) 845 { 846 struct ifnet *ifp = &sc->ec.ec_if; 847 struct sunxi_emac_bufmap *bmap; 848 struct sunxi_emac_desc *desc; 849 uint32_t status; 850 int i; 851 852 EMAC_ASSERT_LOCKED(sc); 853 854 for (i = sc->tx.next; sc->tx.queued > 0; i = TX_NEXT(i)) { 855 KASSERT(sc->tx.queued > 0 && sc->tx.queued <= TX_DESC_COUNT); 856 sunxi_emac_dma_sync(sc, sc->tx.desc_tag, sc->tx.desc_map, 857 i, i + 1, TX_DESC_COUNT, 858 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 859 desc = &sc->tx.desc_ring[i]; 860 status = le32toh(desc->status); 861 if ((status & TX_DESC_CTL) != 0) 862 break; 863 bmap = &sc->tx.buf_map[i]; 864 if (bmap->mbuf != NULL) { 865 bus_dmamap_sync(sc->tx.buf_tag, bmap->map, 866 0, bmap->map->dm_mapsize, 867 BUS_DMASYNC_POSTWRITE); 868 bus_dmamap_unload(sc->tx.buf_tag, bmap->map); 869 m_freem(bmap->mbuf); 870 bmap->mbuf = NULL; 871 } 872 873 sunxi_emac_setup_txdesc(sc, i, 0, 0, 0); 874 sunxi_emac_dma_sync(sc, sc->tx.desc_tag, sc->tx.desc_map, 875 i, i + 1, TX_DESC_COUNT, 876 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 877 878 ifp->if_flags &= ~IFF_OACTIVE; 879 if_statinc(ifp, if_opackets); 880 } 881 882 sc->tx.next = i; 883 } 884 885 static int 886 sunxi_emac_intr(void *arg) 887 { 888 struct sunxi_emac_softc *sc = arg; 889 struct ifnet *ifp = &sc->ec.ec_if; 890 uint32_t val; 891 892 EMAC_LOCK(sc); 893 894 val = RD4(sc, EMAC_INT_STA); 895 WR4(sc, EMAC_INT_STA, val); 896 897 if (val & RX_INT) 898 sunxi_emac_rxintr(sc); 899 900 if (val & (TX_INT | TX_BUF_UA_INT)) { 901 sunxi_emac_txintr(sc); 902 if_schedule_deferred_start(ifp); 903 } 904 905 EMAC_UNLOCK(sc); 906 907 return 1; 908 } 909 910 static int 911 sunxi_emac_ioctl(struct ifnet *ifp, u_long cmd, void *data) 912 { 913 struct sunxi_emac_softc *sc = ifp->if_softc; 914 int error, s; 915 916 #ifndef EMAC_MPSAFE 917 s = splnet(); 918 #endif 919 920 switch (cmd) { 921 default: 922 #ifdef EMAC_MPSAFE 923 s = splnet(); 924 #endif 925 error = ether_ioctl(ifp, cmd, data); 926 #ifdef EMAC_MPSAFE 927 splx(s); 928 #endif 929 if (error != ENETRESET) 930 break; 931 932 error = 0; 933 934 if (cmd == SIOCSIFCAP) 935 error = (*ifp->if_init)(ifp); 936 else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 937 ; 938 else if ((ifp->if_flags & IFF_RUNNING) != 0) { 939 EMAC_LOCK(sc); 940 sunxi_emac_setup_rxfilter(sc); 941 EMAC_UNLOCK(sc); 942 } 943 break; 944 } 945 946 #ifndef EMAC_MPSAFE 947 splx(s); 948 #endif 949 950 return error; 951 } 952 953 static bool 954 sunxi_emac_has_internal_phy(struct sunxi_emac_softc *sc) 955 { 956 const char * mdio_internal_compat[] = { 957 "allwinner,sun8i-h3-mdio-internal", 958 NULL 959 }; 960 int phy; 961 962 /* Non-standard property, for compatible with old dts files */ 963 if (of_hasprop(sc->phandle, "allwinner,use-internal-phy")) 964 return true; 965 966 phy = fdtbus_get_phandle(sc->phandle, "phy-handle"); 967 if (phy == -1) 968 return false; 969 970 /* For internal PHY, check compatible string of parent node */ 971 return of_compatible(OF_parent(phy), mdio_internal_compat) >= 0; 972 } 973 974 static int 975 sunxi_emac_setup_phy(struct sunxi_emac_softc *sc) 976 { 977 uint32_t reg, tx_delay, rx_delay; 978 const char *phy_type; 979 980 phy_type = fdtbus_get_string(sc->phandle, "phy-mode"); 981 if (phy_type == NULL) 982 return 0; 983 984 aprint_debug_dev(sc->dev, "PHY type: %s\n", phy_type); 985 986 syscon_lock(sc->syscon); 987 reg = syscon_read_4(sc->syscon, EMAC_CLK_REG); 988 989 reg &= ~(EMAC_CLK_PIT | EMAC_CLK_SRC | EMAC_CLK_RMII_EN); 990 if (strcmp(phy_type, "rgmii") == 0) 991 reg |= EMAC_CLK_PIT_RGMII | EMAC_CLK_SRC_RGMII; 992 else if (strcmp(phy_type, "rmii") == 0) 993 reg |= EMAC_CLK_RMII_EN; 994 else 995 reg |= EMAC_CLK_PIT_MII | EMAC_CLK_SRC_MII; 996 997 if (of_getprop_uint32(sc->phandle, "allwinner,tx-delay-ps", 998 &tx_delay) == 0) { 999 reg &= ~EMAC_CLK_ETXDC; 1000 reg |= ((tx_delay / 100) << EMAC_CLK_ETXDC_SHIFT); 1001 } else if (of_getprop_uint32(sc->phandle, "tx-delay", &tx_delay) == 0) { 1002 reg &= ~EMAC_CLK_ETXDC; 1003 reg |= (tx_delay << EMAC_CLK_ETXDC_SHIFT); 1004 } 1005 if (of_getprop_uint32(sc->phandle, "allwinner,rx-delay-ps", 1006 &rx_delay) == 0) { 1007 reg &= ~EMAC_CLK_ERXDC; 1008 reg |= ((rx_delay / 100) << EMAC_CLK_ERXDC_SHIFT); 1009 } else if (of_getprop_uint32(sc->phandle, "rx-delay", &rx_delay) == 0) { 1010 reg &= ~EMAC_CLK_ERXDC; 1011 reg |= (rx_delay << EMAC_CLK_ERXDC_SHIFT); 1012 } 1013 1014 if (sc->type == EMAC_H3 || sc->type == EMAC_H6) { 1015 if (sunxi_emac_has_internal_phy(sc)) { 1016 reg |= EMAC_CLK_EPHY_SELECT; 1017 reg &= ~EMAC_CLK_EPHY_SHUTDOWN; 1018 if (of_hasprop(sc->phandle, 1019 "allwinner,leds-active-low")) 1020 reg |= EMAC_CLK_EPHY_LED_POL; 1021 else 1022 reg &= ~EMAC_CLK_EPHY_LED_POL; 1023 1024 /* Set internal PHY addr to 1 */ 1025 reg &= ~EMAC_CLK_EPHY_ADDR; 1026 reg |= (1 << EMAC_CLK_EPHY_ADDR_SHIFT); 1027 } else { 1028 reg &= ~EMAC_CLK_EPHY_SELECT; 1029 } 1030 } 1031 1032 aprint_debug_dev(sc->dev, "EMAC clock: 0x%08x\n", reg); 1033 1034 syscon_write_4(sc->syscon, EMAC_CLK_REG, reg); 1035 syscon_unlock(sc->syscon); 1036 1037 return 0; 1038 } 1039 1040 static int 1041 sunxi_emac_setup_resources(struct sunxi_emac_softc *sc) 1042 { 1043 u_int freq; 1044 int error, div; 1045 1046 /* Configure PHY for MII or RGMII mode */ 1047 if (sunxi_emac_setup_phy(sc) != 0) 1048 return ENXIO; 1049 1050 /* Enable clocks */ 1051 error = clk_enable(sc->clk_ahb); 1052 if (error != 0) { 1053 aprint_error_dev(sc->dev, "cannot enable ahb clock\n"); 1054 return error; 1055 } 1056 1057 if (sc->clk_ephy != NULL) { 1058 error = clk_enable(sc->clk_ephy); 1059 if (error != 0) { 1060 aprint_error_dev(sc->dev, "cannot enable ephy clock\n"); 1061 return error; 1062 } 1063 } 1064 1065 /* De-assert reset */ 1066 error = fdtbus_reset_deassert(sc->rst_ahb); 1067 if (error != 0) { 1068 aprint_error_dev(sc->dev, "cannot de-assert ahb reset\n"); 1069 return error; 1070 } 1071 if (sc->rst_ephy != NULL) { 1072 error = fdtbus_reset_deassert(sc->rst_ephy); 1073 if (error != 0) { 1074 aprint_error_dev(sc->dev, 1075 "cannot de-assert ephy reset\n"); 1076 return error; 1077 } 1078 } 1079 1080 /* Enable PHY regulator if applicable */ 1081 if (sc->reg_phy != NULL) { 1082 error = fdtbus_regulator_enable(sc->reg_phy); 1083 if (error != 0) { 1084 aprint_error_dev(sc->dev, 1085 "cannot enable PHY regulator\n"); 1086 return error; 1087 } 1088 } 1089 1090 /* Determine MDC clock divide ratio based on AHB clock */ 1091 freq = clk_get_rate(sc->clk_ahb); 1092 if (freq == 0) { 1093 aprint_error_dev(sc->dev, "cannot get AHB clock frequency\n"); 1094 return ENXIO; 1095 } 1096 div = freq / MDIO_FREQ; 1097 if (div <= 16) 1098 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_16; 1099 else if (div <= 32) 1100 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_32; 1101 else if (div <= 64) 1102 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_64; 1103 else if (div <= 128) 1104 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_128; 1105 else { 1106 aprint_error_dev(sc->dev, 1107 "cannot determine MDC clock divide ratio\n"); 1108 return ENXIO; 1109 } 1110 1111 aprint_debug_dev(sc->dev, "AHB frequency %u Hz, MDC div: 0x%x\n", 1112 freq, sc->mdc_div_ratio_m); 1113 1114 return 0; 1115 } 1116 1117 static void 1118 sunxi_emac_get_eaddr(struct sunxi_emac_softc *sc, uint8_t *eaddr) 1119 { 1120 uint32_t maclo, machi; 1121 #if notyet 1122 u_char rootkey[16]; 1123 #endif 1124 1125 machi = RD4(sc, EMAC_ADDR_HIGH(0)) & 0xffff; 1126 maclo = RD4(sc, EMAC_ADDR_LOW(0)); 1127 1128 if (maclo == 0xffffffff && machi == 0xffff) { 1129 #if notyet 1130 /* MAC address in hardware is invalid, create one */ 1131 if (aw_sid_get_rootkey(rootkey) == 0 && 1132 (rootkey[3] | rootkey[12] | rootkey[13] | rootkey[14] | 1133 rootkey[15]) != 0) { 1134 /* MAC address is derived from the root key in SID */ 1135 maclo = (rootkey[13] << 24) | (rootkey[12] << 16) | 1136 (rootkey[3] << 8) | 0x02; 1137 machi = (rootkey[15] << 8) | rootkey[14]; 1138 } else { 1139 #endif 1140 /* Create one */ 1141 maclo = 0x00f2 | (cprng_strong32() & 0xffff0000); 1142 machi = cprng_strong32() & 0xffff; 1143 #if notyet 1144 } 1145 #endif 1146 } 1147 1148 eaddr[0] = maclo & 0xff; 1149 eaddr[1] = (maclo >> 8) & 0xff; 1150 eaddr[2] = (maclo >> 16) & 0xff; 1151 eaddr[3] = (maclo >> 24) & 0xff; 1152 eaddr[4] = machi & 0xff; 1153 eaddr[5] = (machi >> 8) & 0xff; 1154 } 1155 1156 static int 1157 sunxi_emac_phy_reset(struct sunxi_emac_softc *sc) 1158 { 1159 uint32_t delay_prop[3]; 1160 int pin_value; 1161 1162 if (sc->pin_reset == NULL) 1163 return 0; 1164 1165 if (OF_getprop(sc->phandle, "allwinner,reset-delays-us", delay_prop, 1166 sizeof(delay_prop)) <= 0) 1167 return ENXIO; 1168 1169 pin_value = of_hasprop(sc->phandle, "allwinner,reset-active-low"); 1170 1171 fdtbus_gpio_write(sc->pin_reset, pin_value); 1172 delay(htole32(delay_prop[0])); 1173 fdtbus_gpio_write(sc->pin_reset, !pin_value); 1174 delay(htole32(delay_prop[1])); 1175 fdtbus_gpio_write(sc->pin_reset, pin_value); 1176 delay(htole32(delay_prop[2])); 1177 1178 return 0; 1179 } 1180 1181 static int 1182 sunxi_emac_setup_dma(struct sunxi_emac_softc *sc) 1183 { 1184 struct mbuf *m; 1185 int error, nsegs, i; 1186 1187 /* Setup TX ring */ 1188 sc->tx.buf_tag = sc->tx.desc_tag = sc->dmat; 1189 error = bus_dmamap_create(sc->dmat, TX_DESC_SIZE, 1, TX_DESC_SIZE, 0, 1190 BUS_DMA_WAITOK, &sc->tx.desc_map); 1191 if (error) 1192 return error; 1193 error = bus_dmamem_alloc(sc->dmat, TX_DESC_SIZE, DESC_ALIGN, 0, 1194 &sc->tx.desc_dmaseg, 1, &nsegs, BUS_DMA_WAITOK); 1195 if (error) 1196 return error; 1197 error = bus_dmamem_map(sc->dmat, &sc->tx.desc_dmaseg, nsegs, 1198 TX_DESC_SIZE, (void *)&sc->tx.desc_ring, 1199 BUS_DMA_WAITOK); 1200 if (error) 1201 return error; 1202 error = bus_dmamap_load(sc->dmat, sc->tx.desc_map, sc->tx.desc_ring, 1203 TX_DESC_SIZE, NULL, BUS_DMA_WAITOK); 1204 if (error) 1205 return error; 1206 sc->tx.desc_ring_paddr = sc->tx.desc_map->dm_segs[0].ds_addr; 1207 1208 memset(sc->tx.desc_ring, 0, TX_DESC_SIZE); 1209 bus_dmamap_sync(sc->dmat, sc->tx.desc_map, 0, TX_DESC_SIZE, 1210 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1211 1212 for (i = 0; i < TX_DESC_COUNT; i++) 1213 sc->tx.desc_ring[i].next = 1214 htole32(sc->tx.desc_ring_paddr + DESC_OFF(TX_NEXT(i))); 1215 1216 sc->tx.queued = TX_DESC_COUNT; 1217 for (i = 0; i < TX_DESC_COUNT; i++) { 1218 error = bus_dmamap_create(sc->tx.buf_tag, MCLBYTES, 1219 TX_MAX_SEGS, MCLBYTES, 0, BUS_DMA_WAITOK, 1220 &sc->tx.buf_map[i].map); 1221 if (error != 0) { 1222 device_printf(sc->dev, "cannot create TX buffer map\n"); 1223 return error; 1224 } 1225 sunxi_emac_setup_txdesc(sc, i, 0, 0, 0); 1226 } 1227 1228 /* Setup RX ring */ 1229 sc->rx.buf_tag = sc->rx.desc_tag = sc->dmat; 1230 error = bus_dmamap_create(sc->dmat, RX_DESC_SIZE, 1, RX_DESC_SIZE, 0, 1231 BUS_DMA_WAITOK, &sc->rx.desc_map); 1232 if (error) 1233 return error; 1234 error = bus_dmamem_alloc(sc->dmat, RX_DESC_SIZE, DESC_ALIGN, 0, 1235 &sc->rx.desc_dmaseg, 1, &nsegs, BUS_DMA_WAITOK); 1236 if (error) 1237 return error; 1238 error = bus_dmamem_map(sc->dmat, &sc->rx.desc_dmaseg, nsegs, 1239 RX_DESC_SIZE, (void *)&sc->rx.desc_ring, 1240 BUS_DMA_WAITOK); 1241 if (error) 1242 return error; 1243 error = bus_dmamap_load(sc->dmat, sc->rx.desc_map, sc->rx.desc_ring, 1244 RX_DESC_SIZE, NULL, BUS_DMA_WAITOK); 1245 if (error) 1246 return error; 1247 sc->rx.desc_ring_paddr = sc->rx.desc_map->dm_segs[0].ds_addr; 1248 1249 memset(sc->rx.desc_ring, 0, RX_DESC_SIZE); 1250 1251 for (i = 0; i < RX_DESC_COUNT; i++) { 1252 error = bus_dmamap_create(sc->rx.buf_tag, MCLBYTES, 1253 RX_DESC_COUNT, MCLBYTES, 0, BUS_DMA_WAITOK, 1254 &sc->rx.buf_map[i].map); 1255 if (error != 0) { 1256 device_printf(sc->dev, "cannot create RX buffer map\n"); 1257 return error; 1258 } 1259 if ((m = sunxi_emac_alloc_mbufcl(sc)) == NULL) { 1260 device_printf(sc->dev, "cannot allocate RX mbuf\n"); 1261 return ENOMEM; 1262 } 1263 error = sunxi_emac_setup_rxbuf(sc, i, m); 1264 if (error != 0) { 1265 device_printf(sc->dev, "cannot create RX buffer\n"); 1266 return error; 1267 } 1268 } 1269 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map, 1270 0, sc->rx.desc_map->dm_mapsize, 1271 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1272 1273 return 0; 1274 } 1275 1276 static int 1277 sunxi_emac_get_resources(struct sunxi_emac_softc *sc) 1278 { 1279 const int phandle = sc->phandle; 1280 bus_addr_t addr, size; 1281 1282 /* Map EMAC registers */ 1283 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 1284 aprint_error_dev(sc->dev, "unable to get registers\n"); 1285 return ENXIO; 1286 } 1287 if (bus_space_map(sc->bst, addr, size, 0, &sc->bsh) != 0) { 1288 aprint_error_dev(sc->dev, "unable to map registers\n"); 1289 return ENXIO; 1290 } 1291 1292 /* Get SYSCON registers */ 1293 sc->syscon = fdtbus_syscon_acquire(phandle, "syscon"); 1294 if (sc->syscon == NULL) { 1295 aprint_error_dev(sc->dev, "unable to acquire syscon\n"); 1296 return ENXIO; 1297 } 1298 1299 /* The "ahb"/"stmmaceth" clock and reset is required */ 1300 if ((sc->clk_ahb = fdtbus_clock_get(phandle, "ahb")) == NULL && 1301 (sc->clk_ahb = fdtbus_clock_get(phandle, "stmmaceth")) == NULL) { 1302 aprint_error_dev(sc->dev, "unable to get clock\n"); 1303 return ENXIO; 1304 } 1305 if ((sc->rst_ahb = fdtbus_reset_get(phandle, "ahb")) == NULL && 1306 (sc->rst_ahb = fdtbus_reset_get(phandle, "stmmaceth")) == NULL) { 1307 aprint_error_dev(sc->dev, "unable to get reset\n"); 1308 return ENXIO; 1309 } 1310 1311 /* Internal PHY clock and reset are optional properties. */ 1312 sc->clk_ephy = fdtbus_clock_get(phandle, "ephy"); 1313 if (sc->clk_ephy == NULL) { 1314 int phy_phandle = fdtbus_get_phandle(phandle, "phy-handle"); 1315 if (phy_phandle != -1) 1316 sc->clk_ephy = fdtbus_clock_get_index(phy_phandle, 0); 1317 } 1318 sc->rst_ephy = fdtbus_reset_get(phandle, "ephy"); 1319 if (sc->rst_ephy == NULL) { 1320 int phy_phandle = fdtbus_get_phandle(phandle, "phy-handle"); 1321 if (phy_phandle != -1) 1322 sc->rst_ephy = fdtbus_reset_get_index(phy_phandle, 0); 1323 } 1324 1325 /* Regulator is optional */ 1326 sc->reg_phy = fdtbus_regulator_acquire(phandle, "phy-supply"); 1327 1328 /* Reset GPIO is optional */ 1329 sc->pin_reset = fdtbus_gpio_acquire(sc->phandle, 1330 "allwinner,reset-gpio", GPIO_PIN_OUTPUT); 1331 1332 return 0; 1333 } 1334 1335 static int 1336 sunxi_emac_get_phyid(struct sunxi_emac_softc *sc) 1337 { 1338 bus_addr_t addr; 1339 int phy_phandle; 1340 1341 phy_phandle = fdtbus_get_phandle(sc->phandle, "phy"); 1342 if (phy_phandle == -1) 1343 phy_phandle = fdtbus_get_phandle(sc->phandle, "phy-handle"); 1344 if (phy_phandle == -1) 1345 return MII_PHY_ANY; 1346 1347 if (fdtbus_get_reg(phy_phandle, 0, &addr, NULL) != 0) 1348 return MII_PHY_ANY; 1349 1350 return (int)addr; 1351 } 1352 1353 static int 1354 sunxi_emac_match(device_t parent, cfdata_t cf, void *aux) 1355 { 1356 struct fdt_attach_args * const faa = aux; 1357 1358 return of_match_compat_data(faa->faa_phandle, compat_data); 1359 } 1360 1361 static void 1362 sunxi_emac_attach(device_t parent, device_t self, void *aux) 1363 { 1364 struct fdt_attach_args * const faa = aux; 1365 struct sunxi_emac_softc * const sc = device_private(self); 1366 const int phandle = faa->faa_phandle; 1367 struct mii_data *mii = &sc->mii; 1368 struct ifnet *ifp = &sc->ec.ec_if; 1369 uint8_t eaddr[ETHER_ADDR_LEN]; 1370 char intrstr[128]; 1371 1372 sc->dev = self; 1373 sc->phandle = phandle; 1374 sc->bst = faa->faa_bst; 1375 sc->dmat = faa->faa_dmat; 1376 sc->type = of_search_compatible(phandle, compat_data)->data; 1377 sc->phy_id = sunxi_emac_get_phyid(sc); 1378 1379 aprint_naive("\n"); 1380 aprint_normal(": EMAC\n"); 1381 1382 if (sunxi_emac_get_resources(sc) != 0) { 1383 aprint_error_dev(self, 1384 "cannot allocate resources for device\n"); 1385 return; 1386 } 1387 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 1388 aprint_error_dev(self, "cannot decode interrupt\n"); 1389 return; 1390 } 1391 1392 mutex_init(&sc->mtx, MUTEX_DEFAULT, IPL_NET); 1393 callout_init(&sc->stat_ch, CALLOUT_FLAGS); 1394 callout_setfunc(&sc->stat_ch, sunxi_emac_tick, sc); 1395 1396 /* Setup clocks and regulators */ 1397 if (sunxi_emac_setup_resources(sc) != 0) 1398 return; 1399 1400 /* Read MAC address before resetting the chip */ 1401 sunxi_emac_get_eaddr(sc, eaddr); 1402 aprint_normal_dev(self, "Ethernet address %s\n", ether_sprintf(eaddr)); 1403 1404 /* Reset PHY if necessary */ 1405 if (sunxi_emac_phy_reset(sc) != 0) { 1406 aprint_error_dev(self, "failed to reset PHY\n"); 1407 return; 1408 } 1409 1410 /* Setup DMA descriptors */ 1411 if (sunxi_emac_setup_dma(sc) != 0) { 1412 aprint_error_dev(self, "failed to setup DMA descriptors\n"); 1413 return; 1414 } 1415 1416 /* Install interrupt handler */ 1417 sc->ih = fdtbus_intr_establish(phandle, 0, IPL_NET, 1418 FDT_INTR_FLAGS, sunxi_emac_intr, sc); 1419 if (sc->ih == NULL) { 1420 aprint_error_dev(self, "failed to establish interrupt on %s\n", 1421 intrstr); 1422 return; 1423 } 1424 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 1425 1426 /* Setup ethernet interface */ 1427 ifp->if_softc = sc; 1428 snprintf(ifp->if_xname, IFNAMSIZ, EMAC_IFNAME, device_unit(self)); 1429 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1430 #ifdef EMAC_MPSAFE 1431 ifp->if_extflags = IFEF_MPSAFE; 1432 #endif 1433 ifp->if_start = sunxi_emac_start; 1434 ifp->if_ioctl = sunxi_emac_ioctl; 1435 ifp->if_init = sunxi_emac_init; 1436 ifp->if_stop = sunxi_emac_stop; 1437 ifp->if_capabilities = IFCAP_CSUM_IPv4_Rx | 1438 IFCAP_CSUM_IPv4_Tx | 1439 IFCAP_CSUM_TCPv4_Rx | 1440 IFCAP_CSUM_TCPv4_Tx | 1441 IFCAP_CSUM_UDPv4_Rx | 1442 IFCAP_CSUM_UDPv4_Tx; 1443 ifp->if_capenable = ifp->if_capabilities; 1444 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 1445 IFQ_SET_READY(&ifp->if_snd); 1446 1447 /* 802.1Q VLAN-sized frames are supported */ 1448 sc->ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 1449 1450 /* Attach MII driver */ 1451 sc->ec.ec_mii = mii; 1452 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 1453 mii->mii_ifp = ifp; 1454 mii->mii_readreg = sunxi_emac_mii_readreg; 1455 mii->mii_writereg = sunxi_emac_mii_writereg; 1456 mii->mii_statchg = sunxi_emac_mii_statchg; 1457 mii_attach(self, mii, 0xffffffff, sc->phy_id, MII_OFFSET_ANY, 1458 MIIF_DOPAUSE); 1459 1460 if (LIST_EMPTY(&mii->mii_phys)) { 1461 aprint_error_dev(self, "no PHY found!\n"); 1462 return; 1463 } 1464 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 1465 1466 /* Attach interface */ 1467 if_attach(ifp); 1468 if_deferred_start_init(ifp, NULL); 1469 1470 /* Attach ethernet interface */ 1471 ether_ifattach(ifp, eaddr); 1472 } 1473 1474 CFATTACH_DECL_NEW(sunxi_emac, sizeof(struct sunxi_emac_softc), 1475 sunxi_emac_match, sunxi_emac_attach, NULL, NULL); 1476
Indexes created Mon Oct 20 16:09:52 GMT 2025