sunxi_emac.c revision 1.31
1 /* $NetBSD: sunxi_emac.c,v 1.31 2021/01/18 02:35:49 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2016-2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Allwinner Gigabit Ethernet MAC (EMAC) controller 31 */ 32 33 #include "opt_net_mpsafe.h" 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: sunxi_emac.c,v 1.31 2021/01/18 02:35:49 thorpej Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/bus.h> 40 #include <sys/device.h> 41 #include <sys/intr.h> 42 #include <sys/systm.h> 43 #include <sys/kernel.h> 44 #include <sys/mutex.h> 45 #include <sys/callout.h> 46 #include <sys/gpio.h> 47 #include <sys/cprng.h> 48 49 #include <net/if.h> 50 #include <net/if_dl.h> 51 #include <net/if_ether.h> 52 #include <net/if_media.h> 53 #include <net/bpf.h> 54 55 #include <dev/mii/miivar.h> 56 57 #include <dev/fdt/fdtvar.h> 58 #include <dev/fdt/syscon.h> 59 60 #include <arm/sunxi/sunxi_emac.h> 61 62 #ifdef NET_MPSAFE 63 #define EMAC_MPSAFE 1 64 #define CALLOUT_FLAGS CALLOUT_MPSAFE 65 #define FDT_INTR_FLAGS FDT_INTR_MPSAFE 66 #else 67 #define CALLOUT_FLAGS 0 68 #define FDT_INTR_FLAGS 0 69 #endif 70 71 #define EMAC_IFNAME "emac%d" 72 73 #define EMAC_LOCK(sc) mutex_enter(&(sc)->mtx) 74 #define EMAC_UNLOCK(sc) mutex_exit(&(sc)->mtx) 75 #define EMAC_ASSERT_LOCKED(sc) KASSERT(mutex_owned(&(sc)->mtx)) 76 77 #define DESC_ALIGN sizeof(struct sunxi_emac_desc) 78 #define TX_DESC_COUNT 1024 79 #define TX_DESC_SIZE (sizeof(struct sunxi_emac_desc) * TX_DESC_COUNT) 80 #define RX_DESC_COUNT 256 81 #define RX_DESC_SIZE (sizeof(struct sunxi_emac_desc) * RX_DESC_COUNT) 82 83 #define DESC_OFF(n) ((n) * sizeof(struct sunxi_emac_desc)) 84 #define TX_NEXT(n) (((n) + 1) & (TX_DESC_COUNT - 1)) 85 #define TX_SKIP(n, o) (((n) + (o)) & (TX_DESC_COUNT - 1)) 86 #define RX_NEXT(n) (((n) + 1) & (RX_DESC_COUNT - 1)) 87 88 #define TX_MAX_SEGS 128 89 90 #define SOFT_RST_RETRY 1000 91 #define MII_BUSY_RETRY 1000 92 #define MDIO_FREQ 2500000 93 94 #define BURST_LEN_DEFAULT 8 95 #define RX_TX_PRI_DEFAULT 0 96 #define PAUSE_TIME_DEFAULT 0x400 97 98 /* syscon EMAC clock register */ 99 #define EMAC_CLK_REG 0x30 100 #define EMAC_CLK_EPHY_ADDR (0x1f << 20) /* H3 */ 101 #define EMAC_CLK_EPHY_ADDR_SHIFT 20 102 #define EMAC_CLK_EPHY_LED_POL (1 << 17) /* H3 */ 103 #define EMAC_CLK_EPHY_SHUTDOWN (1 << 16) /* H3 */ 104 #define EMAC_CLK_EPHY_SELECT (1 << 15) /* H3 */ 105 #define EMAC_CLK_RMII_EN (1 << 13) 106 #define EMAC_CLK_ETXDC (0x7 << 10) 107 #define EMAC_CLK_ETXDC_SHIFT 10 108 #define EMAC_CLK_ERXDC (0x1f << 5) 109 #define EMAC_CLK_ERXDC_SHIFT 5 110 #define EMAC_CLK_PIT (0x1 << 2) 111 #define EMAC_CLK_PIT_MII (0 << 2) 112 #define EMAC_CLK_PIT_RGMII (1 << 2) 113 #define EMAC_CLK_SRC (0x3 << 0) 114 #define EMAC_CLK_SRC_MII (0 << 0) 115 #define EMAC_CLK_SRC_EXT_RGMII (1 << 0) 116 #define EMAC_CLK_SRC_RGMII (2 << 0) 117 118 /* Burst length of RX and TX DMA transfers */ 119 static int sunxi_emac_burst_len = BURST_LEN_DEFAULT; 120 121 /* RX / TX DMA priority. If 1, RX DMA has priority over TX DMA. */ 122 static int sunxi_emac_rx_tx_pri = RX_TX_PRI_DEFAULT; 123 124 /* Pause time field in the transmitted control frame */ 125 static int sunxi_emac_pause_time = PAUSE_TIME_DEFAULT; 126 127 enum sunxi_emac_type { 128 EMAC_A64 = 1, 129 EMAC_A83T, 130 EMAC_H3, 131 EMAC_H6, 132 }; 133 134 static const struct device_compatible_entry compat_data[] = { 135 { .compat = "allwinner,sun8i-a83t-emac", .value = EMAC_A83T }, 136 { .compat = "allwinner,sun8i-h3-emac", .value = EMAC_H3 }, 137 { .compat = "allwinner,sun50i-a64-emac", .value = EMAC_A64 }, 138 { .compat = "allwinner,sun50i-h6-emac", .value = EMAC_H6 }, 139 140 { 0 } 141 }; 142 143 struct sunxi_emac_bufmap { 144 bus_dmamap_t map; 145 struct mbuf *mbuf; 146 }; 147 148 struct sunxi_emac_txring { 149 bus_dma_tag_t desc_tag; 150 bus_dmamap_t desc_map; 151 bus_dma_segment_t desc_dmaseg; 152 struct sunxi_emac_desc *desc_ring; 153 bus_addr_t desc_ring_paddr; 154 bus_dma_tag_t buf_tag; 155 struct sunxi_emac_bufmap buf_map[TX_DESC_COUNT]; 156 u_int cur, next, queued; 157 }; 158 159 struct sunxi_emac_rxring { 160 bus_dma_tag_t desc_tag; 161 bus_dmamap_t desc_map; 162 bus_dma_segment_t desc_dmaseg; 163 struct sunxi_emac_desc *desc_ring; 164 bus_addr_t desc_ring_paddr; 165 bus_dma_tag_t buf_tag; 166 struct sunxi_emac_bufmap buf_map[RX_DESC_COUNT]; 167 u_int cur; 168 }; 169 170 struct sunxi_emac_softc { 171 device_t dev; 172 int phandle; 173 enum sunxi_emac_type type; 174 bus_space_tag_t bst; 175 bus_dma_tag_t dmat; 176 177 bus_space_handle_t bsh; 178 struct clk *clk_ahb; 179 struct clk *clk_ephy; 180 struct fdtbus_reset *rst_ahb; 181 struct fdtbus_reset *rst_ephy; 182 struct fdtbus_regulator *reg_phy; 183 struct fdtbus_gpio_pin *pin_reset; 184 185 struct syscon *syscon; 186 187 int phy_id; 188 189 kmutex_t mtx; 190 struct ethercom ec; 191 struct mii_data mii; 192 callout_t stat_ch; 193 void *ih; 194 u_int mdc_div_ratio_m; 195 196 struct sunxi_emac_txring tx; 197 struct sunxi_emac_rxring rx; 198 }; 199 200 #define RD4(sc, reg) \ 201 bus_space_read_4((sc)->bst, (sc)->bsh, (reg)) 202 #define WR4(sc, reg, val) \ 203 bus_space_write_4((sc)->bst, (sc)->bsh, (reg), (val)) 204 205 static int 206 sunxi_emac_mii_readreg(device_t dev, int phy, int reg, uint16_t *val) 207 { 208 struct sunxi_emac_softc *sc = device_private(dev); 209 int retry; 210 211 WR4(sc, EMAC_MII_CMD, 212 (sc->mdc_div_ratio_m << MDC_DIV_RATIO_M_SHIFT) | 213 (phy << PHY_ADDR_SHIFT) | 214 (reg << PHY_REG_ADDR_SHIFT) | 215 MII_BUSY); 216 for (retry = MII_BUSY_RETRY; retry > 0; retry--) { 217 if ((RD4(sc, EMAC_MII_CMD) & MII_BUSY) == 0) { 218 *val = RD4(sc, EMAC_MII_DATA) & 0xffff; 219 break; 220 } 221 delay(10); 222 } 223 224 if (retry == 0) { 225 device_printf(dev, "phy read timeout, phy=%d reg=%d\n", 226 phy, reg); 227 return ETIMEDOUT; 228 } 229 230 return 0; 231 } 232 233 static int 234 sunxi_emac_mii_writereg(device_t dev, int phy, int reg, uint16_t val) 235 { 236 struct sunxi_emac_softc *sc = device_private(dev); 237 int retry; 238 239 WR4(sc, EMAC_MII_DATA, val); 240 WR4(sc, EMAC_MII_CMD, 241 (sc->mdc_div_ratio_m << MDC_DIV_RATIO_M_SHIFT) | 242 (phy << PHY_ADDR_SHIFT) | 243 (reg << PHY_REG_ADDR_SHIFT) | 244 MII_WR | MII_BUSY); 245 for (retry = MII_BUSY_RETRY; retry > 0; retry--) { 246 if ((RD4(sc, EMAC_MII_CMD) & MII_BUSY) == 0) 247 break; 248 delay(10); 249 } 250 251 if (retry == 0) { 252 device_printf(dev, "phy write timeout, phy=%d reg=%d\n", 253 phy, reg); 254 return ETIMEDOUT; 255 } 256 257 return 0; 258 } 259 260 static void 261 sunxi_emac_update_link(struct sunxi_emac_softc *sc) 262 { 263 struct mii_data *mii = &sc->mii; 264 uint32_t val; 265 266 val = RD4(sc, EMAC_BASIC_CTL_0); 267 val &= ~(BASIC_CTL_SPEED | BASIC_CTL_DUPLEX); 268 269 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 270 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 271 val |= BASIC_CTL_SPEED_1000 << BASIC_CTL_SPEED_SHIFT; 272 else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) 273 val |= BASIC_CTL_SPEED_100 << BASIC_CTL_SPEED_SHIFT; 274 else 275 val |= BASIC_CTL_SPEED_10 << BASIC_CTL_SPEED_SHIFT; 276 277 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 278 val |= BASIC_CTL_DUPLEX; 279 280 WR4(sc, EMAC_BASIC_CTL_0, val); 281 282 val = RD4(sc, EMAC_RX_CTL_0); 283 val &= ~RX_FLOW_CTL_EN; 284 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 285 val |= RX_FLOW_CTL_EN; 286 WR4(sc, EMAC_RX_CTL_0, val); 287 288 val = RD4(sc, EMAC_TX_FLOW_CTL); 289 val &= ~(PAUSE_TIME | TX_FLOW_CTL_EN); 290 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 291 val |= TX_FLOW_CTL_EN; 292 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 293 val |= sunxi_emac_pause_time << PAUSE_TIME_SHIFT; 294 WR4(sc, EMAC_TX_FLOW_CTL, val); 295 } 296 297 static void 298 sunxi_emac_mii_statchg(struct ifnet *ifp) 299 { 300 struct sunxi_emac_softc * const sc = ifp->if_softc; 301 302 sunxi_emac_update_link(sc); 303 } 304 305 static void 306 sunxi_emac_dma_sync(struct sunxi_emac_softc *sc, bus_dma_tag_t dmat, 307 bus_dmamap_t map, int start, int end, int total, int flags) 308 { 309 if (end > start) { 310 bus_dmamap_sync(dmat, map, DESC_OFF(start), 311 DESC_OFF(end) - DESC_OFF(start), flags); 312 } else { 313 bus_dmamap_sync(dmat, map, DESC_OFF(start), 314 DESC_OFF(total) - DESC_OFF(start), flags); 315 if (DESC_OFF(end) - DESC_OFF(0) > 0) 316 bus_dmamap_sync(dmat, map, DESC_OFF(0), 317 DESC_OFF(end) - DESC_OFF(0), flags); 318 } 319 } 320 321 static void 322 sunxi_emac_setup_txdesc(struct sunxi_emac_softc *sc, int index, int flags, 323 bus_addr_t paddr, u_int len) 324 { 325 uint32_t status, size; 326 327 if (paddr == 0 || len == 0) { 328 status = 0; 329 size = 0; 330 --sc->tx.queued; 331 } else { 332 status = TX_DESC_CTL; 333 size = flags | len; 334 ++sc->tx.queued; 335 } 336 337 sc->tx.desc_ring[index].addr = htole32((uint32_t)paddr); 338 sc->tx.desc_ring[index].size = htole32(size); 339 sc->tx.desc_ring[index].status = htole32(status); 340 } 341 342 static int 343 sunxi_emac_setup_txbuf(struct sunxi_emac_softc *sc, int index, struct mbuf *m) 344 { 345 bus_dma_segment_t *segs; 346 int error, nsegs, cur, i, flags; 347 u_int csum_flags; 348 349 error = bus_dmamap_load_mbuf(sc->tx.buf_tag, 350 sc->tx.buf_map[index].map, m, BUS_DMA_WRITE | BUS_DMA_NOWAIT); 351 if (error == EFBIG) { 352 device_printf(sc->dev, 353 "TX packet needs too many DMA segments, dropping...\n"); 354 m_freem(m); 355 return 0; 356 } 357 if (error != 0) 358 return 0; 359 360 segs = sc->tx.buf_map[index].map->dm_segs; 361 nsegs = sc->tx.buf_map[index].map->dm_nsegs; 362 363 flags = TX_FIR_DESC; 364 if ((m->m_pkthdr.csum_flags & M_CSUM_IPv4) != 0) { 365 if ((m->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) != 0) 366 csum_flags = TX_CHECKSUM_CTL_FULL; 367 else 368 csum_flags = TX_CHECKSUM_CTL_IP; 369 flags |= (csum_flags << TX_CHECKSUM_CTL_SHIFT); 370 } 371 372 for (cur = index, i = 0; i < nsegs; i++) { 373 sc->tx.buf_map[cur].mbuf = (i == 0 ? m : NULL); 374 if (i == nsegs - 1) 375 flags |= TX_LAST_DESC | TX_INT_CTL; 376 377 sunxi_emac_setup_txdesc(sc, cur, flags, segs[i].ds_addr, 378 segs[i].ds_len); 379 flags &= ~TX_FIR_DESC; 380 cur = TX_NEXT(cur); 381 } 382 383 bus_dmamap_sync(sc->tx.buf_tag, sc->tx.buf_map[index].map, 384 0, sc->tx.buf_map[index].map->dm_mapsize, BUS_DMASYNC_PREWRITE); 385 386 return nsegs; 387 } 388 389 static void 390 sunxi_emac_setup_rxdesc(struct sunxi_emac_softc *sc, int index, 391 bus_addr_t paddr) 392 { 393 uint32_t status, size; 394 395 status = RX_DESC_CTL; 396 size = MCLBYTES - 1; 397 398 sc->rx.desc_ring[index].addr = htole32((uint32_t)paddr); 399 sc->rx.desc_ring[index].size = htole32(size); 400 sc->rx.desc_ring[index].next = 401 htole32(sc->rx.desc_ring_paddr + DESC_OFF(RX_NEXT(index))); 402 sc->rx.desc_ring[index].status = htole32(status); 403 } 404 405 static int 406 sunxi_emac_setup_rxbuf(struct sunxi_emac_softc *sc, int index, struct mbuf *m) 407 { 408 int error; 409 410 m_adj(m, ETHER_ALIGN); 411 412 error = bus_dmamap_load_mbuf(sc->rx.buf_tag, 413 sc->rx.buf_map[index].map, m, BUS_DMA_READ | BUS_DMA_NOWAIT); 414 if (error != 0) 415 return error; 416 417 bus_dmamap_sync(sc->rx.buf_tag, sc->rx.buf_map[index].map, 418 0, sc->rx.buf_map[index].map->dm_mapsize, 419 BUS_DMASYNC_PREREAD); 420 421 sc->rx.buf_map[index].mbuf = m; 422 sunxi_emac_setup_rxdesc(sc, index, 423 sc->rx.buf_map[index].map->dm_segs[0].ds_addr); 424 425 return 0; 426 } 427 428 static struct mbuf * 429 sunxi_emac_alloc_mbufcl(struct sunxi_emac_softc *sc) 430 { 431 struct mbuf *m; 432 433 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 434 if (m != NULL) 435 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 436 437 return m; 438 } 439 440 static void 441 sunxi_emac_start_locked(struct sunxi_emac_softc *sc) 442 { 443 struct ifnet *ifp = &sc->ec.ec_if; 444 struct mbuf *m; 445 uint32_t val; 446 int cnt, nsegs, start; 447 448 EMAC_ASSERT_LOCKED(sc); 449 450 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 451 return; 452 453 for (cnt = 0, start = sc->tx.cur; ; cnt++) { 454 if (sc->tx.queued >= TX_DESC_COUNT - TX_MAX_SEGS) { 455 ifp->if_flags |= IFF_OACTIVE; 456 break; 457 } 458 459 IFQ_POLL(&ifp->if_snd, m); 460 if (m == NULL) 461 break; 462 463 nsegs = sunxi_emac_setup_txbuf(sc, sc->tx.cur, m); 464 if (nsegs == 0) { 465 ifp->if_flags |= IFF_OACTIVE; 466 break; 467 } 468 IFQ_DEQUEUE(&ifp->if_snd, m); 469 bpf_mtap(ifp, m, BPF_D_OUT); 470 471 sc->tx.cur = TX_SKIP(sc->tx.cur, nsegs); 472 } 473 474 if (cnt != 0) { 475 sunxi_emac_dma_sync(sc, sc->tx.desc_tag, sc->tx.desc_map, 476 start, sc->tx.cur, TX_DESC_COUNT, 477 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 478 479 /* Start and run TX DMA */ 480 val = RD4(sc, EMAC_TX_CTL_1); 481 WR4(sc, EMAC_TX_CTL_1, val | TX_DMA_START); 482 } 483 } 484 485 static void 486 sunxi_emac_start(struct ifnet *ifp) 487 { 488 struct sunxi_emac_softc *sc = ifp->if_softc; 489 490 EMAC_LOCK(sc); 491 sunxi_emac_start_locked(sc); 492 EMAC_UNLOCK(sc); 493 } 494 495 static void 496 sunxi_emac_tick(void *softc) 497 { 498 struct sunxi_emac_softc *sc = softc; 499 struct mii_data *mii = &sc->mii; 500 #ifndef EMAC_MPSAFE 501 int s = splnet(); 502 #endif 503 504 EMAC_LOCK(sc); 505 mii_tick(mii); 506 callout_schedule(&sc->stat_ch, hz); 507 EMAC_UNLOCK(sc); 508 509 #ifndef EMAC_MPSAFE 510 splx(s); 511 #endif 512 } 513 514 /* Bit Reversal - http://aggregate.org/MAGIC/#Bit%20Reversal */ 515 static uint32_t 516 bitrev32(uint32_t x) 517 { 518 x = (((x & 0xaaaaaaaa) >> 1) | ((x & 0x55555555) << 1)); 519 x = (((x & 0xcccccccc) >> 2) | ((x & 0x33333333) << 2)); 520 x = (((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4)); 521 x = (((x & 0xff00ff00) >> 8) | ((x & 0x00ff00ff) << 8)); 522 523 return (x >> 16) | (x << 16); 524 } 525 526 static void 527 sunxi_emac_setup_rxfilter(struct sunxi_emac_softc *sc) 528 { 529 struct ethercom *ec = &sc->ec; 530 struct ifnet *ifp = &ec->ec_if; 531 uint32_t val, crc, hashreg, hashbit, hash[2], machi, maclo; 532 struct ether_multi *enm; 533 struct ether_multistep step; 534 const uint8_t *eaddr; 535 536 EMAC_ASSERT_LOCKED(sc); 537 538 val = 0; 539 hash[0] = hash[1] = 0; 540 541 if ((ifp->if_flags & IFF_PROMISC) != 0) 542 val |= DIS_ADDR_FILTER; 543 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 544 val |= RX_ALL_MULTICAST; 545 hash[0] = hash[1] = ~0; 546 } else { 547 val |= HASH_MULTICAST; 548 ETHER_LOCK(ec); 549 ETHER_FIRST_MULTI(step, ec, enm); 550 while (enm != NULL) { 551 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 552 crc &= 0x7f; 553 crc = bitrev32(~crc) >> 26; 554 hashreg = (crc >> 5); 555 hashbit = (crc & 0x1f); 556 hash[hashreg] |= (1 << hashbit); 557 ETHER_NEXT_MULTI(step, enm); 558 } 559 ETHER_UNLOCK(ec); 560 } 561 562 /* Write our unicast address */ 563 eaddr = CLLADDR(ifp->if_sadl); 564 machi = (eaddr[5] << 8) | eaddr[4]; 565 maclo = (eaddr[3] << 24) | (eaddr[2] << 16) | (eaddr[1] << 8) | 566 (eaddr[0] << 0); 567 WR4(sc, EMAC_ADDR_HIGH(0), machi); 568 WR4(sc, EMAC_ADDR_LOW(0), maclo); 569 570 /* Multicast hash filters */ 571 WR4(sc, EMAC_RX_HASH_0, hash[1]); 572 WR4(sc, EMAC_RX_HASH_1, hash[0]); 573 574 /* RX frame filter config */ 575 WR4(sc, EMAC_RX_FRM_FLT, val); 576 } 577 578 static void 579 sunxi_emac_enable_intr(struct sunxi_emac_softc *sc) 580 { 581 /* Enable interrupts */ 582 WR4(sc, EMAC_INT_EN, RX_INT_EN | TX_INT_EN | TX_BUF_UA_INT_EN); 583 } 584 585 static void 586 sunxi_emac_disable_intr(struct sunxi_emac_softc *sc) 587 { 588 /* Disable interrupts */ 589 WR4(sc, EMAC_INT_EN, 0); 590 } 591 592 #ifdef SUNXI_EMAC_DEBUG 593 static void 594 sunxi_emac_dump_regs(struct sunxi_emac_softc *sc) 595 { 596 static const struct { 597 const char *name; 598 u_int reg; 599 } regs[] = { 600 { "BASIC_CTL_0", EMAC_BASIC_CTL_0 }, 601 { "BASIC_CTL_1", EMAC_BASIC_CTL_1 }, 602 { "INT_STA", EMAC_INT_STA }, 603 { "INT_EN", EMAC_INT_EN }, 604 { "TX_CTL_0", EMAC_TX_CTL_0 }, 605 { "TX_CTL_1", EMAC_TX_CTL_1 }, 606 { "TX_FLOW_CTL", EMAC_TX_FLOW_CTL }, 607 { "TX_DMA_LIST", EMAC_TX_DMA_LIST }, 608 { "RX_CTL_0", EMAC_RX_CTL_0 }, 609 { "RX_CTL_1", EMAC_RX_CTL_1 }, 610 { "RX_DMA_LIST", EMAC_RX_DMA_LIST }, 611 { "RX_FRM_FLT", EMAC_RX_FRM_FLT }, 612 { "RX_HASH_0", EMAC_RX_HASH_0 }, 613 { "RX_HASH_1", EMAC_RX_HASH_1 }, 614 { "MII_CMD", EMAC_MII_CMD }, 615 { "ADDR_HIGH0", EMAC_ADDR_HIGH(0) }, 616 { "ADDR_LOW0", EMAC_ADDR_LOW(0) }, 617 { "TX_DMA_STA", EMAC_TX_DMA_STA }, 618 { "TX_DMA_CUR_DESC", EMAC_TX_DMA_CUR_DESC }, 619 { "TX_DMA_CUR_BUF", EMAC_TX_DMA_CUR_BUF }, 620 { "RX_DMA_STA", EMAC_RX_DMA_STA }, 621 { "RX_DMA_CUR_DESC", EMAC_RX_DMA_CUR_DESC }, 622 { "RX_DMA_CUR_BUF", EMAC_RX_DMA_CUR_BUF }, 623 { "RGMII_STA", EMAC_RGMII_STA }, 624 }; 625 u_int n; 626 627 for (n = 0; n < __arraycount(regs); n++) 628 device_printf(sc->dev, " %-20s %08x\n", regs[n].name, 629 RD4(sc, regs[n].reg)); 630 } 631 #endif 632 633 static int 634 sunxi_emac_reset(struct sunxi_emac_softc *sc) 635 { 636 int retry; 637 638 /* Soft reset all registers and logic */ 639 WR4(sc, EMAC_BASIC_CTL_1, BASIC_CTL_SOFT_RST); 640 641 /* Wait for soft reset bit to self-clear */ 642 for (retry = SOFT_RST_RETRY; retry > 0; retry--) { 643 if ((RD4(sc, EMAC_BASIC_CTL_1) & BASIC_CTL_SOFT_RST) == 0) 644 break; 645 delay(10); 646 } 647 if (retry == 0) { 648 aprint_debug_dev(sc->dev, "soft reset timed out\n"); 649 #ifdef SUNXI_EMAC_DEBUG 650 sunxi_emac_dump_regs(sc); 651 #endif 652 return ETIMEDOUT; 653 } 654 655 return 0; 656 } 657 658 static int 659 sunxi_emac_init_locked(struct sunxi_emac_softc *sc) 660 { 661 struct ifnet *ifp = &sc->ec.ec_if; 662 struct mii_data *mii = &sc->mii; 663 uint32_t val; 664 665 EMAC_ASSERT_LOCKED(sc); 666 667 if ((ifp->if_flags & IFF_RUNNING) != 0) 668 return 0; 669 670 /* Soft reset EMAC core */ 671 sunxi_emac_reset(sc); 672 673 /* Write transmit and receive descriptor base address registers */ 674 WR4(sc, EMAC_TX_DMA_LIST, sc->tx.desc_ring_paddr); 675 WR4(sc, EMAC_RX_DMA_LIST, sc->rx.desc_ring_paddr); 676 677 sunxi_emac_setup_rxfilter(sc); 678 679 /* Configure DMA burst length and priorities */ 680 val = sunxi_emac_burst_len << BASIC_CTL_BURST_LEN_SHIFT; 681 if (sunxi_emac_rx_tx_pri) 682 val |= BASIC_CTL_RX_TX_PRI; 683 WR4(sc, EMAC_BASIC_CTL_1, val); 684 685 /* Enable interrupts */ 686 sunxi_emac_enable_intr(sc); 687 688 /* Enable transmit DMA */ 689 val = RD4(sc, EMAC_TX_CTL_1); 690 WR4(sc, EMAC_TX_CTL_1, val | TX_DMA_EN | TX_MD | TX_NEXT_FRAME); 691 692 /* Enable receive DMA */ 693 val = RD4(sc, EMAC_RX_CTL_1); 694 WR4(sc, EMAC_RX_CTL_1, val | RX_DMA_EN | RX_MD); 695 696 /* Enable transmitter */ 697 val = RD4(sc, EMAC_TX_CTL_0); 698 WR4(sc, EMAC_TX_CTL_0, val | TX_EN); 699 700 /* Enable receiver */ 701 val = RD4(sc, EMAC_RX_CTL_0); 702 WR4(sc, EMAC_RX_CTL_0, val | RX_EN | CHECK_CRC); 703 704 ifp->if_flags |= IFF_RUNNING; 705 ifp->if_flags &= ~IFF_OACTIVE; 706 707 mii_mediachg(mii); 708 callout_schedule(&sc->stat_ch, hz); 709 710 return 0; 711 } 712 713 static int 714 sunxi_emac_init(struct ifnet *ifp) 715 { 716 struct sunxi_emac_softc *sc = ifp->if_softc; 717 int error; 718 719 EMAC_LOCK(sc); 720 error = sunxi_emac_init_locked(sc); 721 EMAC_UNLOCK(sc); 722 723 return error; 724 } 725 726 static void 727 sunxi_emac_stop_locked(struct sunxi_emac_softc *sc, int disable) 728 { 729 struct ifnet *ifp = &sc->ec.ec_if; 730 uint32_t val; 731 732 EMAC_ASSERT_LOCKED(sc); 733 734 callout_stop(&sc->stat_ch); 735 736 mii_down(&sc->mii); 737 738 /* Stop transmit DMA and flush data in the TX FIFO */ 739 val = RD4(sc, EMAC_TX_CTL_1); 740 val &= ~TX_DMA_EN; 741 val |= FLUSH_TX_FIFO; 742 WR4(sc, EMAC_TX_CTL_1, val); 743 744 /* Disable transmitter */ 745 val = RD4(sc, EMAC_TX_CTL_0); 746 WR4(sc, EMAC_TX_CTL_0, val & ~TX_EN); 747 748 /* Disable receiver */ 749 val = RD4(sc, EMAC_RX_CTL_0); 750 WR4(sc, EMAC_RX_CTL_0, val & ~RX_EN); 751 752 /* Disable interrupts */ 753 sunxi_emac_disable_intr(sc); 754 755 /* Disable transmit DMA */ 756 val = RD4(sc, EMAC_TX_CTL_1); 757 WR4(sc, EMAC_TX_CTL_1, val & ~TX_DMA_EN); 758 759 /* Disable receive DMA */ 760 val = RD4(sc, EMAC_RX_CTL_1); 761 WR4(sc, EMAC_RX_CTL_1, val & ~RX_DMA_EN); 762 763 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 764 } 765 766 static void 767 sunxi_emac_stop(struct ifnet *ifp, int disable) 768 { 769 struct sunxi_emac_softc * const sc = ifp->if_softc; 770 771 EMAC_LOCK(sc); 772 sunxi_emac_stop_locked(sc, disable); 773 EMAC_UNLOCK(sc); 774 } 775 776 static int 777 sunxi_emac_rxintr(struct sunxi_emac_softc *sc) 778 { 779 struct ifnet *ifp = &sc->ec.ec_if; 780 int error, index, len, npkt; 781 struct mbuf *m, *m0; 782 uint32_t status; 783 784 npkt = 0; 785 786 for (index = sc->rx.cur; ; index = RX_NEXT(index)) { 787 sunxi_emac_dma_sync(sc, sc->rx.desc_tag, sc->rx.desc_map, 788 index, index + 1, RX_DESC_COUNT, 789 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 790 791 status = le32toh(sc->rx.desc_ring[index].status); 792 if ((status & RX_DESC_CTL) != 0) 793 break; 794 795 bus_dmamap_sync(sc->rx.buf_tag, sc->rx.buf_map[index].map, 796 0, sc->rx.buf_map[index].map->dm_mapsize, 797 BUS_DMASYNC_POSTREAD); 798 bus_dmamap_unload(sc->rx.buf_tag, sc->rx.buf_map[index].map); 799 800 len = (status & RX_FRM_LEN) >> RX_FRM_LEN_SHIFT; 801 if (len != 0) { 802 m = sc->rx.buf_map[index].mbuf; 803 m_set_rcvif(m, ifp); 804 m->m_flags |= M_HASFCS; 805 m->m_pkthdr.len = len; 806 m->m_len = len; 807 m->m_nextpkt = NULL; 808 809 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) != 0 && 810 (status & RX_FRM_TYPE) != 0) { 811 m->m_pkthdr.csum_flags = M_CSUM_IPv4 | 812 M_CSUM_TCPv4 | M_CSUM_UDPv4; 813 if ((status & RX_HEADER_ERR) != 0) 814 m->m_pkthdr.csum_flags |= 815 M_CSUM_IPv4_BAD; 816 if ((status & RX_PAYLOAD_ERR) != 0) 817 m->m_pkthdr.csum_flags |= 818 M_CSUM_TCP_UDP_BAD; 819 } 820 821 ++npkt; 822 823 if_percpuq_enqueue(ifp->if_percpuq, m); 824 } 825 826 if ((m0 = sunxi_emac_alloc_mbufcl(sc)) != NULL) { 827 error = sunxi_emac_setup_rxbuf(sc, index, m0); 828 if (error != 0) { 829 /* XXX hole in RX ring */ 830 } 831 } else 832 if_statinc(ifp, if_ierrors); 833 834 sunxi_emac_dma_sync(sc, sc->rx.desc_tag, sc->rx.desc_map, 835 index, index + 1, 836 RX_DESC_COUNT, BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 837 } 838 839 sc->rx.cur = index; 840 841 return npkt; 842 } 843 844 static void 845 sunxi_emac_txintr(struct sunxi_emac_softc *sc) 846 { 847 struct ifnet *ifp = &sc->ec.ec_if; 848 struct sunxi_emac_bufmap *bmap; 849 struct sunxi_emac_desc *desc; 850 uint32_t status; 851 int i; 852 853 EMAC_ASSERT_LOCKED(sc); 854 855 for (i = sc->tx.next; sc->tx.queued > 0; i = TX_NEXT(i)) { 856 KASSERT(sc->tx.queued > 0 && sc->tx.queued <= TX_DESC_COUNT); 857 sunxi_emac_dma_sync(sc, sc->tx.desc_tag, sc->tx.desc_map, 858 i, i + 1, TX_DESC_COUNT, 859 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 860 desc = &sc->tx.desc_ring[i]; 861 status = le32toh(desc->status); 862 if ((status & TX_DESC_CTL) != 0) 863 break; 864 bmap = &sc->tx.buf_map[i]; 865 if (bmap->mbuf != NULL) { 866 bus_dmamap_sync(sc->tx.buf_tag, bmap->map, 867 0, bmap->map->dm_mapsize, 868 BUS_DMASYNC_POSTWRITE); 869 bus_dmamap_unload(sc->tx.buf_tag, bmap->map); 870 m_freem(bmap->mbuf); 871 bmap->mbuf = NULL; 872 } 873 874 sunxi_emac_setup_txdesc(sc, i, 0, 0, 0); 875 sunxi_emac_dma_sync(sc, sc->tx.desc_tag, sc->tx.desc_map, 876 i, i + 1, TX_DESC_COUNT, 877 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 878 879 ifp->if_flags &= ~IFF_OACTIVE; 880 if_statinc(ifp, if_opackets); 881 } 882 883 sc->tx.next = i; 884 } 885 886 static int 887 sunxi_emac_intr(void *arg) 888 { 889 struct sunxi_emac_softc *sc = arg; 890 struct ifnet *ifp = &sc->ec.ec_if; 891 uint32_t val; 892 893 EMAC_LOCK(sc); 894 895 val = RD4(sc, EMAC_INT_STA); 896 WR4(sc, EMAC_INT_STA, val); 897 898 if (val & RX_INT) 899 sunxi_emac_rxintr(sc); 900 901 if (val & (TX_INT | TX_BUF_UA_INT)) { 902 sunxi_emac_txintr(sc); 903 if_schedule_deferred_start(ifp); 904 } 905 906 EMAC_UNLOCK(sc); 907 908 return 1; 909 } 910 911 static int 912 sunxi_emac_ioctl(struct ifnet *ifp, u_long cmd, void *data) 913 { 914 struct sunxi_emac_softc *sc = ifp->if_softc; 915 int error, s; 916 917 #ifndef EMAC_MPSAFE 918 s = splnet(); 919 #endif 920 921 switch (cmd) { 922 default: 923 #ifdef EMAC_MPSAFE 924 s = splnet(); 925 #endif 926 error = ether_ioctl(ifp, cmd, data); 927 #ifdef EMAC_MPSAFE 928 splx(s); 929 #endif 930 if (error != ENETRESET) 931 break; 932 933 error = 0; 934 935 if (cmd == SIOCSIFCAP) 936 error = (*ifp->if_init)(ifp); 937 else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 938 ; 939 else if ((ifp->if_flags & IFF_RUNNING) != 0) { 940 EMAC_LOCK(sc); 941 sunxi_emac_setup_rxfilter(sc); 942 EMAC_UNLOCK(sc); 943 } 944 break; 945 } 946 947 #ifndef EMAC_MPSAFE 948 splx(s); 949 #endif 950 951 return error; 952 } 953 954 static bool 955 sunxi_emac_has_internal_phy(struct sunxi_emac_softc *sc) 956 { 957 const char * mdio_internal_compat[] = { 958 "allwinner,sun8i-h3-mdio-internal", 959 NULL 960 }; 961 int phy; 962 963 /* Non-standard property, for compatible with old dts files */ 964 if (of_hasprop(sc->phandle, "allwinner,use-internal-phy")) 965 return true; 966 967 phy = fdtbus_get_phandle(sc->phandle, "phy-handle"); 968 if (phy == -1) 969 return false; 970 971 /* For internal PHY, check compatible string of parent node */ 972 return of_compatible(OF_parent(phy), mdio_internal_compat) >= 0; 973 } 974 975 static int 976 sunxi_emac_setup_phy(struct sunxi_emac_softc *sc) 977 { 978 uint32_t reg, tx_delay, rx_delay; 979 const char *phy_type; 980 981 phy_type = fdtbus_get_string(sc->phandle, "phy-mode"); 982 if (phy_type == NULL) 983 return 0; 984 985 aprint_debug_dev(sc->dev, "PHY type: %s\n", phy_type); 986 987 syscon_lock(sc->syscon); 988 reg = syscon_read_4(sc->syscon, EMAC_CLK_REG); 989 990 reg &= ~(EMAC_CLK_PIT | EMAC_CLK_SRC | EMAC_CLK_RMII_EN); 991 if (strcmp(phy_type, "rgmii") == 0) 992 reg |= EMAC_CLK_PIT_RGMII | EMAC_CLK_SRC_RGMII; 993 else if (strcmp(phy_type, "rmii") == 0) 994 reg |= EMAC_CLK_RMII_EN; 995 else 996 reg |= EMAC_CLK_PIT_MII | EMAC_CLK_SRC_MII; 997 998 if (of_getprop_uint32(sc->phandle, "allwinner,tx-delay-ps", 999 &tx_delay) == 0) { 1000 reg &= ~EMAC_CLK_ETXDC; 1001 reg |= ((tx_delay / 100) << EMAC_CLK_ETXDC_SHIFT); 1002 } else if (of_getprop_uint32(sc->phandle, "tx-delay", &tx_delay) == 0) { 1003 reg &= ~EMAC_CLK_ETXDC; 1004 reg |= (tx_delay << EMAC_CLK_ETXDC_SHIFT); 1005 } 1006 if (of_getprop_uint32(sc->phandle, "allwinner,rx-delay-ps", 1007 &rx_delay) == 0) { 1008 reg &= ~EMAC_CLK_ERXDC; 1009 reg |= ((rx_delay / 100) << EMAC_CLK_ERXDC_SHIFT); 1010 } else if (of_getprop_uint32(sc->phandle, "rx-delay", &rx_delay) == 0) { 1011 reg &= ~EMAC_CLK_ERXDC; 1012 reg |= (rx_delay << EMAC_CLK_ERXDC_SHIFT); 1013 } 1014 1015 if (sc->type == EMAC_H3 || sc->type == EMAC_H6) { 1016 if (sunxi_emac_has_internal_phy(sc)) { 1017 reg |= EMAC_CLK_EPHY_SELECT; 1018 reg &= ~EMAC_CLK_EPHY_SHUTDOWN; 1019 if (of_hasprop(sc->phandle, 1020 "allwinner,leds-active-low")) 1021 reg |= EMAC_CLK_EPHY_LED_POL; 1022 else 1023 reg &= ~EMAC_CLK_EPHY_LED_POL; 1024 1025 /* Set internal PHY addr to 1 */ 1026 reg &= ~EMAC_CLK_EPHY_ADDR; 1027 reg |= (1 << EMAC_CLK_EPHY_ADDR_SHIFT); 1028 } else { 1029 reg &= ~EMAC_CLK_EPHY_SELECT; 1030 } 1031 } 1032 1033 aprint_debug_dev(sc->dev, "EMAC clock: 0x%08x\n", reg); 1034 1035 syscon_write_4(sc->syscon, EMAC_CLK_REG, reg); 1036 syscon_unlock(sc->syscon); 1037 1038 return 0; 1039 } 1040 1041 static int 1042 sunxi_emac_setup_resources(struct sunxi_emac_softc *sc) 1043 { 1044 u_int freq; 1045 int error, div; 1046 1047 /* Configure PHY for MII or RGMII mode */ 1048 if (sunxi_emac_setup_phy(sc) != 0) 1049 return ENXIO; 1050 1051 /* Enable clocks */ 1052 error = clk_enable(sc->clk_ahb); 1053 if (error != 0) { 1054 aprint_error_dev(sc->dev, "cannot enable ahb clock\n"); 1055 return error; 1056 } 1057 1058 if (sc->clk_ephy != NULL) { 1059 error = clk_enable(sc->clk_ephy); 1060 if (error != 0) { 1061 aprint_error_dev(sc->dev, "cannot enable ephy clock\n"); 1062 return error; 1063 } 1064 } 1065 1066 /* De-assert reset */ 1067 error = fdtbus_reset_deassert(sc->rst_ahb); 1068 if (error != 0) { 1069 aprint_error_dev(sc->dev, "cannot de-assert ahb reset\n"); 1070 return error; 1071 } 1072 if (sc->rst_ephy != NULL) { 1073 error = fdtbus_reset_deassert(sc->rst_ephy); 1074 if (error != 0) { 1075 aprint_error_dev(sc->dev, 1076 "cannot de-assert ephy reset\n"); 1077 return error; 1078 } 1079 } 1080 1081 /* Enable PHY regulator if applicable */ 1082 if (sc->reg_phy != NULL) { 1083 error = fdtbus_regulator_enable(sc->reg_phy); 1084 if (error != 0) { 1085 aprint_error_dev(sc->dev, 1086 "cannot enable PHY regulator\n"); 1087 return error; 1088 } 1089 } 1090 1091 /* Determine MDC clock divide ratio based on AHB clock */ 1092 freq = clk_get_rate(sc->clk_ahb); 1093 if (freq == 0) { 1094 aprint_error_dev(sc->dev, "cannot get AHB clock frequency\n"); 1095 return ENXIO; 1096 } 1097 div = freq / MDIO_FREQ; 1098 if (div <= 16) 1099 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_16; 1100 else if (div <= 32) 1101 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_32; 1102 else if (div <= 64) 1103 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_64; 1104 else if (div <= 128) 1105 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_128; 1106 else { 1107 aprint_error_dev(sc->dev, 1108 "cannot determine MDC clock divide ratio\n"); 1109 return ENXIO; 1110 } 1111 1112 aprint_debug_dev(sc->dev, "AHB frequency %u Hz, MDC div: 0x%x\n", 1113 freq, sc->mdc_div_ratio_m); 1114 1115 return 0; 1116 } 1117 1118 static void 1119 sunxi_emac_get_eaddr(struct sunxi_emac_softc *sc, uint8_t *eaddr) 1120 { 1121 uint32_t maclo, machi; 1122 #if notyet 1123 u_char rootkey[16]; 1124 #endif 1125 1126 machi = RD4(sc, EMAC_ADDR_HIGH(0)) & 0xffff; 1127 maclo = RD4(sc, EMAC_ADDR_LOW(0)); 1128 1129 if (maclo == 0xffffffff && machi == 0xffff) { 1130 #if notyet 1131 /* MAC address in hardware is invalid, create one */ 1132 if (aw_sid_get_rootkey(rootkey) == 0 && 1133 (rootkey[3] | rootkey[12] | rootkey[13] | rootkey[14] | 1134 rootkey[15]) != 0) { 1135 /* MAC address is derived from the root key in SID */ 1136 maclo = (rootkey[13] << 24) | (rootkey[12] << 16) | 1137 (rootkey[3] << 8) | 0x02; 1138 machi = (rootkey[15] << 8) | rootkey[14]; 1139 } else { 1140 #endif 1141 /* Create one */ 1142 maclo = 0x00f2 | (cprng_strong32() & 0xffff0000); 1143 machi = cprng_strong32() & 0xffff; 1144 #if notyet 1145 } 1146 #endif 1147 } 1148 1149 eaddr[0] = maclo & 0xff; 1150 eaddr[1] = (maclo >> 8) & 0xff; 1151 eaddr[2] = (maclo >> 16) & 0xff; 1152 eaddr[3] = (maclo >> 24) & 0xff; 1153 eaddr[4] = machi & 0xff; 1154 eaddr[5] = (machi >> 8) & 0xff; 1155 } 1156 1157 static int 1158 sunxi_emac_phy_reset(struct sunxi_emac_softc *sc) 1159 { 1160 uint32_t delay_prop[3]; 1161 int pin_value; 1162 1163 if (sc->pin_reset == NULL) 1164 return 0; 1165 1166 if (OF_getprop(sc->phandle, "allwinner,reset-delays-us", delay_prop, 1167 sizeof(delay_prop)) <= 0) 1168 return ENXIO; 1169 1170 pin_value = of_hasprop(sc->phandle, "allwinner,reset-active-low"); 1171 1172 fdtbus_gpio_write(sc->pin_reset, pin_value); 1173 delay(htole32(delay_prop[0])); 1174 fdtbus_gpio_write(sc->pin_reset, !pin_value); 1175 delay(htole32(delay_prop[1])); 1176 fdtbus_gpio_write(sc->pin_reset, pin_value); 1177 delay(htole32(delay_prop[2])); 1178 1179 return 0; 1180 } 1181 1182 static int 1183 sunxi_emac_setup_dma(struct sunxi_emac_softc *sc) 1184 { 1185 struct mbuf *m; 1186 int error, nsegs, i; 1187 1188 /* Setup TX ring */ 1189 sc->tx.buf_tag = sc->tx.desc_tag = sc->dmat; 1190 error = bus_dmamap_create(sc->dmat, TX_DESC_SIZE, 1, TX_DESC_SIZE, 0, 1191 BUS_DMA_WAITOK, &sc->tx.desc_map); 1192 if (error) 1193 return error; 1194 error = bus_dmamem_alloc(sc->dmat, TX_DESC_SIZE, DESC_ALIGN, 0, 1195 &sc->tx.desc_dmaseg, 1, &nsegs, BUS_DMA_WAITOK); 1196 if (error) 1197 return error; 1198 error = bus_dmamem_map(sc->dmat, &sc->tx.desc_dmaseg, nsegs, 1199 TX_DESC_SIZE, (void *)&sc->tx.desc_ring, 1200 BUS_DMA_WAITOK); 1201 if (error) 1202 return error; 1203 error = bus_dmamap_load(sc->dmat, sc->tx.desc_map, sc->tx.desc_ring, 1204 TX_DESC_SIZE, NULL, BUS_DMA_WAITOK); 1205 if (error) 1206 return error; 1207 sc->tx.desc_ring_paddr = sc->tx.desc_map->dm_segs[0].ds_addr; 1208 1209 memset(sc->tx.desc_ring, 0, TX_DESC_SIZE); 1210 bus_dmamap_sync(sc->dmat, sc->tx.desc_map, 0, TX_DESC_SIZE, 1211 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1212 1213 for (i = 0; i < TX_DESC_COUNT; i++) 1214 sc->tx.desc_ring[i].next = 1215 htole32(sc->tx.desc_ring_paddr + DESC_OFF(TX_NEXT(i))); 1216 1217 sc->tx.queued = TX_DESC_COUNT; 1218 for (i = 0; i < TX_DESC_COUNT; i++) { 1219 error = bus_dmamap_create(sc->tx.buf_tag, MCLBYTES, 1220 TX_MAX_SEGS, MCLBYTES, 0, BUS_DMA_WAITOK, 1221 &sc->tx.buf_map[i].map); 1222 if (error != 0) { 1223 device_printf(sc->dev, "cannot create TX buffer map\n"); 1224 return error; 1225 } 1226 sunxi_emac_setup_txdesc(sc, i, 0, 0, 0); 1227 } 1228 1229 /* Setup RX ring */ 1230 sc->rx.buf_tag = sc->rx.desc_tag = sc->dmat; 1231 error = bus_dmamap_create(sc->dmat, RX_DESC_SIZE, 1, RX_DESC_SIZE, 0, 1232 BUS_DMA_WAITOK, &sc->rx.desc_map); 1233 if (error) 1234 return error; 1235 error = bus_dmamem_alloc(sc->dmat, RX_DESC_SIZE, DESC_ALIGN, 0, 1236 &sc->rx.desc_dmaseg, 1, &nsegs, BUS_DMA_WAITOK); 1237 if (error) 1238 return error; 1239 error = bus_dmamem_map(sc->dmat, &sc->rx.desc_dmaseg, nsegs, 1240 RX_DESC_SIZE, (void *)&sc->rx.desc_ring, 1241 BUS_DMA_WAITOK); 1242 if (error) 1243 return error; 1244 error = bus_dmamap_load(sc->dmat, sc->rx.desc_map, sc->rx.desc_ring, 1245 RX_DESC_SIZE, NULL, BUS_DMA_WAITOK); 1246 if (error) 1247 return error; 1248 sc->rx.desc_ring_paddr = sc->rx.desc_map->dm_segs[0].ds_addr; 1249 1250 memset(sc->rx.desc_ring, 0, RX_DESC_SIZE); 1251 1252 for (i = 0; i < RX_DESC_COUNT; i++) { 1253 error = bus_dmamap_create(sc->rx.buf_tag, MCLBYTES, 1254 RX_DESC_COUNT, MCLBYTES, 0, BUS_DMA_WAITOK, 1255 &sc->rx.buf_map[i].map); 1256 if (error != 0) { 1257 device_printf(sc->dev, "cannot create RX buffer map\n"); 1258 return error; 1259 } 1260 if ((m = sunxi_emac_alloc_mbufcl(sc)) == NULL) { 1261 device_printf(sc->dev, "cannot allocate RX mbuf\n"); 1262 return ENOMEM; 1263 } 1264 error = sunxi_emac_setup_rxbuf(sc, i, m); 1265 if (error != 0) { 1266 device_printf(sc->dev, "cannot create RX buffer\n"); 1267 return error; 1268 } 1269 } 1270 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map, 1271 0, sc->rx.desc_map->dm_mapsize, 1272 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1273 1274 return 0; 1275 } 1276 1277 static int 1278 sunxi_emac_get_resources(struct sunxi_emac_softc *sc) 1279 { 1280 const int phandle = sc->phandle; 1281 bus_addr_t addr, size; 1282 1283 /* Map EMAC registers */ 1284 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 1285 aprint_error_dev(sc->dev, "unable to get registers\n"); 1286 return ENXIO; 1287 } 1288 if (bus_space_map(sc->bst, addr, size, 0, &sc->bsh) != 0) { 1289 aprint_error_dev(sc->dev, "unable to map registers\n"); 1290 return ENXIO; 1291 } 1292 1293 /* Get SYSCON registers */ 1294 sc->syscon = fdtbus_syscon_acquire(phandle, "syscon"); 1295 if (sc->syscon == NULL) { 1296 aprint_error_dev(sc->dev, "unable to acquire syscon\n"); 1297 return ENXIO; 1298 } 1299 1300 /* The "ahb"/"stmmaceth" clock and reset is required */ 1301 if ((sc->clk_ahb = fdtbus_clock_get(phandle, "ahb")) == NULL && 1302 (sc->clk_ahb = fdtbus_clock_get(phandle, "stmmaceth")) == NULL) { 1303 aprint_error_dev(sc->dev, "unable to get clock\n"); 1304 return ENXIO; 1305 } 1306 if ((sc->rst_ahb = fdtbus_reset_get(phandle, "ahb")) == NULL && 1307 (sc->rst_ahb = fdtbus_reset_get(phandle, "stmmaceth")) == NULL) { 1308 aprint_error_dev(sc->dev, "unable to get reset\n"); 1309 return ENXIO; 1310 } 1311 1312 /* Internal PHY clock and reset are optional properties. */ 1313 sc->clk_ephy = fdtbus_clock_get(phandle, "ephy"); 1314 if (sc->clk_ephy == NULL) { 1315 int phy_phandle = fdtbus_get_phandle(phandle, "phy-handle"); 1316 if (phy_phandle != -1) 1317 sc->clk_ephy = fdtbus_clock_get_index(phy_phandle, 0); 1318 } 1319 sc->rst_ephy = fdtbus_reset_get(phandle, "ephy"); 1320 if (sc->rst_ephy == NULL) { 1321 int phy_phandle = fdtbus_get_phandle(phandle, "phy-handle"); 1322 if (phy_phandle != -1) 1323 sc->rst_ephy = fdtbus_reset_get_index(phy_phandle, 0); 1324 } 1325 1326 /* Regulator is optional */ 1327 sc->reg_phy = fdtbus_regulator_acquire(phandle, "phy-supply"); 1328 1329 /* Reset GPIO is optional */ 1330 sc->pin_reset = fdtbus_gpio_acquire(sc->phandle, 1331 "allwinner,reset-gpio", GPIO_PIN_OUTPUT); 1332 1333 return 0; 1334 } 1335 1336 static int 1337 sunxi_emac_get_phyid(struct sunxi_emac_softc *sc) 1338 { 1339 bus_addr_t addr; 1340 int phy_phandle; 1341 1342 phy_phandle = fdtbus_get_phandle(sc->phandle, "phy"); 1343 if (phy_phandle == -1) 1344 phy_phandle = fdtbus_get_phandle(sc->phandle, "phy-handle"); 1345 if (phy_phandle == -1) 1346 return MII_PHY_ANY; 1347 1348 if (fdtbus_get_reg(phy_phandle, 0, &addr, NULL) != 0) 1349 return MII_PHY_ANY; 1350 1351 return (int)addr; 1352 } 1353 1354 static int 1355 sunxi_emac_match(device_t parent, cfdata_t cf, void *aux) 1356 { 1357 struct fdt_attach_args * const faa = aux; 1358 1359 return of_match_compat_data(faa->faa_phandle, compat_data); 1360 } 1361 1362 static void 1363 sunxi_emac_attach(device_t parent, device_t self, void *aux) 1364 { 1365 struct fdt_attach_args * const faa = aux; 1366 struct sunxi_emac_softc * const sc = device_private(self); 1367 const int phandle = faa->faa_phandle; 1368 struct mii_data *mii = &sc->mii; 1369 struct ifnet *ifp = &sc->ec.ec_if; 1370 uint8_t eaddr[ETHER_ADDR_LEN]; 1371 char intrstr[128]; 1372 1373 sc->dev = self; 1374 sc->phandle = phandle; 1375 sc->bst = faa->faa_bst; 1376 sc->dmat = faa->faa_dmat; 1377 sc->type = of_search_compatible(phandle, compat_data)->value; 1378 sc->phy_id = sunxi_emac_get_phyid(sc); 1379 1380 aprint_naive("\n"); 1381 aprint_normal(": EMAC\n"); 1382 1383 if (sunxi_emac_get_resources(sc) != 0) { 1384 aprint_error_dev(self, 1385 "cannot allocate resources for device\n"); 1386 return; 1387 } 1388 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 1389 aprint_error_dev(self, "cannot decode interrupt\n"); 1390 return; 1391 } 1392 1393 mutex_init(&sc->mtx, MUTEX_DEFAULT, IPL_NET); 1394 callout_init(&sc->stat_ch, CALLOUT_FLAGS); 1395 callout_setfunc(&sc->stat_ch, sunxi_emac_tick, sc); 1396 1397 /* Setup clocks and regulators */ 1398 if (sunxi_emac_setup_resources(sc) != 0) 1399 return; 1400 1401 /* Read MAC address before resetting the chip */ 1402 sunxi_emac_get_eaddr(sc, eaddr); 1403 aprint_normal_dev(self, "Ethernet address %s\n", ether_sprintf(eaddr)); 1404 1405 /* Reset PHY if necessary */ 1406 if (sunxi_emac_phy_reset(sc) != 0) { 1407 aprint_error_dev(self, "failed to reset PHY\n"); 1408 return; 1409 } 1410 1411 /* Setup DMA descriptors */ 1412 if (sunxi_emac_setup_dma(sc) != 0) { 1413 aprint_error_dev(self, "failed to setup DMA descriptors\n"); 1414 return; 1415 } 1416 1417 /* Install interrupt handler */ 1418 sc->ih = fdtbus_intr_establish_xname(phandle, 0, IPL_NET, 1419 FDT_INTR_FLAGS, sunxi_emac_intr, sc, device_xname(self)); 1420 if (sc->ih == NULL) { 1421 aprint_error_dev(self, "failed to establish interrupt on %s\n", 1422 intrstr); 1423 return; 1424 } 1425 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 1426 1427 /* Setup ethernet interface */ 1428 ifp->if_softc = sc; 1429 snprintf(ifp->if_xname, IFNAMSIZ, EMAC_IFNAME, device_unit(self)); 1430 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1431 #ifdef EMAC_MPSAFE 1432 ifp->if_extflags = IFEF_MPSAFE; 1433 #endif 1434 ifp->if_start = sunxi_emac_start; 1435 ifp->if_ioctl = sunxi_emac_ioctl; 1436 ifp->if_init = sunxi_emac_init; 1437 ifp->if_stop = sunxi_emac_stop; 1438 ifp->if_capabilities = IFCAP_CSUM_IPv4_Rx | 1439 IFCAP_CSUM_IPv4_Tx | 1440 IFCAP_CSUM_TCPv4_Rx | 1441 IFCAP_CSUM_TCPv4_Tx | 1442 IFCAP_CSUM_UDPv4_Rx | 1443 IFCAP_CSUM_UDPv4_Tx; 1444 ifp->if_capenable = ifp->if_capabilities; 1445 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 1446 IFQ_SET_READY(&ifp->if_snd); 1447 1448 /* 802.1Q VLAN-sized frames are supported */ 1449 sc->ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 1450 1451 /* Attach MII driver */ 1452 sc->ec.ec_mii = mii; 1453 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 1454 mii->mii_ifp = ifp; 1455 mii->mii_readreg = sunxi_emac_mii_readreg; 1456 mii->mii_writereg = sunxi_emac_mii_writereg; 1457 mii->mii_statchg = sunxi_emac_mii_statchg; 1458 mii_attach(self, mii, 0xffffffff, sc->phy_id, MII_OFFSET_ANY, 1459 MIIF_DOPAUSE); 1460 1461 if (LIST_EMPTY(&mii->mii_phys)) { 1462 aprint_error_dev(self, "no PHY found!\n"); 1463 return; 1464 } 1465 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 1466 1467 /* Attach interface */ 1468 if_attach(ifp); 1469 if_deferred_start_init(ifp, NULL); 1470 1471 /* Attach ethernet interface */ 1472 ether_ifattach(ifp, eaddr); 1473 } 1474 1475 CFATTACH_DECL_NEW(sunxi_emac, sizeof(struct sunxi_emac_softc), 1476 sunxi_emac_match, sunxi_emac_attach, NULL, NULL); 1477
Indexes created Mon Oct 20 11:09:49 GMT 2025