sunxi_emac.c revision 1.4.6.2
1 /* $NetBSD: sunxi_emac.c,v 1.4.6.2 2017/08/28 17:51:32 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2016-2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Allwinner Gigabit Ethernet MAC (EMAC) controller 31 */ 32 33 #include "opt_net_mpsafe.h" 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: sunxi_emac.c,v 1.4.6.2 2017/08/28 17:51:32 skrll Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/bus.h> 40 #include <sys/device.h> 41 #include <sys/intr.h> 42 #include <sys/systm.h> 43 #include <sys/kernel.h> 44 #include <sys/mutex.h> 45 #include <sys/callout.h> 46 #include <sys/gpio.h> 47 #include <sys/cprng.h> 48 49 #include <net/if.h> 50 #include <net/if_dl.h> 51 #include <net/if_ether.h> 52 #include <net/if_media.h> 53 #include <net/bpf.h> 54 55 #include <dev/mii/miivar.h> 56 57 #include <dev/fdt/fdtvar.h> 58 59 #include <arm/sunxi/sunxi_emac.h> 60 61 #ifdef NET_MPSAFE 62 #define EMAC_MPSAFE 1 63 #define CALLOUT_FLAGS CALLOUT_MPSAFE 64 #define FDT_INTR_FLAGS FDT_INTR_MPSAFE 65 #else 66 #define CALLOUT_FLAGS 0 67 #define FDT_INTR_FLAGS 0 68 #endif 69 70 #define EMAC_IFNAME "emac%d" 71 72 #define ETHER_ALIGN 2 73 74 #define EMAC_LOCK(sc) mutex_enter(&(sc)->mtx) 75 #define EMAC_UNLOCK(sc) mutex_exit(&(sc)->mtx) 76 #define EMAC_ASSERT_LOCKED(sc) KASSERT(mutex_owned(&(sc)->mtx)) 77 78 #define DESC_ALIGN sizeof(struct sunxi_emac_desc) 79 #define TX_DESC_COUNT 1024 80 #define TX_DESC_SIZE (sizeof(struct sunxi_emac_desc) * TX_DESC_COUNT) 81 #define RX_DESC_COUNT 256 82 #define RX_DESC_SIZE (sizeof(struct sunxi_emac_desc) * RX_DESC_COUNT) 83 84 #define DESC_OFF(n) ((n) * sizeof(struct sunxi_emac_desc)) 85 #define TX_NEXT(n) (((n) + 1) & (TX_DESC_COUNT - 1)) 86 #define TX_SKIP(n, o) (((n) + (o)) & (TX_DESC_COUNT - 1)) 87 #define RX_NEXT(n) (((n) + 1) & (RX_DESC_COUNT - 1)) 88 89 #define TX_MAX_SEGS 128 90 91 #define SOFT_RST_RETRY 1000 92 #define MII_BUSY_RETRY 1000 93 #define MDIO_FREQ 2500000 94 95 #define BURST_LEN_DEFAULT 8 96 #define RX_TX_PRI_DEFAULT 0 97 #define PAUSE_TIME_DEFAULT 0x400 98 #define TX_INTERVAL_DEFAULT 64 99 100 /* syscon EMAC clock register */ 101 #define EMAC_CLK_EPHY_ADDR (0x1f << 20) /* H3 */ 102 #define EMAC_CLK_EPHY_ADDR_SHIFT 20 103 #define EMAC_CLK_EPHY_LED_POL (1 << 17) /* H3 */ 104 #define EMAC_CLK_EPHY_SHUTDOWN (1 << 16) /* H3 */ 105 #define EMAC_CLK_EPHY_SELECT (1 << 15) /* H3 */ 106 #define EMAC_CLK_RMII_EN (1 << 13) 107 #define EMAC_CLK_ETXDC (0x7 << 10) 108 #define EMAC_CLK_ETXDC_SHIFT 10 109 #define EMAC_CLK_ERXDC (0x1f << 5) 110 #define EMAC_CLK_ERXDC_SHIFT 5 111 #define EMAC_CLK_PIT (0x1 << 2) 112 #define EMAC_CLK_PIT_MII (0 << 2) 113 #define EMAC_CLK_PIT_RGMII (1 << 2) 114 #define EMAC_CLK_SRC (0x3 << 0) 115 #define EMAC_CLK_SRC_MII (0 << 0) 116 #define EMAC_CLK_SRC_EXT_RGMII (1 << 0) 117 #define EMAC_CLK_SRC_RGMII (2 << 0) 118 119 /* Burst length of RX and TX DMA transfers */ 120 static int sunxi_emac_burst_len = BURST_LEN_DEFAULT; 121 122 /* RX / TX DMA priority. If 1, RX DMA has priority over TX DMA. */ 123 static int sunxi_emac_rx_tx_pri = RX_TX_PRI_DEFAULT; 124 125 /* Pause time field in the transmitted control frame */ 126 static int sunxi_emac_pause_time = PAUSE_TIME_DEFAULT; 127 128 /* Request a TX interrupt every <n> descriptors */ 129 static int sunxi_emac_tx_interval = TX_INTERVAL_DEFAULT; 130 131 enum sunxi_emac_type { 132 EMAC_A83T = 1, 133 EMAC_H3, 134 }; 135 136 static const struct of_compat_data compat_data[] = { 137 { "allwinner,sun8i-a83t-emac", EMAC_A83T }, 138 { "allwinner,sun8i-h3-emac", EMAC_H3 }, 139 { NULL } 140 }; 141 142 struct sunxi_emac_bufmap { 143 bus_dmamap_t map; 144 struct mbuf *mbuf; 145 }; 146 147 struct sunxi_emac_txring { 148 bus_dma_tag_t desc_tag; 149 bus_dmamap_t desc_map; 150 bus_dma_segment_t desc_dmaseg; 151 struct sunxi_emac_desc *desc_ring; 152 bus_addr_t desc_ring_paddr; 153 bus_dma_tag_t buf_tag; 154 struct sunxi_emac_bufmap buf_map[TX_DESC_COUNT]; 155 u_int cur, next, queued; 156 }; 157 158 struct sunxi_emac_rxring { 159 bus_dma_tag_t desc_tag; 160 bus_dmamap_t desc_map; 161 bus_dma_segment_t desc_dmaseg; 162 struct sunxi_emac_desc *desc_ring; 163 bus_addr_t desc_ring_paddr; 164 bus_dma_tag_t buf_tag; 165 struct sunxi_emac_bufmap buf_map[RX_DESC_COUNT]; 166 u_int cur; 167 }; 168 169 enum { 170 _RES_EMAC, 171 _RES_SYSCON, 172 _RES_NITEMS 173 }; 174 175 struct sunxi_emac_softc { 176 device_t dev; 177 int phandle; 178 enum sunxi_emac_type type; 179 bus_space_tag_t bst; 180 bus_dma_tag_t dmat; 181 182 bus_space_handle_t bsh[_RES_NITEMS]; 183 struct clk *clk_ahb; 184 struct clk *clk_ephy; 185 struct fdtbus_reset *rst_ahb; 186 struct fdtbus_reset *rst_ephy; 187 struct fdtbus_regulator *reg_phy; 188 struct fdtbus_gpio_pin *pin_reset; 189 190 kmutex_t mtx; 191 struct ethercom ec; 192 struct mii_data mii; 193 callout_t stat_ch; 194 void *ih; 195 u_int mdc_div_ratio_m; 196 197 struct sunxi_emac_txring tx; 198 struct sunxi_emac_rxring rx; 199 }; 200 201 #define RD4(sc, reg) \ 202 bus_space_read_4((sc)->bst, (sc)->bsh[_RES_EMAC], (reg)) 203 #define WR4(sc, reg, val) \ 204 bus_space_write_4((sc)->bst, (sc)->bsh[_RES_EMAC], (reg), (val)) 205 206 #define SYSCONRD4(sc, reg) \ 207 bus_space_read_4((sc)->bst, (sc)->bsh[_RES_SYSCON], (reg)) 208 #define SYSCONWR4(sc, reg, val) \ 209 bus_space_write_4((sc)->bst, (sc)->bsh[_RES_SYSCON], (reg), (val)) 210 211 static int 212 sunxi_emac_mii_readreg(device_t dev, int phy, int reg) 213 { 214 struct sunxi_emac_softc *sc = device_private(dev); 215 int retry, val; 216 217 val = 0; 218 219 WR4(sc, EMAC_MII_CMD, 220 (sc->mdc_div_ratio_m << MDC_DIV_RATIO_M_SHIFT) | 221 (phy << PHY_ADDR_SHIFT) | 222 (reg << PHY_REG_ADDR_SHIFT) | 223 MII_BUSY); 224 for (retry = MII_BUSY_RETRY; retry > 0; retry--) { 225 if ((RD4(sc, EMAC_MII_CMD) & MII_BUSY) == 0) { 226 val = RD4(sc, EMAC_MII_DATA); 227 break; 228 } 229 delay(10); 230 } 231 232 if (retry == 0) 233 device_printf(dev, "phy read timeout, phy=%d reg=%d\n", 234 phy, reg); 235 236 return val; 237 } 238 239 static void 240 sunxi_emac_mii_writereg(device_t dev, int phy, int reg, int val) 241 { 242 struct sunxi_emac_softc *sc = device_private(dev); 243 int retry; 244 245 WR4(sc, EMAC_MII_DATA, val); 246 WR4(sc, EMAC_MII_CMD, 247 (sc->mdc_div_ratio_m << MDC_DIV_RATIO_M_SHIFT) | 248 (phy << PHY_ADDR_SHIFT) | 249 (reg << PHY_REG_ADDR_SHIFT) | 250 MII_WR | MII_BUSY); 251 for (retry = MII_BUSY_RETRY; retry > 0; retry--) { 252 if ((RD4(sc, EMAC_MII_CMD) & MII_BUSY) == 0) 253 break; 254 delay(10); 255 } 256 257 if (retry == 0) 258 device_printf(dev, "phy write timeout, phy=%d reg=%d\n", 259 phy, reg); 260 } 261 262 static void 263 sunxi_emac_update_link(struct sunxi_emac_softc *sc) 264 { 265 struct mii_data *mii = &sc->mii; 266 uint32_t val; 267 268 val = RD4(sc, EMAC_BASIC_CTL_0); 269 val &= ~(BASIC_CTL_SPEED | BASIC_CTL_DUPLEX); 270 271 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 272 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 273 val |= BASIC_CTL_SPEED_1000 << BASIC_CTL_SPEED_SHIFT; 274 else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) 275 val |= BASIC_CTL_SPEED_100 << BASIC_CTL_SPEED_SHIFT; 276 else 277 val |= BASIC_CTL_SPEED_10 << BASIC_CTL_SPEED_SHIFT; 278 279 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 280 val |= BASIC_CTL_DUPLEX; 281 282 WR4(sc, EMAC_BASIC_CTL_0, val); 283 284 val = RD4(sc, EMAC_RX_CTL_0); 285 val &= ~RX_FLOW_CTL_EN; 286 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 287 val |= RX_FLOW_CTL_EN; 288 WR4(sc, EMAC_RX_CTL_0, val); 289 290 val = RD4(sc, EMAC_TX_FLOW_CTL); 291 val &= ~(PAUSE_TIME|TX_FLOW_CTL_EN); 292 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 293 val |= TX_FLOW_CTL_EN; 294 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 295 val |= sunxi_emac_pause_time << PAUSE_TIME_SHIFT; 296 WR4(sc, EMAC_TX_FLOW_CTL, val); 297 } 298 299 static void 300 sunxi_emac_mii_statchg(struct ifnet *ifp) 301 { 302 struct sunxi_emac_softc * const sc = ifp->if_softc; 303 304 sunxi_emac_update_link(sc); 305 } 306 307 static void 308 sunxi_emac_dma_sync(struct sunxi_emac_softc *sc, bus_dma_tag_t dmat, 309 bus_dmamap_t map, int start, int end, int total, int flags) 310 { 311 if (end > start) { 312 bus_dmamap_sync(dmat, map, DESC_OFF(start), 313 DESC_OFF(end) - DESC_OFF(start), flags); 314 } else { 315 bus_dmamap_sync(dmat, map, DESC_OFF(start), 316 DESC_OFF(total) - DESC_OFF(start), flags); 317 if (DESC_OFF(end) - DESC_OFF(0) > 0) 318 bus_dmamap_sync(dmat, map, DESC_OFF(0), 319 DESC_OFF(end) - DESC_OFF(0), flags); 320 } 321 } 322 323 static void 324 sunxi_emac_setup_txdesc(struct sunxi_emac_softc *sc, int index, int flags, 325 bus_addr_t paddr, u_int len) 326 { 327 uint32_t status, size; 328 329 if (paddr == 0 || len == 0) { 330 status = 0; 331 size = 0; 332 --sc->tx.queued; 333 } else { 334 status = TX_DESC_CTL; 335 size = flags | len; 336 if ((index & (sunxi_emac_tx_interval - 1)) == 0) 337 size |= TX_INT_CTL; 338 ++sc->tx.queued; 339 } 340 341 sc->tx.desc_ring[index].addr = htole32((uint32_t)paddr); 342 sc->tx.desc_ring[index].size = htole32(size); 343 sc->tx.desc_ring[index].status = htole32(status); 344 } 345 346 static int 347 sunxi_emac_setup_txbuf(struct sunxi_emac_softc *sc, int index, struct mbuf *m) 348 { 349 bus_dma_segment_t *segs; 350 int error, nsegs, cur, i, flags; 351 u_int csum_flags; 352 353 error = bus_dmamap_load_mbuf(sc->tx.buf_tag, 354 sc->tx.buf_map[index].map, m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 355 if (error == EFBIG) { 356 device_printf(sc->dev, 357 "TX packet needs too many DMA segments, dropping...\n"); 358 m_freem(m); 359 return 0; 360 } 361 if (error != 0) 362 return 0; 363 364 segs = sc->tx.buf_map[index].map->dm_segs; 365 nsegs = sc->tx.buf_map[index].map->dm_nsegs; 366 367 flags = TX_FIR_DESC; 368 if ((m->m_pkthdr.csum_flags & M_CSUM_IPv4) != 0) { 369 if ((m->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) != 0) 370 csum_flags = TX_CHECKSUM_CTL_FULL; 371 else 372 csum_flags = TX_CHECKSUM_CTL_IP; 373 flags |= (csum_flags << TX_CHECKSUM_CTL_SHIFT); 374 } 375 376 for (cur = index, i = 0; i < nsegs; i++) { 377 sc->tx.buf_map[cur].mbuf = (i == 0 ? m : NULL); 378 if (i == nsegs - 1) 379 flags |= TX_LAST_DESC; 380 381 sunxi_emac_setup_txdesc(sc, cur, flags, segs[i].ds_addr, 382 segs[i].ds_len); 383 flags &= ~TX_FIR_DESC; 384 cur = TX_NEXT(cur); 385 } 386 387 bus_dmamap_sync(sc->tx.buf_tag, sc->tx.buf_map[index].map, 388 0, sc->tx.buf_map[index].map->dm_mapsize, BUS_DMASYNC_PREWRITE); 389 390 return nsegs; 391 } 392 393 static void 394 sunxi_emac_setup_rxdesc(struct sunxi_emac_softc *sc, int index, 395 bus_addr_t paddr) 396 { 397 uint32_t status, size; 398 399 status = RX_DESC_CTL; 400 size = MCLBYTES - 1; 401 402 sc->rx.desc_ring[index].addr = htole32((uint32_t)paddr); 403 sc->rx.desc_ring[index].size = htole32(size); 404 sc->rx.desc_ring[index].next = 405 htole32(sc->rx.desc_ring_paddr + DESC_OFF(RX_NEXT(index))); 406 sc->rx.desc_ring[index].status = htole32(status); 407 } 408 409 static int 410 sunxi_emac_setup_rxbuf(struct sunxi_emac_softc *sc, int index, struct mbuf *m) 411 { 412 int error; 413 414 m_adj(m, ETHER_ALIGN); 415 416 error = bus_dmamap_load_mbuf(sc->rx.buf_tag, 417 sc->rx.buf_map[index].map, m, BUS_DMA_READ|BUS_DMA_NOWAIT); 418 if (error != 0) 419 return error; 420 421 bus_dmamap_sync(sc->rx.buf_tag, sc->rx.buf_map[index].map, 422 0, sc->rx.buf_map[index].map->dm_mapsize, 423 BUS_DMASYNC_PREREAD); 424 425 sc->rx.buf_map[index].mbuf = m; 426 sunxi_emac_setup_rxdesc(sc, index, 427 sc->rx.buf_map[index].map->dm_segs[0].ds_addr); 428 429 return 0; 430 } 431 432 static struct mbuf * 433 sunxi_emac_alloc_mbufcl(struct sunxi_emac_softc *sc) 434 { 435 struct mbuf *m; 436 437 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 438 if (m != NULL) 439 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 440 441 return m; 442 } 443 444 static void 445 sunxi_emac_start_locked(struct sunxi_emac_softc *sc) 446 { 447 struct ifnet *ifp = &sc->ec.ec_if; 448 struct mbuf *m; 449 uint32_t val; 450 int cnt, nsegs, start; 451 452 EMAC_ASSERT_LOCKED(sc); 453 454 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 455 return; 456 457 for (cnt = 0, start = sc->tx.cur; ; cnt++) { 458 if (sc->tx.queued >= TX_DESC_COUNT - TX_MAX_SEGS) { 459 ifp->if_flags |= IFF_OACTIVE; 460 break; 461 } 462 463 IFQ_POLL(&ifp->if_snd, m); 464 if (m == NULL) 465 break; 466 467 nsegs = sunxi_emac_setup_txbuf(sc, sc->tx.cur, m); 468 if (nsegs == 0) { 469 ifp->if_flags |= IFF_OACTIVE; 470 break; 471 } 472 IFQ_DEQUEUE(&ifp->if_snd, m); 473 bpf_mtap(ifp, m); 474 475 sc->tx.cur = TX_SKIP(sc->tx.cur, nsegs); 476 } 477 478 if (cnt != 0) { 479 sunxi_emac_dma_sync(sc, sc->tx.desc_tag, sc->tx.desc_map, 480 start, sc->tx.cur, TX_DESC_COUNT, 481 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 482 483 /* Start and run TX DMA */ 484 val = RD4(sc, EMAC_TX_CTL_1); 485 WR4(sc, EMAC_TX_CTL_1, val | TX_DMA_START); 486 } 487 } 488 489 static void 490 sunxi_emac_start(struct ifnet *ifp) 491 { 492 struct sunxi_emac_softc *sc = ifp->if_softc; 493 494 EMAC_LOCK(sc); 495 sunxi_emac_start_locked(sc); 496 EMAC_UNLOCK(sc); 497 } 498 499 static void 500 sunxi_emac_tick(void *softc) 501 { 502 struct sunxi_emac_softc *sc = softc; 503 struct mii_data *mii = &sc->mii; 504 #ifndef EMAC_MPSAFE 505 int s = splnet(); 506 #endif 507 508 EMAC_LOCK(sc); 509 mii_tick(mii); 510 callout_schedule(&sc->stat_ch, hz); 511 EMAC_UNLOCK(sc); 512 513 #ifndef EMAC_MPSAFE 514 splx(s); 515 #endif 516 } 517 518 /* Bit Reversal - http://aggregate.org/MAGIC/#Bit%20Reversal */ 519 static uint32_t 520 bitrev32(uint32_t x) 521 { 522 x = (((x & 0xaaaaaaaa) >> 1) | ((x & 0x55555555) << 1)); 523 x = (((x & 0xcccccccc) >> 2) | ((x & 0x33333333) << 2)); 524 x = (((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4)); 525 x = (((x & 0xff00ff00) >> 8) | ((x & 0x00ff00ff) << 8)); 526 527 return (x >> 16) | (x << 16); 528 } 529 530 static void 531 sunxi_emac_setup_rxfilter(struct sunxi_emac_softc *sc) 532 { 533 struct ifnet *ifp = &sc->ec.ec_if; 534 uint32_t val, crc, hashreg, hashbit, hash[2], machi, maclo; 535 struct ether_multi *enm; 536 struct ether_multistep step; 537 const uint8_t *eaddr; 538 539 EMAC_ASSERT_LOCKED(sc); 540 541 val = 0; 542 hash[0] = hash[1] = 0; 543 544 if ((ifp->if_flags & IFF_PROMISC) != 0) 545 val |= DIS_ADDR_FILTER; 546 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 547 val |= RX_ALL_MULTICAST; 548 hash[0] = hash[1] = ~0; 549 } else { 550 val |= HASH_MULTICAST; 551 ETHER_FIRST_MULTI(step, &sc->ec, enm); 552 while (enm != NULL) { 553 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 554 crc &= 0x7f; 555 crc = bitrev32(~crc) >> 26; 556 hashreg = (crc >> 5); 557 hashbit = (crc & 0x1f); 558 hash[hashreg] |= (1 << hashbit); 559 ETHER_NEXT_MULTI(step, enm); 560 } 561 } 562 563 /* Write our unicast address */ 564 eaddr = CLLADDR(ifp->if_sadl); 565 machi = (eaddr[5] << 8) | eaddr[4]; 566 maclo = (eaddr[3] << 24) | (eaddr[2] << 16) | (eaddr[1] << 8) | 567 (eaddr[0] << 0); 568 WR4(sc, EMAC_ADDR_HIGH(0), machi); 569 WR4(sc, EMAC_ADDR_LOW(0), maclo); 570 571 /* Multicast hash filters */ 572 WR4(sc, EMAC_RX_HASH_0, hash[1]); 573 WR4(sc, EMAC_RX_HASH_1, hash[0]); 574 575 /* RX frame filter config */ 576 WR4(sc, EMAC_RX_FRM_FLT, val); 577 } 578 579 static void 580 sunxi_emac_enable_intr(struct sunxi_emac_softc *sc) 581 { 582 /* Enable interrupts */ 583 WR4(sc, EMAC_INT_EN, RX_INT_EN | TX_INT_EN | TX_BUF_UA_INT_EN); 584 } 585 586 static void 587 sunxi_emac_disable_intr(struct sunxi_emac_softc *sc) 588 { 589 /* Disable interrupts */ 590 WR4(sc, EMAC_INT_EN, 0); 591 } 592 593 static int 594 sunxi_emac_init_locked(struct sunxi_emac_softc *sc) 595 { 596 struct ifnet *ifp = &sc->ec.ec_if; 597 struct mii_data *mii = &sc->mii; 598 uint32_t val; 599 600 EMAC_ASSERT_LOCKED(sc); 601 602 if ((ifp->if_flags & IFF_RUNNING) != 0) 603 return 0; 604 605 sunxi_emac_setup_rxfilter(sc); 606 607 /* Configure DMA burst length and priorities */ 608 val = sunxi_emac_burst_len << BASIC_CTL_BURST_LEN_SHIFT; 609 if (sunxi_emac_rx_tx_pri) 610 val |= BASIC_CTL_RX_TX_PRI; 611 WR4(sc, EMAC_BASIC_CTL_1, val); 612 613 /* Enable interrupts */ 614 sunxi_emac_enable_intr(sc); 615 616 /* Enable transmit DMA */ 617 val = RD4(sc, EMAC_TX_CTL_1); 618 WR4(sc, EMAC_TX_CTL_1, val | TX_DMA_EN | TX_MD | TX_NEXT_FRAME); 619 620 /* Enable receive DMA */ 621 val = RD4(sc, EMAC_RX_CTL_1); 622 WR4(sc, EMAC_RX_CTL_1, val | RX_DMA_EN | RX_MD); 623 624 /* Enable transmitter */ 625 val = RD4(sc, EMAC_TX_CTL_0); 626 WR4(sc, EMAC_TX_CTL_0, val | TX_EN); 627 628 /* Enable receiver */ 629 val = RD4(sc, EMAC_RX_CTL_0); 630 WR4(sc, EMAC_RX_CTL_0, val | RX_EN | CHECK_CRC); 631 632 ifp->if_flags |= IFF_RUNNING; 633 ifp->if_flags &= ~IFF_OACTIVE; 634 635 mii_mediachg(mii); 636 callout_schedule(&sc->stat_ch, hz); 637 638 return 0; 639 } 640 641 static int 642 sunxi_emac_init(struct ifnet *ifp) 643 { 644 struct sunxi_emac_softc *sc = ifp->if_softc; 645 int error; 646 647 EMAC_LOCK(sc); 648 error = sunxi_emac_init_locked(sc); 649 EMAC_UNLOCK(sc); 650 651 return error; 652 } 653 654 static void 655 sunxi_emac_stop_locked(struct sunxi_emac_softc *sc, int disable) 656 { 657 struct ifnet *ifp = &sc->ec.ec_if; 658 uint32_t val; 659 660 EMAC_ASSERT_LOCKED(sc); 661 662 callout_stop(&sc->stat_ch); 663 664 mii_down(&sc->mii); 665 666 /* Stop transmit DMA and flush data in the TX FIFO */ 667 val = RD4(sc, EMAC_TX_CTL_1); 668 val &= ~TX_DMA_EN; 669 val |= FLUSH_TX_FIFO; 670 WR4(sc, EMAC_TX_CTL_1, val); 671 672 /* Disable transmitter */ 673 val = RD4(sc, EMAC_TX_CTL_0); 674 WR4(sc, EMAC_TX_CTL_0, val & ~TX_EN); 675 676 /* Disable receiver */ 677 val = RD4(sc, EMAC_RX_CTL_0); 678 WR4(sc, EMAC_RX_CTL_0, val & ~RX_EN); 679 680 /* Disable interrupts */ 681 sunxi_emac_disable_intr(sc); 682 683 /* Disable transmit DMA */ 684 val = RD4(sc, EMAC_TX_CTL_1); 685 WR4(sc, EMAC_TX_CTL_1, val & ~TX_DMA_EN); 686 687 /* Disable receive DMA */ 688 val = RD4(sc, EMAC_RX_CTL_1); 689 WR4(sc, EMAC_RX_CTL_1, val & ~RX_DMA_EN); 690 691 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 692 } 693 694 static void 695 sunxi_emac_stop(struct ifnet *ifp, int disable) 696 { 697 struct sunxi_emac_softc * const sc = ifp->if_softc; 698 699 EMAC_LOCK(sc); 700 sunxi_emac_stop_locked(sc, disable); 701 EMAC_UNLOCK(sc); 702 } 703 704 static int 705 sunxi_emac_rxintr(struct sunxi_emac_softc *sc) 706 { 707 struct ifnet *ifp = &sc->ec.ec_if; 708 int error, index, len, npkt; 709 struct mbuf *m, *m0; 710 uint32_t status; 711 712 npkt = 0; 713 714 for (index = sc->rx.cur; ; index = RX_NEXT(index)) { 715 sunxi_emac_dma_sync(sc, sc->rx.desc_tag, sc->rx.desc_map, 716 index, index + 1, 717 RX_DESC_COUNT, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 718 719 status = le32toh(sc->rx.desc_ring[index].status); 720 if ((status & RX_DESC_CTL) != 0) 721 break; 722 723 bus_dmamap_sync(sc->rx.buf_tag, sc->rx.buf_map[index].map, 724 0, sc->rx.buf_map[index].map->dm_mapsize, 725 BUS_DMASYNC_POSTREAD); 726 bus_dmamap_unload(sc->rx.buf_tag, sc->rx.buf_map[index].map); 727 728 len = (status & RX_FRM_LEN) >> RX_FRM_LEN_SHIFT; 729 if (len != 0) { 730 m = sc->rx.buf_map[index].mbuf; 731 m_set_rcvif(m, ifp); 732 m->m_flags |= M_HASFCS; 733 m->m_pkthdr.len = len; 734 m->m_len = len; 735 m->m_nextpkt = NULL; 736 737 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) != 0 && 738 (status & RX_FRM_TYPE) != 0) { 739 m->m_pkthdr.csum_flags = M_CSUM_IPv4; 740 if ((status & RX_HEADER_ERR) != 0) 741 m->m_pkthdr.csum_flags |= 742 M_CSUM_IPv4_BAD; 743 if ((status & RX_PAYLOAD_ERR) == 0) { 744 m->m_pkthdr.csum_flags |= 745 M_CSUM_DATA; 746 m->m_pkthdr.csum_data = 0xffff; 747 } 748 } 749 750 ++npkt; 751 752 if_percpuq_enqueue(ifp->if_percpuq, m); 753 } 754 755 if ((m0 = sunxi_emac_alloc_mbufcl(sc)) != NULL) { 756 error = sunxi_emac_setup_rxbuf(sc, index, m0); 757 if (error != 0) { 758 /* XXX hole in RX ring */ 759 } 760 } else 761 ifp->if_ierrors++; 762 763 sunxi_emac_dma_sync(sc, sc->rx.desc_tag, sc->rx.desc_map, 764 index, index + 1, 765 RX_DESC_COUNT, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 766 } 767 768 sc->rx.cur = index; 769 770 return npkt; 771 } 772 773 static void 774 sunxi_emac_txintr(struct sunxi_emac_softc *sc) 775 { 776 struct ifnet *ifp = &sc->ec.ec_if; 777 struct sunxi_emac_bufmap *bmap; 778 struct sunxi_emac_desc *desc; 779 uint32_t status; 780 int i; 781 782 EMAC_ASSERT_LOCKED(sc); 783 784 for (i = sc->tx.next; sc->tx.queued > 0; i = TX_NEXT(i)) { 785 KASSERT(sc->tx.queued > 0 && sc->tx.queued <= TX_DESC_COUNT); 786 sunxi_emac_dma_sync(sc, sc->tx.desc_tag, sc->tx.desc_map, 787 i, i + 1, TX_DESC_COUNT, 788 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 789 desc = &sc->tx.desc_ring[i]; 790 status = le32toh(desc->status); 791 if ((status & TX_DESC_CTL) != 0) 792 break; 793 bmap = &sc->tx.buf_map[i]; 794 if (bmap->mbuf != NULL) { 795 bus_dmamap_sync(sc->tx.buf_tag, bmap->map, 796 0, bmap->map->dm_mapsize, 797 BUS_DMASYNC_POSTWRITE); 798 bus_dmamap_unload(sc->tx.buf_tag, bmap->map); 799 m_freem(bmap->mbuf); 800 bmap->mbuf = NULL; 801 } 802 803 sunxi_emac_setup_txdesc(sc, i, 0, 0, 0); 804 sunxi_emac_dma_sync(sc, sc->tx.desc_tag, sc->tx.desc_map, 805 i, i + 1, TX_DESC_COUNT, 806 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 807 808 ifp->if_flags &= ~IFF_OACTIVE; 809 ifp->if_opackets++; 810 } 811 812 sc->tx.next = i; 813 } 814 815 static int 816 sunxi_emac_intr(void *arg) 817 { 818 struct sunxi_emac_softc *sc = arg; 819 struct ifnet *ifp = &sc->ec.ec_if; 820 uint32_t val; 821 822 EMAC_LOCK(sc); 823 824 val = RD4(sc, EMAC_INT_STA); 825 WR4(sc, EMAC_INT_STA, val); 826 827 if (val & RX_INT) 828 sunxi_emac_rxintr(sc); 829 830 if (val & (TX_INT|TX_BUF_UA_INT)) { 831 sunxi_emac_txintr(sc); 832 if_schedule_deferred_start(ifp); 833 } 834 835 EMAC_UNLOCK(sc); 836 837 return 1; 838 } 839 840 static int 841 sunxi_emac_ioctl(struct ifnet *ifp, u_long cmd, void *data) 842 { 843 struct sunxi_emac_softc *sc = ifp->if_softc; 844 struct mii_data *mii = &sc->mii; 845 struct ifreq *ifr = data; 846 int error, s; 847 848 #ifndef EMAC_MPSAFE 849 s = splnet(); 850 #endif 851 852 switch (cmd) { 853 case SIOCSIFMEDIA: 854 case SIOCGIFMEDIA: 855 #ifdef EMAC_MPSAFE 856 s = splnet(); 857 #endif 858 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 859 #ifdef EMAC_MPSAFE 860 splx(s); 861 #endif 862 break; 863 default: 864 #ifdef EMAC_MPSAFE 865 s = splnet(); 866 #endif 867 error = ether_ioctl(ifp, cmd, data); 868 #ifdef EMAC_MPSAFE 869 splx(s); 870 #endif 871 if (error != ENETRESET) 872 break; 873 874 error = 0; 875 876 if (cmd == SIOCSIFCAP) 877 error = (*ifp->if_init)(ifp); 878 else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 879 ; 880 else if ((ifp->if_flags & IFF_RUNNING) != 0) { 881 EMAC_LOCK(sc); 882 sunxi_emac_setup_rxfilter(sc); 883 EMAC_UNLOCK(sc); 884 } 885 break; 886 } 887 888 #ifndef EMAC_MPSAFE 889 splx(s); 890 #endif 891 892 return error; 893 } 894 895 static int 896 sunxi_emac_setup_phy(struct sunxi_emac_softc *sc) 897 { 898 uint32_t reg, tx_delay, rx_delay; 899 const char *phy_type; 900 901 phy_type = fdtbus_get_string(sc->phandle, "phy-mode"); 902 if (phy_type == NULL) 903 return 0; 904 905 aprint_debug_dev(sc->dev, "PHY type: %s\n", phy_type); 906 907 reg = SYSCONRD4(sc, 0); 908 909 reg &= ~(EMAC_CLK_PIT | EMAC_CLK_SRC | EMAC_CLK_RMII_EN); 910 if (strcmp(phy_type, "rgmii") == 0) 911 reg |= EMAC_CLK_PIT_RGMII | EMAC_CLK_SRC_RGMII; 912 else if (strcmp(phy_type, "rmii") == 0) 913 reg |= EMAC_CLK_RMII_EN; 914 else 915 reg |= EMAC_CLK_PIT_MII | EMAC_CLK_SRC_MII; 916 917 if (of_getprop_uint32(sc->phandle, "tx-delay", &tx_delay) == 0) { 918 reg &= ~EMAC_CLK_ETXDC; 919 reg |= (tx_delay << EMAC_CLK_ETXDC_SHIFT); 920 } 921 if (of_getprop_uint32(sc->phandle, "rx-delay", &rx_delay) == 0) { 922 reg &= ~EMAC_CLK_ERXDC; 923 reg |= (rx_delay << EMAC_CLK_ERXDC_SHIFT); 924 } 925 926 if (sc->type == EMAC_H3) { 927 if (of_hasprop(sc->phandle, "allwinner,use-internal-phy")) { 928 reg |= EMAC_CLK_EPHY_SELECT; 929 reg &= ~EMAC_CLK_EPHY_SHUTDOWN; 930 if (of_hasprop(sc->phandle, 931 "allwinner,leds-active-low")) 932 reg |= EMAC_CLK_EPHY_LED_POL; 933 else 934 reg &= ~EMAC_CLK_EPHY_LED_POL; 935 936 /* Set internal PHY addr to 1 */ 937 reg &= ~EMAC_CLK_EPHY_ADDR; 938 reg |= (1 << EMAC_CLK_EPHY_ADDR_SHIFT); 939 } else { 940 reg &= ~EMAC_CLK_EPHY_SELECT; 941 } 942 } 943 944 aprint_debug_dev(sc->dev, "EMAC clock: 0x%08x\n", reg); 945 946 SYSCONWR4(sc, 0, reg); 947 948 return 0; 949 } 950 951 static int 952 sunxi_emac_setup_resources(struct sunxi_emac_softc *sc) 953 { 954 u_int freq; 955 int error, div; 956 957 /* Configure PHY for MII or RGMII mode */ 958 if (sunxi_emac_setup_phy(sc) != 0) 959 return ENXIO; 960 961 /* Enable clocks */ 962 error = clk_enable(sc->clk_ahb); 963 if (error != 0) { 964 aprint_error_dev(sc->dev, "cannot enable ahb clock\n"); 965 return error; 966 } 967 968 if (sc->clk_ephy != NULL) { 969 error = clk_enable(sc->clk_ephy); 970 if (error != 0) { 971 aprint_error_dev(sc->dev, "cannot enable ephy clock\n"); 972 return error; 973 } 974 } 975 976 /* De-assert reset */ 977 error = fdtbus_reset_deassert(sc->rst_ahb); 978 if (error != 0) { 979 aprint_error_dev(sc->dev, "cannot de-assert ahb reset\n"); 980 return error; 981 } 982 if (sc->rst_ephy != NULL) { 983 error = fdtbus_reset_deassert(sc->rst_ephy); 984 if (error != 0) { 985 aprint_error_dev(sc->dev, 986 "cannot de-assert ephy reset\n"); 987 return error; 988 } 989 } 990 991 /* Enable PHY regulator if applicable */ 992 if (sc->reg_phy != NULL) { 993 error = fdtbus_regulator_enable(sc->reg_phy); 994 if (error != 0) { 995 aprint_error_dev(sc->dev, 996 "cannot enable PHY regulator\n"); 997 return error; 998 } 999 } 1000 1001 /* Determine MDC clock divide ratio based on AHB clock */ 1002 freq = clk_get_rate(sc->clk_ahb); 1003 if (freq == 0) { 1004 aprint_error_dev(sc->dev, "cannot get AHB clock frequency\n"); 1005 return ENXIO; 1006 } 1007 div = freq / MDIO_FREQ; 1008 if (div <= 16) 1009 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_16; 1010 else if (div <= 32) 1011 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_32; 1012 else if (div <= 64) 1013 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_64; 1014 else if (div <= 128) 1015 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_128; 1016 else { 1017 aprint_error_dev(sc->dev, 1018 "cannot determine MDC clock divide ratio\n"); 1019 return ENXIO; 1020 } 1021 1022 aprint_debug_dev(sc->dev, "AHB frequency %u Hz, MDC div: 0x%x\n", 1023 freq, sc->mdc_div_ratio_m); 1024 1025 return 0; 1026 } 1027 1028 static void 1029 sunxi_emac_get_eaddr(struct sunxi_emac_softc *sc, uint8_t *eaddr) 1030 { 1031 uint32_t maclo, machi; 1032 #if notyet 1033 u_char rootkey[16]; 1034 #endif 1035 1036 machi = RD4(sc, EMAC_ADDR_HIGH(0)) & 0xffff; 1037 maclo = RD4(sc, EMAC_ADDR_LOW(0)); 1038 1039 if (maclo == 0xffffffff && machi == 0xffff) { 1040 #if notyet 1041 /* MAC address in hardware is invalid, create one */ 1042 if (aw_sid_get_rootkey(rootkey) == 0 && 1043 (rootkey[3] | rootkey[12] | rootkey[13] | rootkey[14] | 1044 rootkey[15]) != 0) { 1045 /* MAC address is derived from the root key in SID */ 1046 maclo = (rootkey[13] << 24) | (rootkey[12] << 16) | 1047 (rootkey[3] << 8) | 0x02; 1048 machi = (rootkey[15] << 8) | rootkey[14]; 1049 } else { 1050 #endif 1051 /* Create one */ 1052 maclo = 0x00f2 | (cprng_strong32() & 0xffff0000); 1053 machi = cprng_strong32() & 0xffff; 1054 #if notyet 1055 } 1056 #endif 1057 } 1058 1059 eaddr[0] = maclo & 0xff; 1060 eaddr[1] = (maclo >> 8) & 0xff; 1061 eaddr[2] = (maclo >> 16) & 0xff; 1062 eaddr[3] = (maclo >> 24) & 0xff; 1063 eaddr[4] = machi & 0xff; 1064 eaddr[5] = (machi >> 8) & 0xff; 1065 } 1066 1067 #ifdef SUNXI_EMAC_DEBUG 1068 static void 1069 sunxi_emac_dump_regs(struct sunxi_emac_softc *sc) 1070 { 1071 static const struct { 1072 const char *name; 1073 u_int reg; 1074 } regs[] = { 1075 { "BASIC_CTL_0", EMAC_BASIC_CTL_0 }, 1076 { "BASIC_CTL_1", EMAC_BASIC_CTL_1 }, 1077 { "INT_STA", EMAC_INT_STA }, 1078 { "INT_EN", EMAC_INT_EN }, 1079 { "TX_CTL_0", EMAC_TX_CTL_0 }, 1080 { "TX_CTL_1", EMAC_TX_CTL_1 }, 1081 { "TX_FLOW_CTL", EMAC_TX_FLOW_CTL }, 1082 { "TX_DMA_LIST", EMAC_TX_DMA_LIST }, 1083 { "RX_CTL_0", EMAC_RX_CTL_0 }, 1084 { "RX_CTL_1", EMAC_RX_CTL_1 }, 1085 { "RX_DMA_LIST", EMAC_RX_DMA_LIST }, 1086 { "RX_FRM_FLT", EMAC_RX_FRM_FLT }, 1087 { "RX_HASH_0", EMAC_RX_HASH_0 }, 1088 { "RX_HASH_1", EMAC_RX_HASH_1 }, 1089 { "MII_CMD", EMAC_MII_CMD }, 1090 { "ADDR_HIGH0", EMAC_ADDR_HIGH(0) }, 1091 { "ADDR_LOW0", EMAC_ADDR_LOW(0) }, 1092 { "TX_DMA_STA", EMAC_TX_DMA_STA }, 1093 { "TX_DMA_CUR_DESC", EMAC_TX_DMA_CUR_DESC }, 1094 { "TX_DMA_CUR_BUF", EMAC_TX_DMA_CUR_BUF }, 1095 { "RX_DMA_STA", EMAC_RX_DMA_STA }, 1096 { "RX_DMA_CUR_DESC", EMAC_RX_DMA_CUR_DESC }, 1097 { "RX_DMA_CUR_BUF", EMAC_RX_DMA_CUR_BUF }, 1098 { "RGMII_STA", EMAC_RGMII_STA }, 1099 }; 1100 u_int n; 1101 1102 for (n = 0; n < __arraycount(regs); n++) 1103 device_printf(dev, " %-20s %08x\n", regs[n].name, 1104 RD4(sc, regs[n].reg)); 1105 } 1106 #endif 1107 1108 static int 1109 sunxi_emac_phy_reset(struct sunxi_emac_softc *sc) 1110 { 1111 uint32_t delay_prop[3]; 1112 int pin_value; 1113 1114 if (sc->pin_reset == NULL) 1115 return 0; 1116 1117 if (OF_getprop(sc->phandle, "allwinner,reset-delays-us", delay_prop, 1118 sizeof(delay_prop)) <= 0) 1119 return ENXIO; 1120 1121 pin_value = of_hasprop(sc->phandle, "allwinner,reset-active-low"); 1122 1123 fdtbus_gpio_write(sc->pin_reset, pin_value); 1124 delay(htole32(delay_prop[0])); 1125 fdtbus_gpio_write(sc->pin_reset, !pin_value); 1126 delay(htole32(delay_prop[1])); 1127 fdtbus_gpio_write(sc->pin_reset, pin_value); 1128 delay(htole32(delay_prop[2])); 1129 1130 return 0; 1131 } 1132 1133 static int 1134 sunxi_emac_reset(struct sunxi_emac_softc *sc) 1135 { 1136 int retry; 1137 1138 /* Reset PHY if necessary */ 1139 if (sunxi_emac_phy_reset(sc) != 0) { 1140 aprint_error_dev(sc->dev, "failed to reset PHY\n"); 1141 return ENXIO; 1142 } 1143 1144 /* Soft reset all registers and logic */ 1145 WR4(sc, EMAC_BASIC_CTL_1, BASIC_CTL_SOFT_RST); 1146 1147 /* Wait for soft reset bit to self-clear */ 1148 for (retry = SOFT_RST_RETRY; retry > 0; retry--) { 1149 if ((RD4(sc, EMAC_BASIC_CTL_1) & BASIC_CTL_SOFT_RST) == 0) 1150 break; 1151 delay(10); 1152 } 1153 if (retry == 0) { 1154 aprint_error_dev(sc->dev, "soft reset timed out\n"); 1155 #ifdef SUNXI_EMAC_DEBUG 1156 sunxi_emac_dump_regs(sc); 1157 #endif 1158 return ETIMEDOUT; 1159 } 1160 1161 return 0; 1162 } 1163 1164 static int 1165 sunxi_emac_setup_dma(struct sunxi_emac_softc *sc) 1166 { 1167 struct mbuf *m; 1168 int error, nsegs, i; 1169 1170 /* Setup TX ring */ 1171 sc->tx.buf_tag = sc->tx.desc_tag = sc->dmat; 1172 error = bus_dmamap_create(sc->dmat, TX_DESC_SIZE, 1, TX_DESC_SIZE, 0, 1173 BUS_DMA_WAITOK, &sc->tx.desc_map); 1174 if (error) 1175 return error; 1176 error = bus_dmamem_alloc(sc->dmat, TX_DESC_SIZE, DESC_ALIGN, 0, 1177 &sc->tx.desc_dmaseg, 1, &nsegs, BUS_DMA_WAITOK); 1178 if (error) 1179 return error; 1180 error = bus_dmamem_map(sc->dmat, &sc->tx.desc_dmaseg, nsegs, 1181 TX_DESC_SIZE, (void *)&sc->tx.desc_ring, 1182 BUS_DMA_WAITOK); 1183 if (error) 1184 return error; 1185 error = bus_dmamap_load(sc->dmat, sc->tx.desc_map, sc->tx.desc_ring, 1186 TX_DESC_SIZE, NULL, BUS_DMA_WAITOK); 1187 if (error) 1188 return error; 1189 sc->tx.desc_ring_paddr = sc->tx.desc_map->dm_segs[0].ds_addr; 1190 1191 memset(sc->tx.desc_ring, 0, TX_DESC_SIZE); 1192 bus_dmamap_sync(sc->dmat, sc->tx.desc_map, 0, TX_DESC_SIZE, 1193 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1194 1195 for (i = 0; i < TX_DESC_COUNT; i++) 1196 sc->tx.desc_ring[i].next = 1197 htole32(sc->tx.desc_ring_paddr + DESC_OFF(TX_NEXT(i))); 1198 1199 sc->tx.queued = TX_DESC_COUNT; 1200 for (i = 0; i < TX_DESC_COUNT; i++) { 1201 error = bus_dmamap_create(sc->tx.buf_tag, MCLBYTES, 1202 TX_MAX_SEGS, MCLBYTES, 0, BUS_DMA_WAITOK, 1203 &sc->tx.buf_map[i].map); 1204 if (error != 0) { 1205 device_printf(sc->dev, "cannot create TX buffer map\n"); 1206 return error; 1207 } 1208 sunxi_emac_setup_txdesc(sc, i, 0, 0, 0); 1209 } 1210 1211 /* Setup RX ring */ 1212 sc->rx.buf_tag = sc->rx.desc_tag = sc->dmat; 1213 error = bus_dmamap_create(sc->dmat, RX_DESC_SIZE, 1, RX_DESC_SIZE, 0, 1214 BUS_DMA_WAITOK, &sc->rx.desc_map); 1215 if (error) 1216 return error; 1217 error = bus_dmamem_alloc(sc->dmat, RX_DESC_SIZE, DESC_ALIGN, 0, 1218 &sc->rx.desc_dmaseg, 1, &nsegs, BUS_DMA_WAITOK); 1219 if (error) 1220 return error; 1221 error = bus_dmamem_map(sc->dmat, &sc->rx.desc_dmaseg, nsegs, 1222 RX_DESC_SIZE, (void *)&sc->rx.desc_ring, 1223 BUS_DMA_WAITOK); 1224 if (error) 1225 return error; 1226 error = bus_dmamap_load(sc->dmat, sc->rx.desc_map, sc->rx.desc_ring, 1227 RX_DESC_SIZE, NULL, BUS_DMA_WAITOK); 1228 if (error) 1229 return error; 1230 sc->rx.desc_ring_paddr = sc->rx.desc_map->dm_segs[0].ds_addr; 1231 1232 memset(sc->rx.desc_ring, 0, RX_DESC_SIZE); 1233 1234 for (i = 0; i < RX_DESC_COUNT; i++) { 1235 error = bus_dmamap_create(sc->rx.buf_tag, MCLBYTES, 1236 RX_DESC_COUNT, MCLBYTES, 0, BUS_DMA_WAITOK, 1237 &sc->rx.buf_map[i].map); 1238 if (error != 0) { 1239 device_printf(sc->dev, "cannot create RX buffer map\n"); 1240 return error; 1241 } 1242 if ((m = sunxi_emac_alloc_mbufcl(sc)) == NULL) { 1243 device_printf(sc->dev, "cannot allocate RX mbuf\n"); 1244 return ENOMEM; 1245 } 1246 error = sunxi_emac_setup_rxbuf(sc, i, m); 1247 if (error != 0) { 1248 device_printf(sc->dev, "cannot create RX buffer\n"); 1249 return error; 1250 } 1251 } 1252 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map, 1253 0, sc->rx.desc_map->dm_mapsize, 1254 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1255 1256 /* Write transmit and receive descriptor base address registers */ 1257 WR4(sc, EMAC_TX_DMA_LIST, sc->tx.desc_ring_paddr); 1258 WR4(sc, EMAC_RX_DMA_LIST, sc->rx.desc_ring_paddr); 1259 1260 return 0; 1261 } 1262 1263 static int 1264 sunxi_emac_get_resources(struct sunxi_emac_softc *sc) 1265 { 1266 const int phandle = sc->phandle; 1267 bus_addr_t addr, size; 1268 u_int n; 1269 1270 /* Map registers */ 1271 for (n = 0; n < _RES_NITEMS; n++) { 1272 if (fdtbus_get_reg(phandle, n, &addr, &size) != 0) 1273 return ENXIO; 1274 if (bus_space_map(sc->bst, addr, size, 0, &sc->bsh[n]) != 0) 1275 return ENXIO; 1276 } 1277 1278 /* Get clocks and resets. "ahb" is required, "ephy" is optional. */ 1279 1280 if ((sc->clk_ahb = fdtbus_clock_get(phandle, "ahb")) == NULL) 1281 return ENXIO; 1282 sc->clk_ephy = fdtbus_clock_get(phandle, "ephy"); 1283 1284 if ((sc->rst_ahb = fdtbus_reset_get(phandle, "ahb")) == NULL) 1285 return ENXIO; 1286 sc->rst_ahb = fdtbus_reset_get(phandle, "ephy"); 1287 1288 /* Regulator is optional */ 1289 sc->reg_phy = fdtbus_regulator_acquire(phandle, "phy-supply"); 1290 1291 /* Reset GPIO is optional */ 1292 sc->pin_reset = fdtbus_gpio_acquire(sc->phandle, 1293 "allwinner,reset-gpio", GPIO_PIN_OUTPUT); 1294 1295 return 0; 1296 } 1297 1298 static int 1299 sunxi_emac_match(device_t parent, cfdata_t cf, void *aux) 1300 { 1301 struct fdt_attach_args * const faa = aux; 1302 1303 return of_match_compat_data(faa->faa_phandle, compat_data); 1304 } 1305 1306 static void 1307 sunxi_emac_attach(device_t parent, device_t self, void *aux) 1308 { 1309 struct fdt_attach_args * const faa = aux; 1310 struct sunxi_emac_softc * const sc = device_private(self); 1311 const int phandle = faa->faa_phandle; 1312 struct mii_data *mii = &sc->mii; 1313 struct ifnet *ifp = &sc->ec.ec_if; 1314 uint8_t eaddr[ETHER_ADDR_LEN]; 1315 char intrstr[128]; 1316 1317 sc->dev = self; 1318 sc->phandle = phandle; 1319 sc->bst = faa->faa_bst; 1320 sc->dmat = faa->faa_dmat; 1321 sc->type = of_search_compatible(phandle, compat_data)->data; 1322 1323 if (sunxi_emac_get_resources(sc) != 0) { 1324 aprint_error(": cannot allocate resources for device\n"); 1325 return; 1326 } 1327 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 1328 aprint_error(": cannot decode interrupt\n"); 1329 return; 1330 } 1331 1332 mutex_init(&sc->mtx, MUTEX_DEFAULT, IPL_NET); 1333 callout_init(&sc->stat_ch, CALLOUT_FLAGS); 1334 callout_setfunc(&sc->stat_ch, sunxi_emac_tick, sc); 1335 1336 aprint_naive("\n"); 1337 aprint_normal(": EMAC\n"); 1338 1339 /* Setup clocks and regulators */ 1340 if (sunxi_emac_setup_resources(sc) != 0) 1341 return; 1342 1343 /* Read MAC address before resetting the chip */ 1344 sunxi_emac_get_eaddr(sc, eaddr); 1345 1346 /* Soft reset EMAC core */ 1347 if (sunxi_emac_reset(sc) != 0) 1348 return; 1349 1350 /* Setup DMA descriptors */ 1351 if (sunxi_emac_setup_dma(sc) != 0) { 1352 aprint_error_dev(self, "failed to setup DMA descriptors\n"); 1353 return; 1354 } 1355 1356 /* Install interrupt handler */ 1357 sc->ih = fdtbus_intr_establish(phandle, 0, IPL_NET, 1358 FDT_INTR_FLAGS, sunxi_emac_intr, sc); 1359 if (sc->ih == NULL) { 1360 aprint_error_dev(self, "failed to establish interrupt on %s\n", 1361 intrstr); 1362 return; 1363 } 1364 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 1365 1366 /* Setup ethernet interface */ 1367 ifp->if_softc = sc; 1368 snprintf(ifp->if_xname, IFNAMSIZ, EMAC_IFNAME, device_unit(self)); 1369 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1370 #ifdef EMAC_MPSAFE 1371 ifp->if_extflags = IFEF_START_MPSAFE; 1372 #endif 1373 ifp->if_start = sunxi_emac_start; 1374 ifp->if_ioctl = sunxi_emac_ioctl; 1375 ifp->if_init = sunxi_emac_init; 1376 ifp->if_stop = sunxi_emac_stop; 1377 ifp->if_capabilities = IFCAP_CSUM_IPv4_Rx | 1378 IFCAP_CSUM_IPv4_Tx | 1379 IFCAP_CSUM_TCPv4_Rx | 1380 IFCAP_CSUM_TCPv4_Tx | 1381 IFCAP_CSUM_UDPv4_Rx | 1382 IFCAP_CSUM_UDPv4_Tx; 1383 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 1384 IFQ_SET_READY(&ifp->if_snd); 1385 1386 /* 802.1Q VLAN-sized frames are supported */ 1387 sc->ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 1388 1389 /* Attach MII driver */ 1390 sc->ec.ec_mii = mii; 1391 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 1392 mii->mii_ifp = ifp; 1393 mii->mii_readreg = sunxi_emac_mii_readreg; 1394 mii->mii_writereg = sunxi_emac_mii_writereg; 1395 mii->mii_statchg = sunxi_emac_mii_statchg; 1396 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 1397 MIIF_DOPAUSE); 1398 1399 if (LIST_EMPTY(&mii->mii_phys)) { 1400 aprint_error_dev(self, "no PHY found!\n"); 1401 return; 1402 } 1403 ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_AUTO); 1404 1405 /* Attach interface */ 1406 if_attach(ifp); 1407 if_deferred_start_init(ifp, NULL); 1408 1409 /* Attach ethernet interface */ 1410 ether_ifattach(ifp, eaddr); 1411 } 1412 1413 CFATTACH_DECL_NEW(sunxi_emac, sizeof(struct sunxi_emac_softc), 1414 sunxi_emac_match, sunxi_emac_attach, NULL, NULL); 1415
Indexes created Mon Oct 20 20:10:13 GMT 2025