sunxi_gates.c revision 1.1.10.1
1 /* $NetBSD: sunxi_gates.c,v 1.1.10.1 2018/09/30 01:45:39 pgoyette Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: sunxi_gates.c,v 1.1.10.1 2018/09/30 01:45:39 pgoyette Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/cpu.h> 35 #include <sys/device.h> 36 #include <sys/kmem.h> 37 38 #include <dev/fdt/fdtvar.h> 39 40 #include <dev/clk/clk_backend.h> 41 42 #define GATE_REG(index) (((index) / 32) * 4) 43 #define GATE_MASK(index) __BIT((index) % 32) 44 45 static const char * compatible[] = { 46 "allwinner,sun4i-a10-gates-clk", 47 NULL 48 }; 49 50 struct sunxi_gate { 51 struct clk base; 52 u_int index; 53 54 TAILQ_ENTRY(sunxi_gate) gates; 55 }; 56 57 struct sunxi_gates_softc { 58 device_t sc_dev; 59 bus_space_tag_t sc_bst; 60 bus_space_handle_t sc_bsh; 61 int sc_phandle; 62 63 struct clk_domain sc_clkdom; 64 TAILQ_HEAD(, sunxi_gate) sc_gates; 65 }; 66 67 #define GATE_READ(sc, reg) \ 68 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 69 #define GATE_WRITE(sc, reg, val) \ 70 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 71 72 static struct clk * 73 sunxi_gates_clock_decode(device_t dev, int cc_phandle, const void *data, 74 size_t len) 75 { 76 struct sunxi_gates_softc * const sc = device_private(dev); 77 struct sunxi_gate *gate; 78 79 if (len != 4) 80 return NULL; 81 82 const u_int index = be32dec(data); 83 84 TAILQ_FOREACH(gate, &sc->sc_gates, gates) 85 if (gate->index == index) 86 return &gate->base; 87 88 return NULL; 89 } 90 91 static const struct fdtbus_clock_controller_func sunxi_gates_fdtclock_funcs = { 92 .decode = sunxi_gates_clock_decode, 93 }; 94 95 static struct clk * 96 sunxi_gates_clock_get(void *priv, const char *name) 97 { 98 struct sunxi_gates_softc * const sc = priv; 99 struct sunxi_gate *gate; 100 101 TAILQ_FOREACH(gate, &sc->sc_gates, gates) 102 if (strcmp(gate->base.name, name) == 0) 103 return &gate->base; 104 105 return NULL; 106 } 107 108 static void 109 sunxi_gates_clock_put(void *priv, struct clk *clk) 110 { 111 } 112 113 static u_int 114 sunxi_gates_clock_get_rate(void *priv, struct clk *clkp) 115 { 116 struct sunxi_gates_softc * const sc = priv; 117 struct sunxi_gate *gate = (struct sunxi_gate *)clkp; 118 struct clk *clkp_parent; 119 120 clkp_parent = clk_get_parent(clkp); 121 if (clkp_parent == NULL) 122 return 0; 123 124 const bus_size_t gate_reg = GATE_REG(gate->index); 125 const uint32_t gate_mask = GATE_MASK(gate->index); 126 127 if ((GATE_READ(sc, gate_reg) & gate_mask) == 0) 128 return 0; 129 130 return clk_get_rate(clkp_parent); 131 } 132 133 static int 134 sunxi_gates_clock_enable(void *priv, struct clk *clkp) 135 { 136 struct sunxi_gates_softc * const sc = priv; 137 struct sunxi_gate *gate = (struct sunxi_gate *)clkp; 138 uint32_t val; 139 140 const bus_size_t gate_reg = GATE_REG(gate->index); 141 const uint32_t gate_mask = GATE_MASK(gate->index); 142 143 val = GATE_READ(sc, gate_reg); 144 val |= gate_mask; 145 GATE_WRITE(sc, gate_reg, val); 146 147 return 0; 148 } 149 150 static int 151 sunxi_gates_clock_disable(void *priv, struct clk *clkp) 152 { 153 struct sunxi_gates_softc * const sc = priv; 154 struct sunxi_gate *gate = (struct sunxi_gate *)clkp; 155 uint32_t val; 156 157 const bus_size_t gate_reg = GATE_REG(gate->index); 158 const uint32_t gate_mask = GATE_MASK(gate->index); 159 160 val = GATE_READ(sc, gate_reg); 161 val &= ~gate_mask; 162 GATE_WRITE(sc, gate_reg, val); 163 164 return 0; 165 } 166 167 static struct clk * 168 sunxi_gates_clock_get_parent(void *priv, struct clk *clkp) 169 { 170 struct sunxi_gates_softc * const sc = priv; 171 172 return fdtbus_clock_get_index(sc->sc_phandle, 0); 173 } 174 175 static const struct clk_funcs sunxi_gates_clock_funcs = { 176 .get = sunxi_gates_clock_get, 177 .put = sunxi_gates_clock_put, 178 .get_rate = sunxi_gates_clock_get_rate, 179 .enable = sunxi_gates_clock_enable, 180 .disable = sunxi_gates_clock_disable, 181 .get_parent = sunxi_gates_clock_get_parent, 182 }; 183 184 static void 185 sunxi_gates_print(struct sunxi_gates_softc *sc) 186 { 187 struct sunxi_gate *gate; 188 struct clk *clkp_parent; 189 190 TAILQ_FOREACH(gate, &sc->sc_gates, gates) { 191 clkp_parent = clk_get_parent(&gate->base); 192 193 aprint_debug_dev(sc->sc_dev, 194 "%3d %-12s %2s %-12s %-7s ", 195 gate->index, 196 gate->base.name, 197 clkp_parent ? "<-" : "", 198 clkp_parent ? clkp_parent->name : "", 199 "gate"); 200 aprint_debug("%10d Hz\n", clk_get_rate(&gate->base)); 201 } 202 } 203 204 static int 205 sunxi_gates_match(device_t parent, cfdata_t cf, void *aux) 206 { 207 struct fdt_attach_args * const faa = aux; 208 209 return of_match_compatible(faa->faa_phandle, compatible); 210 } 211 212 static void 213 sunxi_gates_attach(device_t parent, device_t self, void *aux) 214 { 215 struct sunxi_gates_softc * const sc = device_private(self); 216 struct fdt_attach_args * const faa = aux; 217 const int phandle = faa->faa_phandle; 218 struct sunxi_gate *gate; 219 const u_int *indices; 220 bus_addr_t addr; 221 bus_size_t size; 222 int len, i; 223 224 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 225 aprint_error(": couldn't get registers\n"); 226 return; 227 } 228 229 sc->sc_dev = self; 230 sc->sc_phandle = phandle; 231 sc->sc_bst = faa->faa_bst; 232 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 233 aprint_error(": couldn't map registers\n"); 234 return; 235 } 236 TAILQ_INIT(&sc->sc_gates); 237 238 aprint_naive("\n"); 239 aprint_normal("\n"); 240 241 sc->sc_clkdom.funcs = &sunxi_gates_clock_funcs; 242 sc->sc_clkdom.priv = sc; 243 244 indices = fdtbus_get_prop(phandle, "clock-indices", &len); 245 if (indices == NULL) { 246 aprint_error_dev(self, "no clock-indices property\n"); 247 return; 248 } 249 250 for (i = 0; 251 len >= sizeof(u_int); 252 len -= sizeof(u_int), i++, indices++) { 253 const u_int index = be32dec(indices); 254 const char *name = fdtbus_get_string_index(phandle, 255 "clock-output-names", i); 256 257 if (name == NULL) { 258 aprint_error_dev(self, "no name for clk index %d\n", 259 index); 260 continue; 261 } 262 263 gate = kmem_zalloc(sizeof(*gate), KM_SLEEP); 264 gate->base.domain = &sc->sc_clkdom; 265 gate->base.name = name; 266 gate->index = index; 267 268 TAILQ_INSERT_TAIL(&sc->sc_gates, gate, gates); 269 } 270 271 fdtbus_register_clock_controller(sc->sc_dev, phandle, 272 &sunxi_gates_fdtclock_funcs); 273 274 sunxi_gates_print(sc); 275 } 276 277 CFATTACH_DECL_NEW(sunxi_gates, sizeof(struct sunxi_gates_softc), 278 sunxi_gates_match, sunxi_gates_attach, NULL, NULL); 279
Indexes created Mon Oct 20 11:09:49 GMT 2025