sunxi_gates.c revision 1.1.6.2
1 /* $NetBSD: sunxi_gates.c,v 1.1.6.2 2017/08/28 17:51:32 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: sunxi_gates.c,v 1.1.6.2 2017/08/28 17:51:32 skrll Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/cpu.h> 35 #include <sys/device.h> 36 #include <sys/kmem.h> 37 38 #include <dev/fdt/fdtvar.h> 39 40 #include <dev/clk/clk_backend.h> 41 42 #define GATE_REG(index) (((index) / 32) * 4) 43 #define GATE_MASK(index) __BIT((index) % 32) 44 45 static const char * compatible[] = { 46 "allwinner,sun4i-a10-gates-clk", 47 NULL 48 }; 49 50 struct sunxi_gate { 51 struct clk base; 52 u_int index; 53 54 TAILQ_ENTRY(sunxi_gate) gates; 55 }; 56 57 struct sunxi_gates_softc { 58 device_t sc_dev; 59 bus_space_tag_t sc_bst; 60 bus_space_handle_t sc_bsh; 61 int sc_phandle; 62 63 struct clk_domain sc_clkdom; 64 TAILQ_HEAD(, sunxi_gate) sc_gates; 65 }; 66 67 #define GATE_READ(sc, reg) \ 68 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 69 #define GATE_WRITE(sc, reg, val) \ 70 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 71 72 static struct clk * 73 sunxi_gates_clock_decode(device_t dev, const void *data, size_t len) 74 { 75 struct sunxi_gates_softc * const sc = device_private(dev); 76 struct sunxi_gate *gate; 77 78 if (len != 4) 79 return NULL; 80 81 const u_int index = be32dec(data); 82 83 TAILQ_FOREACH(gate, &sc->sc_gates, gates) 84 if (gate->index == index) 85 return &gate->base; 86 87 return NULL; 88 } 89 90 static const struct fdtbus_clock_controller_func sunxi_gates_fdtclock_funcs = { 91 .decode = sunxi_gates_clock_decode, 92 }; 93 94 static struct clk * 95 sunxi_gates_clock_get(void *priv, const char *name) 96 { 97 struct sunxi_gates_softc * const sc = priv; 98 struct sunxi_gate *gate; 99 100 TAILQ_FOREACH(gate, &sc->sc_gates, gates) 101 if (strcmp(gate->base.name, name) == 0) 102 return &gate->base; 103 104 return NULL; 105 } 106 107 static void 108 sunxi_gates_clock_put(void *priv, struct clk *clk) 109 { 110 } 111 112 static u_int 113 sunxi_gates_clock_get_rate(void *priv, struct clk *clkp) 114 { 115 struct sunxi_gates_softc * const sc = priv; 116 struct sunxi_gate *gate = (struct sunxi_gate *)clkp; 117 struct clk *clkp_parent; 118 119 clkp_parent = clk_get_parent(clkp); 120 if (clkp_parent == NULL) 121 return 0; 122 123 const bus_size_t gate_reg = GATE_REG(gate->index); 124 const uint32_t gate_mask = GATE_MASK(gate->index); 125 126 if ((GATE_READ(sc, gate_reg) & gate_mask) == 0) 127 return 0; 128 129 return clk_get_rate(clkp_parent); 130 } 131 132 static int 133 sunxi_gates_clock_enable(void *priv, struct clk *clkp) 134 { 135 struct sunxi_gates_softc * const sc = priv; 136 struct sunxi_gate *gate = (struct sunxi_gate *)clkp; 137 uint32_t val; 138 139 const bus_size_t gate_reg = GATE_REG(gate->index); 140 const uint32_t gate_mask = GATE_MASK(gate->index); 141 142 val = GATE_READ(sc, gate_reg); 143 val |= gate_mask; 144 GATE_WRITE(sc, gate_reg, val); 145 146 return 0; 147 } 148 149 static int 150 sunxi_gates_clock_disable(void *priv, struct clk *clkp) 151 { 152 struct sunxi_gates_softc * const sc = priv; 153 struct sunxi_gate *gate = (struct sunxi_gate *)clkp; 154 uint32_t val; 155 156 const bus_size_t gate_reg = GATE_REG(gate->index); 157 const uint32_t gate_mask = GATE_MASK(gate->index); 158 159 val = GATE_READ(sc, gate_reg); 160 val &= ~gate_mask; 161 GATE_WRITE(sc, gate_reg, val); 162 163 return 0; 164 } 165 166 static struct clk * 167 sunxi_gates_clock_get_parent(void *priv, struct clk *clkp) 168 { 169 struct sunxi_gates_softc * const sc = priv; 170 171 return fdtbus_clock_get_index(sc->sc_phandle, 0); 172 } 173 174 static const struct clk_funcs sunxi_gates_clock_funcs = { 175 .get = sunxi_gates_clock_get, 176 .put = sunxi_gates_clock_put, 177 .get_rate = sunxi_gates_clock_get_rate, 178 .enable = sunxi_gates_clock_enable, 179 .disable = sunxi_gates_clock_disable, 180 .get_parent = sunxi_gates_clock_get_parent, 181 }; 182 183 static void 184 sunxi_gates_print(struct sunxi_gates_softc *sc) 185 { 186 struct sunxi_gate *gate; 187 struct clk *clkp_parent; 188 189 TAILQ_FOREACH(gate, &sc->sc_gates, gates) { 190 clkp_parent = clk_get_parent(&gate->base); 191 192 aprint_debug_dev(sc->sc_dev, 193 "%3d %-12s %2s %-12s %-7s ", 194 gate->index, 195 gate->base.name, 196 clkp_parent ? "<-" : "", 197 clkp_parent ? clkp_parent->name : "", 198 "gate"); 199 aprint_debug("%10d Hz\n", clk_get_rate(&gate->base)); 200 } 201 } 202 203 static int 204 sunxi_gates_match(device_t parent, cfdata_t cf, void *aux) 205 { 206 struct fdt_attach_args * const faa = aux; 207 208 return of_match_compatible(faa->faa_phandle, compatible); 209 } 210 211 static void 212 sunxi_gates_attach(device_t parent, device_t self, void *aux) 213 { 214 struct sunxi_gates_softc * const sc = device_private(self); 215 struct fdt_attach_args * const faa = aux; 216 const int phandle = faa->faa_phandle; 217 struct sunxi_gate *gate; 218 const u_int *indices; 219 bus_addr_t addr; 220 bus_size_t size; 221 int len, i; 222 223 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 224 aprint_error(": couldn't get registers\n"); 225 return; 226 } 227 228 sc->sc_dev = self; 229 sc->sc_phandle = phandle; 230 sc->sc_bst = faa->faa_bst; 231 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 232 aprint_error(": couldn't map registers\n"); 233 return; 234 } 235 TAILQ_INIT(&sc->sc_gates); 236 237 aprint_naive("\n"); 238 aprint_normal("\n"); 239 240 sc->sc_clkdom.funcs = &sunxi_gates_clock_funcs; 241 sc->sc_clkdom.priv = sc; 242 243 indices = fdtbus_get_prop(phandle, "clock-indices", &len); 244 if (indices == NULL) { 245 aprint_error_dev(self, "no clock-indices property\n"); 246 return; 247 } 248 249 for (i = 0; 250 len >= sizeof(u_int); 251 len -= sizeof(u_int), i++, indices++) { 252 const u_int index = be32dec(indices); 253 const char *name = fdtbus_get_string_index(phandle, 254 "clock-output-names", i); 255 256 if (name == NULL) { 257 aprint_error_dev(self, "no name for clk index %d\n", 258 index); 259 continue; 260 } 261 262 gate = kmem_zalloc(sizeof(*gate), KM_SLEEP); 263 gate->base.domain = &sc->sc_clkdom; 264 gate->base.name = name; 265 gate->index = index; 266 267 TAILQ_INSERT_TAIL(&sc->sc_gates, gate, gates); 268 } 269 270 fdtbus_register_clock_controller(sc->sc_dev, phandle, 271 &sunxi_gates_fdtclock_funcs); 272 273 sunxi_gates_print(sc); 274 } 275 276 CFATTACH_DECL_NEW(sunxi_gates, sizeof(struct sunxi_gates_softc), 277 sunxi_gates_match, sunxi_gates_attach, NULL, NULL); 278
Indexes created Thu Oct 23 22:10:10 GMT 2025