sunxi_gpio.c revision 1.12
1 /* $NetBSD: sunxi_gpio.c,v 1.12 2017/08/26 17:59:24 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_soc.h" 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: sunxi_gpio.c,v 1.12 2017/08/26 17:59:24 jmcneill Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/intr.h> 38 #include <sys/systm.h> 39 #include <sys/mutex.h> 40 #include <sys/kmem.h> 41 #include <sys/gpio.h> 42 #include <sys/bitops.h> 43 44 #include <dev/fdt/fdtvar.h> 45 #include <dev/gpio/gpiovar.h> 46 47 #include <arm/sunxi/sunxi_gpio.h> 48 49 #define SUNXI_GPIO_MAX_EINT 32 50 51 #define SUNXI_GPIO_PORT(port) (0x24 * (port)) 52 #define SUNXI_GPIO_CFG(port, pin) (SUNXI_GPIO_PORT(port) + 0x00 + (0x4 * ((pin) / 8))) 53 #define SUNXI_GPIO_CFG_PINMASK(pin) (0x7 << (((pin) % 8) * 4)) 54 #define SUNXI_GPIO_DATA(port) (SUNXI_GPIO_PORT(port) + 0x10) 55 #define SUNXI_GPIO_DRV(port, pin) (SUNXI_GPIO_PORT(port) + 0x14 + (0x4 * ((pin) / 16))) 56 #define SUNXI_GPIO_DRV_PINMASK(pin) (0x3 << (((pin) % 16) * 2)) 57 #define SUNXI_GPIO_PULL(port, pin) (SUNXI_GPIO_PORT(port) + 0x1c + (0x4 * ((pin) / 16))) 58 #define SUNXI_GPIO_PULL_DISABLE 0 59 #define SUNXI_GPIO_PULL_UP 1 60 #define SUNXI_GPIO_PULL_DOWN 2 61 #define SUNXI_GPIO_PULL_PINMASK(pin) (0x3 << (((pin) % 16) * 2)) 62 #define SUNXI_GPIO_INT_CFG(eint) (0x200 + (0x4 * ((eint) / 8))) 63 #define SUNXI_GPIO_INT_MODEMASK(eint) (0xf << (((eint) % 8) * 4)) 64 #define SUNXI_GPIO_INT_MODE_POS_EDGE 0x0 65 #define SUNXI_GPIO_INT_MODE_NEG_EDGE 0x1 66 #define SUNXI_GPIO_INT_MODE_HIGH_LEVEL 0x2 67 #define SUNXI_GPIO_INT_MODE_LOW_LEVEL 0x3 68 #define SUNXI_GPIO_INT_MODE_DOUBLE_EDGE 0x4 69 #define SUNXI_GPIO_INT_CTL 0x210 70 #define SUNXI_GPIO_INT_STATUS 0x214 71 72 static const struct of_compat_data compat_data[] = { 73 #ifdef SOC_SUN5I_A13 74 { "allwinner,sun5i-a13-pinctrl", (uintptr_t)&sun5i_a13_padconf }, 75 #endif 76 #ifdef SOC_SUN6I_A31 77 { "allwinner,sun6i-a31-pinctrl", (uintptr_t)&sun6i_a31_padconf }, 78 { "allwinner,sun6i-a31-r-pinctrl", (uintptr_t)&sun6i_a31_r_padconf }, 79 #endif 80 #ifdef SOC_SUN8I_A83T 81 { "allwinner,sun8i-a83t-pinctrl", (uintptr_t)&sun8i_a83t_padconf }, 82 { "allwinner,sun8i-a83t-r-pinctrl", (uintptr_t)&sun8i_a83t_r_padconf }, 83 #endif 84 #ifdef SOC_SUN8I_H3 85 { "allwinner,sun8i-h3-pinctrl", (uintptr_t)&sun8i_h3_padconf }, 86 { "allwinner,sun8i-h3-r-pinctrl", (uintptr_t)&sun8i_h3_r_padconf }, 87 #endif 88 #ifdef SOC_SUN50I_A64 89 { "allwinner,sun50i-a64-pinctrl", (uintptr_t)&sun50i_a64_padconf }, 90 { "allwinner,sun50i-a64-r-pinctrl", (uintptr_t)&sun50i_a64_r_padconf }, 91 #endif 92 { NULL } 93 }; 94 95 struct sunxi_gpio_eint { 96 int (*eint_func)(void *); 97 void *eint_arg; 98 int eint_flags; 99 int eint_num; 100 }; 101 102 struct sunxi_gpio_softc { 103 device_t sc_dev; 104 bus_space_tag_t sc_bst; 105 bus_space_handle_t sc_bsh; 106 const struct sunxi_gpio_padconf *sc_padconf; 107 kmutex_t sc_lock; 108 109 struct gpio_chipset_tag sc_gp; 110 gpio_pin_t *sc_pins; 111 device_t sc_gpiodev; 112 113 void *sc_ih; 114 struct sunxi_gpio_eint sc_eint[SUNXI_GPIO_MAX_EINT]; 115 }; 116 117 struct sunxi_gpio_pin { 118 struct sunxi_gpio_softc *pin_sc; 119 const struct sunxi_gpio_pins *pin_def; 120 int pin_flags; 121 bool pin_actlo; 122 }; 123 124 #define GPIO_READ(sc, reg) \ 125 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 126 #define GPIO_WRITE(sc, reg, val) \ 127 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 128 129 static int sunxi_gpio_match(device_t, cfdata_t, void *); 130 static void sunxi_gpio_attach(device_t, device_t, void *); 131 132 CFATTACH_DECL_NEW(sunxi_gpio, sizeof(struct sunxi_gpio_softc), 133 sunxi_gpio_match, sunxi_gpio_attach, NULL, NULL); 134 135 static const struct sunxi_gpio_pins * 136 sunxi_gpio_lookup(struct sunxi_gpio_softc *sc, uint8_t port, uint8_t pin) 137 { 138 const struct sunxi_gpio_pins *pin_def; 139 u_int n; 140 141 for (n = 0; n < sc->sc_padconf->npins; n++) { 142 pin_def = &sc->sc_padconf->pins[n]; 143 if (pin_def->port == port && pin_def->pin == pin) 144 return pin_def; 145 } 146 147 return NULL; 148 } 149 150 static const struct sunxi_gpio_pins * 151 sunxi_gpio_lookup_byname(struct sunxi_gpio_softc *sc, const char *name) 152 { 153 const struct sunxi_gpio_pins *pin_def; 154 u_int n; 155 156 for (n = 0; n < sc->sc_padconf->npins; n++) { 157 pin_def = &sc->sc_padconf->pins[n]; 158 if (strcmp(pin_def->name, name) == 0) 159 return pin_def; 160 } 161 162 return NULL; 163 } 164 165 static int 166 sunxi_gpio_setfunc(struct sunxi_gpio_softc *sc, 167 const struct sunxi_gpio_pins *pin_def, const char *func) 168 { 169 uint32_t cfg; 170 u_int n; 171 172 KASSERT(mutex_owned(&sc->sc_lock)); 173 174 const bus_size_t cfg_reg = SUNXI_GPIO_CFG(pin_def->port, pin_def->pin); 175 const uint32_t cfg_mask = SUNXI_GPIO_CFG_PINMASK(pin_def->pin); 176 177 for (n = 0; n < SUNXI_GPIO_MAXFUNC; n++) { 178 if (pin_def->functions[n] == NULL) 179 continue; 180 if (strcmp(pin_def->functions[n], func) == 0) { 181 cfg = GPIO_READ(sc, cfg_reg); 182 cfg &= ~cfg_mask; 183 cfg |= __SHIFTIN(n, cfg_mask); 184 #ifdef SUNXI_GPIO_DEBUG 185 device_printf(sc->sc_dev, "P%c%02d cfg %08x -> %08x\n", 186 pin_def->port + 'A', pin_def->pin, GPIO_READ(sc, cfg_reg), cfg); 187 #endif 188 GPIO_WRITE(sc, cfg_reg, cfg); 189 return 0; 190 } 191 } 192 193 /* Function not found */ 194 device_printf(sc->sc_dev, "function '%s' not supported on P%c%02d\n", 195 func, pin_def->port + 'A', pin_def->pin); 196 197 return ENXIO; 198 } 199 200 static int 201 sunxi_gpio_setpull(struct sunxi_gpio_softc *sc, 202 const struct sunxi_gpio_pins *pin_def, int flags) 203 { 204 uint32_t pull; 205 206 KASSERT(mutex_owned(&sc->sc_lock)); 207 208 const bus_size_t pull_reg = SUNXI_GPIO_PULL(pin_def->port, pin_def->pin); 209 const uint32_t pull_mask = SUNXI_GPIO_PULL_PINMASK(pin_def->pin); 210 211 pull = GPIO_READ(sc, pull_reg); 212 pull &= ~pull_mask; 213 if (flags & GPIO_PIN_PULLUP) 214 pull |= __SHIFTIN(SUNXI_GPIO_PULL_UP, pull_mask); 215 else if (flags & GPIO_PIN_PULLDOWN) 216 pull |= __SHIFTIN(SUNXI_GPIO_PULL_DOWN, pull_mask); 217 else 218 pull |= __SHIFTIN(SUNXI_GPIO_PULL_DISABLE, pull_mask); 219 #ifdef SUNXI_GPIO_DEBUG 220 device_printf(sc->sc_dev, "P%c%02d pull %08x -> %08x\n", 221 pin_def->port + 'A', pin_def->pin, GPIO_READ(sc, pull_reg), pull); 222 #endif 223 GPIO_WRITE(sc, pull_reg, pull); 224 225 return 0; 226 } 227 228 static int 229 sunxi_gpio_setdrv(struct sunxi_gpio_softc *sc, 230 const struct sunxi_gpio_pins *pin_def, int drive_strength) 231 { 232 uint32_t drv; 233 234 KASSERT(mutex_owned(&sc->sc_lock)); 235 236 if (drive_strength < 10 || drive_strength > 40) 237 return EINVAL; 238 239 const bus_size_t drv_reg = SUNXI_GPIO_DRV(pin_def->port, pin_def->pin); 240 const uint32_t drv_mask = SUNXI_GPIO_DRV_PINMASK(pin_def->pin); 241 242 drv = GPIO_READ(sc, drv_reg); 243 drv &= ~drv_mask; 244 drv |= __SHIFTIN((drive_strength / 10) - 1, drv_mask); 245 #ifdef SUNXI_GPIO_DEBUG 246 device_printf(sc->sc_dev, "P%c%02d drv %08x -> %08x\n", 247 pin_def->port + 'A', pin_def->pin, GPIO_READ(sc, drv_reg), drv); 248 #endif 249 GPIO_WRITE(sc, drv_reg, drv); 250 251 return 0; 252 } 253 254 static int 255 sunxi_gpio_ctl(struct sunxi_gpio_softc *sc, const struct sunxi_gpio_pins *pin_def, 256 int flags) 257 { 258 KASSERT(mutex_owned(&sc->sc_lock)); 259 260 if (flags & GPIO_PIN_INPUT) 261 return sunxi_gpio_setfunc(sc, pin_def, "gpio_in"); 262 if (flags & GPIO_PIN_OUTPUT) 263 return sunxi_gpio_setfunc(sc, pin_def, "gpio_out"); 264 265 return EINVAL; 266 } 267 268 static void * 269 sunxi_gpio_acquire(device_t dev, const void *data, size_t len, int flags) 270 { 271 struct sunxi_gpio_softc * const sc = device_private(dev); 272 const struct sunxi_gpio_pins *pin_def; 273 struct sunxi_gpio_pin *gpin; 274 const u_int *gpio = data; 275 int error; 276 277 if (len != 16) 278 return NULL; 279 280 const uint8_t port = be32toh(gpio[1]) & 0xff; 281 const uint8_t pin = be32toh(gpio[2]) & 0xff; 282 const bool actlo = be32toh(gpio[3]) & 1; 283 284 pin_def = sunxi_gpio_lookup(sc, port, pin); 285 if (pin_def == NULL) 286 return NULL; 287 288 mutex_enter(&sc->sc_lock); 289 error = sunxi_gpio_ctl(sc, pin_def, flags); 290 mutex_exit(&sc->sc_lock); 291 292 if (error != 0) 293 return NULL; 294 295 gpin = kmem_zalloc(sizeof(*gpin), KM_SLEEP); 296 gpin->pin_sc = sc; 297 gpin->pin_def = pin_def; 298 gpin->pin_flags = flags; 299 gpin->pin_actlo = actlo; 300 301 return gpin; 302 } 303 304 static void 305 sunxi_gpio_release(device_t dev, void *priv) 306 { 307 struct sunxi_gpio_pin *pin = priv; 308 309 sunxi_gpio_ctl(pin->pin_sc, pin->pin_def, GPIO_PIN_INPUT); 310 311 kmem_free(pin, sizeof(*pin)); 312 } 313 314 static int 315 sunxi_gpio_read(device_t dev, void *priv, bool raw) 316 { 317 struct sunxi_gpio_softc * const sc = device_private(dev); 318 struct sunxi_gpio_pin *pin = priv; 319 const struct sunxi_gpio_pins *pin_def = pin->pin_def; 320 uint32_t data; 321 int val; 322 323 KASSERT(sc == pin->pin_sc); 324 325 const bus_size_t data_reg = SUNXI_GPIO_DATA(pin_def->port); 326 const uint32_t data_mask = __BIT(pin_def->pin); 327 328 /* No lock required for reads */ 329 data = GPIO_READ(sc, data_reg); 330 val = __SHIFTOUT(data, data_mask); 331 if (!raw && pin->pin_actlo) 332 val = !val; 333 334 #ifdef SUNXI_GPIO_DEBUG 335 device_printf(dev, "P%c%02d rd %08x (%d %d)\n", 336 pin_def->port + 'A', pin_def->pin, data, 337 __SHIFTOUT(val, data_mask), val); 338 #endif 339 340 return val; 341 } 342 343 static void 344 sunxi_gpio_write(device_t dev, void *priv, int val, bool raw) 345 { 346 struct sunxi_gpio_softc * const sc = device_private(dev); 347 struct sunxi_gpio_pin *pin = priv; 348 const struct sunxi_gpio_pins *pin_def = pin->pin_def; 349 uint32_t data; 350 351 KASSERT(sc == pin->pin_sc); 352 353 const bus_size_t data_reg = SUNXI_GPIO_DATA(pin_def->port); 354 const uint32_t data_mask = __BIT(pin_def->pin); 355 356 if (!raw && pin->pin_actlo) 357 val = !val; 358 359 mutex_enter(&sc->sc_lock); 360 data = GPIO_READ(sc, data_reg); 361 data &= ~data_mask; 362 data |= __SHIFTIN(val, data_mask); 363 #ifdef SUNXI_GPIO_DEBUG 364 device_printf(dev, "P%c%02d wr %08x -> %08x\n", 365 pin_def->port + 'A', pin_def->pin, GPIO_READ(sc, data_reg), data); 366 #endif 367 GPIO_WRITE(sc, data_reg, data); 368 mutex_exit(&sc->sc_lock); 369 } 370 371 static struct fdtbus_gpio_controller_func sunxi_gpio_funcs = { 372 .acquire = sunxi_gpio_acquire, 373 .release = sunxi_gpio_release, 374 .read = sunxi_gpio_read, 375 .write = sunxi_gpio_write, 376 }; 377 378 static int 379 sunxi_gpio_intr(void *priv) 380 { 381 struct sunxi_gpio_softc * const sc = priv; 382 struct sunxi_gpio_eint *eint; 383 uint32_t status, bit; 384 int ret = 0; 385 386 status = GPIO_READ(sc, SUNXI_GPIO_INT_STATUS); 387 GPIO_WRITE(sc, SUNXI_GPIO_INT_STATUS, status); 388 389 while ((bit = ffs32(status)) != 0) { 390 status &= ~__BIT(bit - 1); 391 eint = &sc->sc_eint[bit - 1]; 392 if (eint->eint_func == NULL) 393 continue; 394 const bool mpsafe = (eint->eint_flags & FDT_INTR_MPSAFE) != 0; 395 if (!mpsafe) 396 KERNEL_LOCK(1, curlwp); 397 ret |= eint->eint_func(eint->eint_arg); 398 if (!mpsafe) 399 KERNEL_UNLOCK_ONE(curlwp); 400 } 401 402 return ret; 403 } 404 405 static void * 406 sunxi_gpio_establish(device_t dev, u_int *specifier, int ipl, int flags, 407 int (*func)(void *), void *arg) 408 { 409 struct sunxi_gpio_softc * const sc = device_private(dev); 410 const struct sunxi_gpio_pins *pin_def; 411 struct sunxi_gpio_eint *eint; 412 uint32_t val; 413 u_int mode; 414 415 if (ipl != IPL_VM) { 416 aprint_error_dev(dev, "%s: wrong IPL %d (expected %d)\n", 417 __func__, ipl, IPL_VM); 418 return NULL; 419 } 420 421 /* 1st cell is the bank */ 422 /* 2nd cell is the pin */ 423 /* 3rd cell is flags */ 424 const u_int port = be32toh(specifier[0]); 425 const u_int pin = be32toh(specifier[1]); 426 const u_int type = be32toh(specifier[2]) & 0xf; 427 428 switch (type) { 429 case 0x1: 430 mode = SUNXI_GPIO_INT_MODE_POS_EDGE; 431 break; 432 case 0x2: 433 mode = SUNXI_GPIO_INT_MODE_NEG_EDGE; 434 break; 435 case 0x3: 436 mode = SUNXI_GPIO_INT_MODE_DOUBLE_EDGE; 437 break; 438 case 0x4: 439 mode = SUNXI_GPIO_INT_MODE_HIGH_LEVEL; 440 break; 441 case 0x8: 442 mode = SUNXI_GPIO_INT_MODE_LOW_LEVEL; 443 break; 444 default: 445 aprint_error_dev(dev, "%s: unsupported irq type 0x%x\n", 446 __func__, type); 447 return NULL; 448 } 449 450 pin_def = sunxi_gpio_lookup(sc, port, pin); 451 if (pin_def == NULL) 452 return NULL; 453 if (pin_def->functions[pin_def->eint_func] == NULL || 454 strcmp(pin_def->functions[pin_def->eint_func], "eint") != 0) 455 return NULL; 456 457 KASSERT(pin_def->eint_num < SUNXI_GPIO_MAX_EINT); 458 459 mutex_enter(&sc->sc_lock); 460 461 eint = &sc->sc_eint[pin_def->eint_num]; 462 if (eint->eint_func != NULL) { 463 mutex_exit(&sc->sc_lock); 464 return NULL; /* in use */ 465 } 466 467 /* Set function */ 468 if (sunxi_gpio_setfunc(sc, pin_def, "eint") != 0) { 469 mutex_exit(&sc->sc_lock); 470 return NULL; 471 } 472 473 eint->eint_func = func; 474 eint->eint_arg = arg; 475 eint->eint_flags = flags; 476 eint->eint_num = pin_def->eint_num; 477 478 /* Configure eint mode */ 479 val = GPIO_READ(sc, SUNXI_GPIO_INT_CFG(eint->eint_num)); 480 val &= ~SUNXI_GPIO_INT_MODEMASK(eint->eint_num); 481 val |= __SHIFTIN(mode, SUNXI_GPIO_INT_MODEMASK(eint->eint_num)); 482 GPIO_WRITE(sc, SUNXI_GPIO_INT_CFG(eint->eint_num), val); 483 484 /* Enable eint */ 485 val = GPIO_READ(sc, SUNXI_GPIO_INT_CTL); 486 val |= __BIT(eint->eint_num); 487 GPIO_WRITE(sc, SUNXI_GPIO_INT_CTL, val); 488 489 mutex_exit(&sc->sc_lock); 490 491 return eint; 492 } 493 494 static void 495 sunxi_gpio_disestablish(device_t dev, void *ih) 496 { 497 struct sunxi_gpio_softc * const sc = device_private(dev); 498 struct sunxi_gpio_eint * const eint = ih; 499 uint32_t val; 500 501 KASSERT(eint->eint_func != NULL); 502 503 mutex_enter(&sc->sc_lock); 504 505 /* Disable eint */ 506 val = GPIO_READ(sc, SUNXI_GPIO_INT_CTL); 507 val &= ~__BIT(eint->eint_num); 508 GPIO_WRITE(sc, SUNXI_GPIO_INT_CTL, val); 509 GPIO_WRITE(sc, SUNXI_GPIO_INT_STATUS, __BIT(eint->eint_num)); 510 511 eint->eint_func = NULL; 512 eint->eint_arg = NULL; 513 eint->eint_flags = 0; 514 515 mutex_exit(&sc->sc_lock); 516 } 517 518 static bool 519 sunxi_gpio_intrstr(device_t dev, u_int *specifier, char *buf, size_t buflen) 520 { 521 struct sunxi_gpio_softc * const sc = device_private(dev); 522 const struct sunxi_gpio_pins *pin_def; 523 524 /* 1st cell is the bank */ 525 /* 2nd cell is the pin */ 526 /* 3rd cell is flags */ 527 if (!specifier) 528 return false; 529 const u_int port = be32toh(specifier[0]); 530 const u_int pin = be32toh(specifier[1]); 531 532 pin_def = sunxi_gpio_lookup(sc, port, pin); 533 if (pin_def == NULL) 534 return false; 535 536 snprintf(buf, buflen, "GPIO %s", pin_def->name); 537 538 return true; 539 } 540 541 static struct fdtbus_interrupt_controller_func sunxi_gpio_intrfuncs = { 542 .establish = sunxi_gpio_establish, 543 .disestablish = sunxi_gpio_disestablish, 544 .intrstr = sunxi_gpio_intrstr, 545 }; 546 547 static const char * 548 sunxi_pinctrl_parse_function(int phandle) 549 { 550 const char *function; 551 552 function = fdtbus_get_string(phandle, "function"); 553 if (function != NULL) 554 return function; 555 556 return fdtbus_get_string(phandle, "allwinner,function"); 557 } 558 559 static const char * 560 sunxi_pinctrl_parse_pins(int phandle, int *pins_len) 561 { 562 int len; 563 564 len = OF_getproplen(phandle, "pins"); 565 if (len > 0) { 566 *pins_len = len; 567 return fdtbus_get_string(phandle, "pins"); 568 } 569 570 len = OF_getproplen(phandle, "allwinner,pins"); 571 if (len > 0) { 572 *pins_len = len; 573 return fdtbus_get_string(phandle, "allwinner,pins"); 574 } 575 576 return NULL; 577 } 578 579 static int 580 sunxi_pinctrl_parse_bias(int phandle) 581 { 582 u_int pull; 583 int bias = -1; 584 585 if (of_hasprop(phandle, "bias-disable")) 586 bias = 0; 587 else if (of_hasprop(phandle, "bias-pull-up")) 588 bias = GPIO_PIN_PULLUP; 589 else if (of_hasprop(phandle, "bias-pull-down")) 590 bias = GPIO_PIN_PULLDOWN; 591 else if (of_getprop_uint32(phandle, "allwinner,pull", &pull) == 0) { 592 switch (pull) { 593 case 0: 594 bias = 0; 595 break; 596 case 1: 597 bias = GPIO_PIN_PULLUP; 598 break; 599 case 2: 600 bias = GPIO_PIN_PULLDOWN; 601 break; 602 } 603 } 604 605 return bias; 606 } 607 608 static int 609 sunxi_pinctrl_parse_drive_strength(int phandle) 610 { 611 int val; 612 613 if (of_getprop_uint32(phandle, "drive-strength", &val) == 0) 614 return val; 615 616 if (of_getprop_uint32(phandle, "allwinner,drive", &val) == 0) 617 return (val + 1) * 10; 618 619 return -1; 620 } 621 622 static int 623 sunxi_pinctrl_set_config(device_t dev, const void *data, size_t len) 624 { 625 struct sunxi_gpio_softc * const sc = device_private(dev); 626 const struct sunxi_gpio_pins *pin_def; 627 int pins_len; 628 629 if (len != 4) 630 return -1; 631 632 const int phandle = fdtbus_get_phandle_from_native(be32dec(data)); 633 634 /* 635 * Required: pins, function 636 * Optional: bias, drive strength 637 */ 638 639 const char *function = sunxi_pinctrl_parse_function(phandle); 640 if (function == NULL) 641 return -1; 642 const char *pins = sunxi_pinctrl_parse_pins(phandle, &pins_len); 643 if (pins == NULL) 644 return -1; 645 646 const int bias = sunxi_pinctrl_parse_bias(phandle); 647 const int drive_strength = sunxi_pinctrl_parse_drive_strength(phandle); 648 649 mutex_enter(&sc->sc_lock); 650 651 for (; pins_len > 0; 652 pins_len -= strlen(pins) + 1, pins += strlen(pins) + 1) { 653 pin_def = sunxi_gpio_lookup_byname(sc, pins); 654 if (pin_def == NULL) { 655 aprint_error_dev(dev, "unknown pin name '%s'\n", pins); 656 continue; 657 } 658 if (sunxi_gpio_setfunc(sc, pin_def, function) != 0) 659 continue; 660 661 if (bias != -1) 662 sunxi_gpio_setpull(sc, pin_def, bias); 663 664 if (drive_strength != -1) 665 sunxi_gpio_setdrv(sc, pin_def, drive_strength); 666 } 667 668 mutex_exit(&sc->sc_lock); 669 670 return 0; 671 } 672 673 static struct fdtbus_pinctrl_controller_func sunxi_pinctrl_funcs = { 674 .set_config = sunxi_pinctrl_set_config, 675 }; 676 677 static int 678 sunxi_gpio_pin_read(void *priv, int pin) 679 { 680 struct sunxi_gpio_softc * const sc = priv; 681 const struct sunxi_gpio_pins *pin_def = &sc->sc_padconf->pins[pin]; 682 uint32_t data; 683 int val; 684 685 KASSERT(pin < sc->sc_padconf->npins); 686 687 const bus_size_t data_reg = SUNXI_GPIO_DATA(pin_def->port); 688 const uint32_t data_mask = __BIT(pin_def->pin); 689 690 /* No lock required for reads */ 691 data = GPIO_READ(sc, data_reg); 692 val = __SHIFTOUT(data, data_mask); 693 694 return val; 695 } 696 697 static void 698 sunxi_gpio_pin_write(void *priv, int pin, int val) 699 { 700 struct sunxi_gpio_softc * const sc = priv; 701 const struct sunxi_gpio_pins *pin_def = &sc->sc_padconf->pins[pin]; 702 uint32_t data; 703 704 KASSERT(pin < sc->sc_padconf->npins); 705 706 const bus_size_t data_reg = SUNXI_GPIO_DATA(pin_def->port); 707 const uint32_t data_mask = __BIT(pin_def->pin); 708 709 mutex_enter(&sc->sc_lock); 710 data = GPIO_READ(sc, data_reg); 711 if (val) 712 data |= data_mask; 713 else 714 data &= ~data_mask; 715 GPIO_WRITE(sc, data_reg, data); 716 mutex_exit(&sc->sc_lock); 717 } 718 719 static void 720 sunxi_gpio_pin_ctl(void *priv, int pin, int flags) 721 { 722 struct sunxi_gpio_softc * const sc = priv; 723 const struct sunxi_gpio_pins *pin_def = &sc->sc_padconf->pins[pin]; 724 725 KASSERT(pin < sc->sc_padconf->npins); 726 727 mutex_enter(&sc->sc_lock); 728 sunxi_gpio_ctl(sc, pin_def, flags); 729 sunxi_gpio_setpull(sc, pin_def, flags); 730 mutex_exit(&sc->sc_lock); 731 } 732 733 static void 734 sunxi_gpio_attach_ports(struct sunxi_gpio_softc *sc) 735 { 736 const struct sunxi_gpio_pins *pin_def; 737 struct gpio_chipset_tag *gp = &sc->sc_gp; 738 struct gpiobus_attach_args gba; 739 u_int pin; 740 741 gp->gp_cookie = sc; 742 gp->gp_pin_read = sunxi_gpio_pin_read; 743 gp->gp_pin_write = sunxi_gpio_pin_write; 744 gp->gp_pin_ctl = sunxi_gpio_pin_ctl; 745 746 const u_int npins = sc->sc_padconf->npins; 747 sc->sc_pins = kmem_zalloc(sizeof(*sc->sc_pins) * npins, KM_SLEEP); 748 749 for (pin = 0; pin < sc->sc_padconf->npins; pin++) { 750 pin_def = &sc->sc_padconf->pins[pin]; 751 sc->sc_pins[pin].pin_num = pin; 752 sc->sc_pins[pin].pin_caps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | 753 GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN; 754 sc->sc_pins[pin].pin_state = sunxi_gpio_pin_read(sc, pin); 755 strlcpy(sc->sc_pins[pin].pin_defname, pin_def->name, 756 sizeof(sc->sc_pins[pin].pin_defname)); 757 } 758 759 memset(&gba, 0, sizeof(gba)); 760 gba.gba_gc = gp; 761 gba.gba_pins = sc->sc_pins; 762 gba.gba_npins = npins; 763 sc->sc_gpiodev = config_found_ia(sc->sc_dev, "gpiobus", &gba, NULL); 764 } 765 766 static int 767 sunxi_gpio_match(device_t parent, cfdata_t cf, void *aux) 768 { 769 struct fdt_attach_args * const faa = aux; 770 771 return of_match_compat_data(faa->faa_phandle, compat_data); 772 } 773 774 static void 775 sunxi_gpio_attach(device_t parent, device_t self, void *aux) 776 { 777 struct sunxi_gpio_softc * const sc = device_private(self); 778 struct fdt_attach_args * const faa = aux; 779 const int phandle = faa->faa_phandle; 780 char intrstr[128]; 781 struct fdtbus_reset *rst; 782 struct clk *clk; 783 bus_addr_t addr; 784 bus_size_t size; 785 int child; 786 787 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 788 aprint_error(": couldn't get registers\n"); 789 return; 790 } 791 792 if ((clk = fdtbus_clock_get_index(phandle, 0)) != NULL) 793 if (clk_enable(clk) != 0) { 794 aprint_error(": couldn't enable clock\n"); 795 return; 796 } 797 798 if ((rst = fdtbus_reset_get_index(phandle, 0)) != NULL) 799 if (fdtbus_reset_deassert(rst) != 0) { 800 aprint_error(": couldn't de-assert reset\n"); 801 return; 802 } 803 804 sc->sc_dev = self; 805 sc->sc_bst = faa->faa_bst; 806 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 807 aprint_error(": couldn't map registers\n"); 808 return; 809 } 810 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); 811 sc->sc_padconf = (void *)of_search_compatible(phandle, compat_data)->data; 812 813 aprint_naive("\n"); 814 aprint_normal(": PIO\n"); 815 816 fdtbus_register_gpio_controller(self, phandle, &sunxi_gpio_funcs); 817 818 for (child = OF_child(phandle); child; child = OF_peer(child)) { 819 if (!of_hasprop(child, "function") || !of_hasprop(child, "pins")) 820 continue; 821 fdtbus_register_pinctrl_config(self, child, &sunxi_pinctrl_funcs); 822 } 823 824 fdtbus_pinctrl_configure(); 825 826 sunxi_gpio_attach_ports(sc); 827 828 /* Disable all external interrupts */ 829 GPIO_WRITE(sc, SUNXI_GPIO_INT_CTL, 0); 830 GPIO_WRITE(sc, SUNXI_GPIO_INT_STATUS, GPIO_READ(sc, SUNXI_GPIO_INT_STATUS)); 831 832 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 833 aprint_error_dev(self, "failed to decode interrupt\n"); 834 return; 835 } 836 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_VM, FDT_INTR_MPSAFE, 837 sunxi_gpio_intr, sc); 838 if (sc->sc_ih == NULL) { 839 aprint_error_dev(self, "failed to establish interrupt on %s\n", 840 intrstr); 841 return; 842 } 843 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 844 fdtbus_register_interrupt_controller(self, phandle, 845 &sunxi_gpio_intrfuncs); 846 } 847
Indexes created Fri Oct 17 03:10:13 GMT 2025