sunxi_gpio.c revision 1.12.2.2
1 /* $NetBSD: sunxi_gpio.c,v 1.12.2.2 2017/08/28 17:51:32 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_soc.h" 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: sunxi_gpio.c,v 1.12.2.2 2017/08/28 17:51:32 skrll Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/intr.h> 38 #include <sys/systm.h> 39 #include <sys/mutex.h> 40 #include <sys/kmem.h> 41 #include <sys/gpio.h> 42 43 #include <dev/fdt/fdtvar.h> 44 #include <dev/gpio/gpiovar.h> 45 46 #include <arm/sunxi/sunxi_gpio.h> 47 48 #define SUNXI_GPIO_PORT(port) (0x24 * (port)) 49 #define SUNXI_GPIO_CFG(port, pin) (SUNXI_GPIO_PORT(port) + 0x00 + (0x4 * ((pin) / 8))) 50 #define SUNXI_GPIO_CFG_PINMASK(pin) (0x7 << (((pin) % 8) * 4)) 51 #define SUNXI_GPIO_DATA(port) (SUNXI_GPIO_PORT(port) + 0x10) 52 #define SUNXI_GPIO_DRV(port, pin) (SUNXI_GPIO_PORT(port) + 0x14 + (0x4 * ((pin) / 16))) 53 #define SUNXI_GPIO_DRV_PINMASK(pin) (0x3 << (((pin) % 16) * 2)) 54 #define SUNXI_GPIO_PULL(port, pin) (SUNXI_GPIO_PORT(port) + 0x1c + (0x4 * ((pin) / 16))) 55 #define SUNXI_GPIO_PULL_DISABLE 0 56 #define SUNXI_GPIO_PULL_UP 1 57 #define SUNXI_GPIO_PULL_DOWN 2 58 #define SUNXI_GPIO_PULL_PINMASK(pin) (0x3 << (((pin) % 16) * 2)) 59 60 static const struct of_compat_data compat_data[] = { 61 #ifdef SOC_SUN5I_A13 62 { "allwinner,sun5i-a13-pinctrl", (uintptr_t)&sun5i_a13_padconf }, 63 #endif 64 #ifdef SOC_SUN6I_A31 65 { "allwinner,sun6i-a31-pinctrl", (uintptr_t)&sun6i_a31_padconf }, 66 { "allwinner,sun6i-a31-r-pinctrl", (uintptr_t)&sun6i_a31_r_padconf }, 67 #endif 68 #ifdef SOC_SUN8I_A83T 69 { "allwinner,sun8i-a83t-pinctrl", (uintptr_t)&sun8i_a83t_padconf }, 70 { "allwinner,sun8i-a83t-r-pinctrl", (uintptr_t)&sun8i_a83t_r_padconf }, 71 #endif 72 #ifdef SOC_SUN8I_H3 73 { "allwinner,sun8i-h3-pinctrl", (uintptr_t)&sun8i_h3_padconf }, 74 { "allwinner,sun8i-h3-r-pinctrl", (uintptr_t)&sun8i_h3_r_padconf }, 75 #endif 76 #ifdef SOC_SUN50I_A64 77 { "allwinner,sun50i-a64-pinctrl", (uintptr_t)&sun50i_a64_padconf }, 78 { "allwinner,sun50i-a64-r-pinctrl", (uintptr_t)&sun50i_a64_r_padconf }, 79 #endif 80 { NULL } 81 }; 82 83 struct sunxi_gpio_softc { 84 device_t sc_dev; 85 bus_space_tag_t sc_bst; 86 bus_space_handle_t sc_bsh; 87 const struct sunxi_gpio_padconf *sc_padconf; 88 kmutex_t sc_lock; 89 90 struct gpio_chipset_tag sc_gp; 91 gpio_pin_t *sc_pins; 92 device_t sc_gpiodev; 93 }; 94 95 struct sunxi_gpio_pin { 96 struct sunxi_gpio_softc *pin_sc; 97 const struct sunxi_gpio_pins *pin_def; 98 int pin_flags; 99 bool pin_actlo; 100 }; 101 102 #define GPIO_READ(sc, reg) \ 103 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 104 #define GPIO_WRITE(sc, reg, val) \ 105 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 106 107 static int sunxi_gpio_match(device_t, cfdata_t, void *); 108 static void sunxi_gpio_attach(device_t, device_t, void *); 109 110 CFATTACH_DECL_NEW(sunxi_gpio, sizeof(struct sunxi_gpio_softc), 111 sunxi_gpio_match, sunxi_gpio_attach, NULL, NULL); 112 113 static const struct sunxi_gpio_pins * 114 sunxi_gpio_lookup(struct sunxi_gpio_softc *sc, uint8_t port, uint8_t pin) 115 { 116 const struct sunxi_gpio_pins *pin_def; 117 u_int n; 118 119 for (n = 0; n < sc->sc_padconf->npins; n++) { 120 pin_def = &sc->sc_padconf->pins[n]; 121 if (pin_def->port == port && pin_def->pin == pin) 122 return pin_def; 123 } 124 125 return NULL; 126 } 127 128 static const struct sunxi_gpio_pins * 129 sunxi_gpio_lookup_byname(struct sunxi_gpio_softc *sc, const char *name) 130 { 131 const struct sunxi_gpio_pins *pin_def; 132 u_int n; 133 134 for (n = 0; n < sc->sc_padconf->npins; n++) { 135 pin_def = &sc->sc_padconf->pins[n]; 136 if (strcmp(pin_def->name, name) == 0) 137 return pin_def; 138 } 139 140 return NULL; 141 } 142 143 static int 144 sunxi_gpio_setfunc(struct sunxi_gpio_softc *sc, 145 const struct sunxi_gpio_pins *pin_def, const char *func) 146 { 147 uint32_t cfg; 148 u_int n; 149 150 KASSERT(mutex_owned(&sc->sc_lock)); 151 152 const bus_size_t cfg_reg = SUNXI_GPIO_CFG(pin_def->port, pin_def->pin); 153 const uint32_t cfg_mask = SUNXI_GPIO_CFG_PINMASK(pin_def->pin); 154 155 for (n = 0; n < SUNXI_GPIO_MAXFUNC; n++) { 156 if (pin_def->functions[n] == NULL) 157 continue; 158 if (strcmp(pin_def->functions[n], func) == 0) { 159 cfg = GPIO_READ(sc, cfg_reg); 160 cfg &= ~cfg_mask; 161 cfg |= __SHIFTIN(n, cfg_mask); 162 #ifdef SUNXI_GPIO_DEBUG 163 device_printf(sc->sc_dev, "P%c%02d cfg %08x -> %08x\n", 164 pin_def->port + 'A', pin_def->pin, GPIO_READ(sc, cfg_reg), cfg); 165 #endif 166 GPIO_WRITE(sc, cfg_reg, cfg); 167 return 0; 168 } 169 } 170 171 /* Function not found */ 172 device_printf(sc->sc_dev, "function '%s' not supported on P%c%02d\n", 173 func, pin_def->port + 'A', pin_def->pin); 174 175 return ENXIO; 176 } 177 178 static int 179 sunxi_gpio_setpull(struct sunxi_gpio_softc *sc, 180 const struct sunxi_gpio_pins *pin_def, int flags) 181 { 182 uint32_t pull; 183 184 KASSERT(mutex_owned(&sc->sc_lock)); 185 186 const bus_size_t pull_reg = SUNXI_GPIO_PULL(pin_def->port, pin_def->pin); 187 const uint32_t pull_mask = SUNXI_GPIO_PULL_PINMASK(pin_def->pin); 188 189 pull = GPIO_READ(sc, pull_reg); 190 pull &= ~pull_mask; 191 if (flags & GPIO_PIN_PULLUP) 192 pull |= __SHIFTIN(SUNXI_GPIO_PULL_UP, pull_mask); 193 else if (flags & GPIO_PIN_PULLDOWN) 194 pull |= __SHIFTIN(SUNXI_GPIO_PULL_DOWN, pull_mask); 195 else 196 pull |= __SHIFTIN(SUNXI_GPIO_PULL_DISABLE, pull_mask); 197 #ifdef SUNXI_GPIO_DEBUG 198 device_printf(sc->sc_dev, "P%c%02d pull %08x -> %08x\n", 199 pin_def->port + 'A', pin_def->pin, GPIO_READ(sc, pull_reg), pull); 200 #endif 201 GPIO_WRITE(sc, pull_reg, pull); 202 203 return 0; 204 } 205 206 static int 207 sunxi_gpio_setdrv(struct sunxi_gpio_softc *sc, 208 const struct sunxi_gpio_pins *pin_def, int drive_strength) 209 { 210 uint32_t drv; 211 212 KASSERT(mutex_owned(&sc->sc_lock)); 213 214 if (drive_strength < 10 || drive_strength > 40) 215 return EINVAL; 216 217 const bus_size_t drv_reg = SUNXI_GPIO_DRV(pin_def->port, pin_def->pin); 218 const uint32_t drv_mask = SUNXI_GPIO_DRV_PINMASK(pin_def->pin); 219 220 drv = GPIO_READ(sc, drv_reg); 221 drv &= ~drv_mask; 222 drv |= __SHIFTIN((drive_strength / 10) - 1, drv_mask); 223 #ifdef SUNXI_GPIO_DEBUG 224 device_printf(sc->sc_dev, "P%c%02d drv %08x -> %08x\n", 225 pin_def->port + 'A', pin_def->pin, GPIO_READ(sc, drv_reg), drv); 226 #endif 227 GPIO_WRITE(sc, drv_reg, drv); 228 229 return 0; 230 } 231 232 static int 233 sunxi_gpio_ctl(struct sunxi_gpio_softc *sc, const struct sunxi_gpio_pins *pin_def, 234 int flags) 235 { 236 KASSERT(mutex_owned(&sc->sc_lock)); 237 238 if (flags & GPIO_PIN_INPUT) 239 return sunxi_gpio_setfunc(sc, pin_def, "gpio_in"); 240 if (flags & GPIO_PIN_OUTPUT) 241 return sunxi_gpio_setfunc(sc, pin_def, "gpio_out"); 242 243 return EINVAL; 244 } 245 246 static void * 247 sunxi_gpio_acquire(device_t dev, const void *data, size_t len, int flags) 248 { 249 struct sunxi_gpio_softc * const sc = device_private(dev); 250 const struct sunxi_gpio_pins *pin_def; 251 struct sunxi_gpio_pin *gpin; 252 const u_int *gpio = data; 253 int error; 254 255 if (len != 16) 256 return NULL; 257 258 const uint8_t port = be32toh(gpio[1]) & 0xff; 259 const uint8_t pin = be32toh(gpio[2]) & 0xff; 260 const bool actlo = be32toh(gpio[3]) & 1; 261 262 pin_def = sunxi_gpio_lookup(sc, port, pin); 263 if (pin_def == NULL) 264 return NULL; 265 266 mutex_enter(&sc->sc_lock); 267 error = sunxi_gpio_ctl(sc, pin_def, flags); 268 mutex_exit(&sc->sc_lock); 269 270 if (error != 0) 271 return NULL; 272 273 gpin = kmem_zalloc(sizeof(*gpin), KM_SLEEP); 274 gpin->pin_sc = sc; 275 gpin->pin_def = pin_def; 276 gpin->pin_flags = flags; 277 gpin->pin_actlo = actlo; 278 279 return gpin; 280 } 281 282 static void 283 sunxi_gpio_release(device_t dev, void *priv) 284 { 285 struct sunxi_gpio_pin *pin = priv; 286 287 sunxi_gpio_ctl(pin->pin_sc, pin->pin_def, GPIO_PIN_INPUT); 288 289 kmem_free(pin, sizeof(*pin)); 290 } 291 292 static int 293 sunxi_gpio_read(device_t dev, void *priv, bool raw) 294 { 295 struct sunxi_gpio_softc * const sc = device_private(dev); 296 struct sunxi_gpio_pin *pin = priv; 297 const struct sunxi_gpio_pins *pin_def = pin->pin_def; 298 uint32_t data; 299 int val; 300 301 KASSERT(sc == pin->pin_sc); 302 303 const bus_size_t data_reg = SUNXI_GPIO_DATA(pin_def->port); 304 const uint32_t data_mask = __BIT(pin_def->pin); 305 306 /* No lock required for reads */ 307 data = GPIO_READ(sc, data_reg); 308 val = __SHIFTOUT(data, data_mask); 309 if (!raw && pin->pin_actlo) 310 val = !val; 311 312 #ifdef SUNXI_GPIO_DEBUG 313 device_printf(dev, "P%c%02d rd %08x (%d %d)\n", 314 pin_def->port + 'A', pin_def->pin, data, 315 __SHIFTOUT(val, data_mask), val); 316 #endif 317 318 return val; 319 } 320 321 static void 322 sunxi_gpio_write(device_t dev, void *priv, int val, bool raw) 323 { 324 struct sunxi_gpio_softc * const sc = device_private(dev); 325 struct sunxi_gpio_pin *pin = priv; 326 const struct sunxi_gpio_pins *pin_def = pin->pin_def; 327 uint32_t data; 328 329 KASSERT(sc == pin->pin_sc); 330 331 const bus_size_t data_reg = SUNXI_GPIO_DATA(pin_def->port); 332 const uint32_t data_mask = __BIT(pin_def->pin); 333 334 if (!raw && pin->pin_actlo) 335 val = !val; 336 337 mutex_enter(&sc->sc_lock); 338 data = GPIO_READ(sc, data_reg); 339 data &= ~data_mask; 340 data |= __SHIFTIN(val, data_mask); 341 #ifdef SUNXI_GPIO_DEBUG 342 device_printf(dev, "P%c%02d wr %08x -> %08x\n", 343 pin_def->port + 'A', pin_def->pin, GPIO_READ(sc, data_reg), data); 344 #endif 345 GPIO_WRITE(sc, data_reg, data); 346 mutex_exit(&sc->sc_lock); 347 } 348 349 static struct fdtbus_gpio_controller_func sunxi_gpio_funcs = { 350 .acquire = sunxi_gpio_acquire, 351 .release = sunxi_gpio_release, 352 .read = sunxi_gpio_read, 353 .write = sunxi_gpio_write, 354 }; 355 356 static const char * 357 sunxi_pinctrl_parse_function(int phandle) 358 { 359 const char *function; 360 361 function = fdtbus_get_string(phandle, "function"); 362 if (function != NULL) 363 return function; 364 365 return fdtbus_get_string(phandle, "allwinner,function"); 366 } 367 368 static const char * 369 sunxi_pinctrl_parse_pins(int phandle, int *pins_len) 370 { 371 int len; 372 373 len = OF_getproplen(phandle, "pins"); 374 if (len > 0) { 375 *pins_len = len; 376 return fdtbus_get_string(phandle, "pins"); 377 } 378 379 len = OF_getproplen(phandle, "allwinner,pins"); 380 if (len > 0) { 381 *pins_len = len; 382 return fdtbus_get_string(phandle, "allwinner,pins"); 383 } 384 385 return NULL; 386 } 387 388 static int 389 sunxi_pinctrl_parse_bias(int phandle) 390 { 391 u_int pull; 392 int bias = -1; 393 394 if (of_hasprop(phandle, "bias-disable")) 395 bias = 0; 396 else if (of_hasprop(phandle, "bias-pull-up")) 397 bias = GPIO_PIN_PULLUP; 398 else if (of_hasprop(phandle, "bias-pull-down")) 399 bias = GPIO_PIN_PULLDOWN; 400 else if (of_getprop_uint32(phandle, "allwinner,pull", &pull) == 0) { 401 switch (pull) { 402 case 0: 403 bias = 0; 404 break; 405 case 1: 406 bias = GPIO_PIN_PULLUP; 407 break; 408 case 2: 409 bias = GPIO_PIN_PULLDOWN; 410 break; 411 } 412 } 413 414 return bias; 415 } 416 417 static int 418 sunxi_pinctrl_parse_drive_strength(int phandle) 419 { 420 int val; 421 422 if (of_getprop_uint32(phandle, "drive-strength", &val) == 0) 423 return val; 424 425 if (of_getprop_uint32(phandle, "allwinner,drive", &val) == 0) 426 return (val + 1) * 10; 427 428 return -1; 429 } 430 431 static int 432 sunxi_pinctrl_set_config(device_t dev, const void *data, size_t len) 433 { 434 struct sunxi_gpio_softc * const sc = device_private(dev); 435 const struct sunxi_gpio_pins *pin_def; 436 int pins_len; 437 438 if (len != 4) 439 return -1; 440 441 const int phandle = fdtbus_get_phandle_from_native(be32dec(data)); 442 443 /* 444 * Required: pins, function 445 * Optional: bias, drive strength 446 */ 447 448 const char *function = sunxi_pinctrl_parse_function(phandle); 449 if (function == NULL) 450 return -1; 451 const char *pins = sunxi_pinctrl_parse_pins(phandle, &pins_len); 452 if (pins == NULL) 453 return -1; 454 455 const int bias = sunxi_pinctrl_parse_bias(phandle); 456 const int drive_strength = sunxi_pinctrl_parse_drive_strength(phandle); 457 458 mutex_enter(&sc->sc_lock); 459 460 for (; pins_len > 0; 461 pins_len -= strlen(pins) + 1, pins += strlen(pins) + 1) { 462 pin_def = sunxi_gpio_lookup_byname(sc, pins); 463 if (pin_def == NULL) { 464 aprint_error_dev(dev, "unknown pin name '%s'\n", pins); 465 continue; 466 } 467 if (sunxi_gpio_setfunc(sc, pin_def, function) != 0) 468 continue; 469 470 if (bias != -1) 471 sunxi_gpio_setpull(sc, pin_def, bias); 472 473 if (drive_strength != -1) 474 sunxi_gpio_setdrv(sc, pin_def, drive_strength); 475 } 476 477 mutex_exit(&sc->sc_lock); 478 479 return 0; 480 } 481 482 static struct fdtbus_pinctrl_controller_func sunxi_pinctrl_funcs = { 483 .set_config = sunxi_pinctrl_set_config, 484 }; 485 486 static int 487 sunxi_gpio_pin_read(void *priv, int pin) 488 { 489 struct sunxi_gpio_softc * const sc = priv; 490 const struct sunxi_gpio_pins *pin_def = &sc->sc_padconf->pins[pin]; 491 uint32_t data; 492 int val; 493 494 KASSERT(pin < sc->sc_padconf->npins); 495 496 const bus_size_t data_reg = SUNXI_GPIO_DATA(pin_def->port); 497 const uint32_t data_mask = __BIT(pin_def->pin); 498 499 /* No lock required for reads */ 500 data = GPIO_READ(sc, data_reg); 501 val = __SHIFTOUT(data, data_mask); 502 503 return val; 504 } 505 506 static void 507 sunxi_gpio_pin_write(void *priv, int pin, int val) 508 { 509 struct sunxi_gpio_softc * const sc = priv; 510 const struct sunxi_gpio_pins *pin_def = &sc->sc_padconf->pins[pin]; 511 uint32_t data; 512 513 KASSERT(pin < sc->sc_padconf->npins); 514 515 const bus_size_t data_reg = SUNXI_GPIO_DATA(pin_def->port); 516 const uint32_t data_mask = __BIT(pin_def->pin); 517 518 mutex_enter(&sc->sc_lock); 519 data = GPIO_READ(sc, data_reg); 520 if (val) 521 data |= data_mask; 522 else 523 data &= ~data_mask; 524 GPIO_WRITE(sc, data_reg, data); 525 mutex_exit(&sc->sc_lock); 526 } 527 528 static void 529 sunxi_gpio_pin_ctl(void *priv, int pin, int flags) 530 { 531 struct sunxi_gpio_softc * const sc = priv; 532 const struct sunxi_gpio_pins *pin_def = &sc->sc_padconf->pins[pin]; 533 534 KASSERT(pin < sc->sc_padconf->npins); 535 536 mutex_enter(&sc->sc_lock); 537 sunxi_gpio_ctl(sc, pin_def, flags); 538 sunxi_gpio_setpull(sc, pin_def, flags); 539 mutex_exit(&sc->sc_lock); 540 } 541 542 static void 543 sunxi_gpio_attach_ports(struct sunxi_gpio_softc *sc) 544 { 545 const struct sunxi_gpio_pins *pin_def; 546 struct gpio_chipset_tag *gp = &sc->sc_gp; 547 struct gpiobus_attach_args gba; 548 u_int pin; 549 550 gp->gp_cookie = sc; 551 gp->gp_pin_read = sunxi_gpio_pin_read; 552 gp->gp_pin_write = sunxi_gpio_pin_write; 553 gp->gp_pin_ctl = sunxi_gpio_pin_ctl; 554 555 const u_int npins = sc->sc_padconf->npins; 556 sc->sc_pins = kmem_zalloc(sizeof(*sc->sc_pins) * npins, KM_SLEEP); 557 558 for (pin = 0; pin < sc->sc_padconf->npins; pin++) { 559 pin_def = &sc->sc_padconf->pins[pin]; 560 sc->sc_pins[pin].pin_num = pin; 561 sc->sc_pins[pin].pin_caps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | 562 GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN; 563 sc->sc_pins[pin].pin_state = sunxi_gpio_pin_read(sc, pin); 564 strlcpy(sc->sc_pins[pin].pin_defname, pin_def->name, 565 sizeof(sc->sc_pins[pin].pin_defname)); 566 } 567 568 memset(&gba, 0, sizeof(gba)); 569 gba.gba_gc = gp; 570 gba.gba_pins = sc->sc_pins; 571 gba.gba_npins = npins; 572 sc->sc_gpiodev = config_found_ia(sc->sc_dev, "gpiobus", &gba, NULL); 573 } 574 575 static int 576 sunxi_gpio_match(device_t parent, cfdata_t cf, void *aux) 577 { 578 struct fdt_attach_args * const faa = aux; 579 580 return of_match_compat_data(faa->faa_phandle, compat_data); 581 } 582 583 static void 584 sunxi_gpio_attach(device_t parent, device_t self, void *aux) 585 { 586 struct sunxi_gpio_softc * const sc = device_private(self); 587 struct fdt_attach_args * const faa = aux; 588 const int phandle = faa->faa_phandle; 589 struct fdtbus_reset *rst; 590 struct clk *clk; 591 bus_addr_t addr; 592 bus_size_t size; 593 int child; 594 595 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 596 aprint_error(": couldn't get registers\n"); 597 return; 598 } 599 600 if ((clk = fdtbus_clock_get_index(phandle, 0)) != NULL) 601 if (clk_enable(clk) != 0) { 602 aprint_error(": couldn't enable clock\n"); 603 return; 604 } 605 606 if ((rst = fdtbus_reset_get_index(phandle, 0)) != NULL) 607 if (fdtbus_reset_deassert(rst) != 0) { 608 aprint_error(": couldn't de-assert reset\n"); 609 return; 610 } 611 612 sc->sc_dev = self; 613 sc->sc_bst = faa->faa_bst; 614 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 615 aprint_error(": couldn't map registers\n"); 616 return; 617 } 618 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); 619 sc->sc_padconf = (void *)of_search_compatible(phandle, compat_data)->data; 620 621 aprint_naive("\n"); 622 aprint_normal(": PIO\n"); 623 624 fdtbus_register_gpio_controller(self, phandle, &sunxi_gpio_funcs); 625 626 for (child = OF_child(phandle); child; child = OF_peer(child)) { 627 if (!of_hasprop(child, "function") || !of_hasprop(child, "pins")) 628 continue; 629 fdtbus_register_pinctrl_config(self, child, &sunxi_pinctrl_funcs); 630 } 631 632 fdtbus_pinctrl_configure(); 633 634 sunxi_gpio_attach_ports(sc); 635 } 636
Indexes created Mon Oct 20 11:09:49 GMT 2025